rk3188.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <hang.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <syscon.h>
  11. #include <asm/io.h>
  12. #include <asm/arch-rockchip/bootrom.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/grf_rk3188.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <linux/err.h>
  17. #define GRF_BASE 0x20008000
  18. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  19. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
  20. [BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
  21. };
  22. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  23. void board_debug_uart_init(void)
  24. {
  25. /* Enable early UART on the RK3188 */
  26. struct rk3188_grf * const grf = (void *)GRF_BASE;
  27. enum {
  28. GPIO1B1_SHIFT = 2,
  29. GPIO1B1_MASK = 3,
  30. GPIO1B1_GPIO = 0,
  31. GPIO1B1_UART2_SOUT,
  32. GPIO1B1_JTAG_TDO,
  33. GPIO1B0_SHIFT = 0,
  34. GPIO1B0_MASK = 3,
  35. GPIO1B0_GPIO = 0,
  36. GPIO1B0_UART2_SIN,
  37. GPIO1B0_JTAG_TDI,
  38. };
  39. rk_clrsetreg(&grf->gpio1b_iomux,
  40. GPIO1B1_MASK << GPIO1B1_SHIFT |
  41. GPIO1B0_MASK << GPIO1B0_SHIFT,
  42. GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
  43. GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
  44. }
  45. #endif
  46. #ifdef CONFIG_SPL_BUILD
  47. int arch_cpu_init(void)
  48. {
  49. struct rk3188_grf *grf;
  50. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  51. if (IS_ERR(grf)) {
  52. pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
  53. return 0;
  54. }
  55. #ifdef CONFIG_ROCKCHIP_USB_UART
  56. rk_clrsetreg(&grf->uoc0_con[0],
  57. SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
  58. 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
  59. 1 << COMMON_ON_N_SHIFT);
  60. rk_clrsetreg(&grf->uoc0_con[2],
  61. SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
  62. rk_clrsetreg(&grf->uoc0_con[3],
  63. OPMODE_MASK | XCVRSELECT_MASK |
  64. TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
  65. OPMODE_NODRIVING << OPMODE_SHIFT |
  66. XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
  67. 1 << TERMSEL_FULLSPEED_SHIFT |
  68. 1 << SUSPENDN_SHIFT);
  69. rk_clrsetreg(&grf->uoc0_con[0],
  70. BYPASSSEL_MASK | BYPASSDMEN_MASK,
  71. 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
  72. #endif
  73. /* enable noc remap to mimic legacy loaders */
  74. rk_clrsetreg(&grf->soc_con0,
  75. NOC_REMAP_MASK << NOC_REMAP_SHIFT,
  76. NOC_REMAP_MASK << NOC_REMAP_SHIFT);
  77. return 0;
  78. }
  79. #endif
  80. #ifdef CONFIG_SPL_BUILD
  81. static int setup_led(void)
  82. {
  83. #ifdef CONFIG_SPL_LED
  84. struct udevice *dev;
  85. char *led_name;
  86. int ret;
  87. led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
  88. if (!led_name)
  89. return 0;
  90. ret = led_get_by_label(led_name, &dev);
  91. if (ret) {
  92. debug("%s: get=%d\n", __func__, ret);
  93. return ret;
  94. }
  95. ret = led_set_on(dev, 1);
  96. if (ret)
  97. return ret;
  98. #endif
  99. return 0;
  100. }
  101. void spl_board_init(void)
  102. {
  103. int ret;
  104. ret = setup_led();
  105. if (ret) {
  106. debug("LED ret=%d\n", ret);
  107. hang();
  108. }
  109. }
  110. #endif