board.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <ram.h>
  12. #include <syscon.h>
  13. #include <asm/cache.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-rockchip/boot_mode.h>
  16. #include <asm/arch-rockchip/clock.h>
  17. #include <asm/arch-rockchip/periph.h>
  18. #include <asm/arch-rockchip/misc.h>
  19. #include <power/regulator.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. __weak int rk_board_late_init(void)
  22. {
  23. return 0;
  24. }
  25. int board_late_init(void)
  26. {
  27. setup_boot_mode();
  28. return rk_board_late_init();
  29. }
  30. int board_init(void)
  31. {
  32. int ret;
  33. #ifdef CONFIG_DM_REGULATOR
  34. ret = regulators_enable_boot_on(false);
  35. if (ret)
  36. debug("%s: Cannot enable boot on regulator\n", __func__);
  37. #endif
  38. return 0;
  39. }
  40. #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  41. void enable_caches(void)
  42. {
  43. /* Enable D-cache. I-cache is already enabled in start.S */
  44. dcache_enable();
  45. }
  46. #endif
  47. #if defined(CONFIG_USB_GADGET)
  48. #include <usb.h>
  49. #if defined(CONFIG_USB_GADGET_DWC2_OTG)
  50. #include <usb/dwc2_udc.h>
  51. static struct dwc2_plat_otg_data otg_data = {
  52. .rx_fifo_sz = 512,
  53. .np_tx_fifo_sz = 16,
  54. .tx_fifo_sz = 128,
  55. };
  56. int board_usb_init(int index, enum usb_init_type init)
  57. {
  58. ofnode node;
  59. const char *mode;
  60. bool matched = false;
  61. /* find the usb_otg node */
  62. node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
  63. while (ofnode_valid(node)) {
  64. mode = ofnode_read_string(node, "dr_mode");
  65. if (mode && strcmp(mode, "otg") == 0) {
  66. matched = true;
  67. break;
  68. }
  69. node = ofnode_by_compatible(node, "snps,dwc2");
  70. }
  71. if (!matched) {
  72. debug("Not found usb_otg device\n");
  73. return -ENODEV;
  74. }
  75. otg_data.regs_otg = ofnode_get_addr(node);
  76. #ifdef CONFIG_ROCKCHIP_RK3288
  77. int ret;
  78. u32 phandle, offset;
  79. ofnode phy_node;
  80. ret = ofnode_read_u32(node, "phys", &phandle);
  81. if (ret)
  82. return ret;
  83. node = ofnode_get_by_phandle(phandle);
  84. if (!ofnode_valid(node)) {
  85. debug("Not found usb phy device\n");
  86. return -ENODEV;
  87. }
  88. phy_node = ofnode_get_parent(node);
  89. if (!ofnode_valid(node)) {
  90. debug("Not found usb phy device\n");
  91. return -ENODEV;
  92. }
  93. otg_data.phy_of_node = phy_node;
  94. ret = ofnode_read_u32(node, "reg", &offset);
  95. if (ret)
  96. return ret;
  97. otg_data.regs_phy = offset +
  98. (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  99. #endif
  100. return dwc2_udc_probe(&otg_data);
  101. }
  102. int board_usb_cleanup(int index, enum usb_init_type init)
  103. {
  104. return 0;
  105. }
  106. #endif /* CONFIG_USB_GADGET_DWC2_OTG */
  107. #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
  108. #include <dwc3-uboot.h>
  109. static struct dwc3_device dwc3_device_data = {
  110. .maximum_speed = USB_SPEED_HIGH,
  111. .base = 0xfe800000,
  112. .dr_mode = USB_DR_MODE_PERIPHERAL,
  113. .index = 0,
  114. .dis_u2_susphy_quirk = 1,
  115. .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
  116. };
  117. int usb_gadget_handle_interrupts(void)
  118. {
  119. dwc3_uboot_handle_interrupt(0);
  120. return 0;
  121. }
  122. int board_usb_init(int index, enum usb_init_type init)
  123. {
  124. return dwc3_uboot_init(&dwc3_device_data);
  125. }
  126. #endif /* CONFIG_USB_DWC3_GADGET */
  127. #endif /* CONFIG_USB_GADGET */
  128. #if CONFIG_IS_ENABLED(FASTBOOT)
  129. int fastboot_set_reboot_flag(void)
  130. {
  131. printf("Setting reboot to fastboot flag ...\n");
  132. /* Set boot mode to fastboot */
  133. writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
  134. return 0;
  135. }
  136. #endif
  137. #ifdef CONFIG_MISC_INIT_R
  138. __weak int misc_init_r(void)
  139. {
  140. const u32 cpuid_offset = 0x7;
  141. const u32 cpuid_length = 0x10;
  142. u8 cpuid[cpuid_length];
  143. int ret;
  144. ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
  145. if (ret)
  146. return ret;
  147. ret = rockchip_cpuid_set(cpuid, cpuid_length);
  148. if (ret)
  149. return ret;
  150. ret = rockchip_setup_macaddr();
  151. return ret;
  152. }
  153. #endif