am35x_musb.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * This file configures the internal USB PHY in AM35X.
  4. *
  5. * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
  6. *
  7. * Based on omap_phy_internal.c code from Linux by
  8. * Hema HK <hemahk@ti.com>
  9. */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/am35x_def.h>
  14. void am35x_musb_reset(struct udevice *dev)
  15. {
  16. /* Reset the musb interface */
  17. clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
  18. 0, USBOTGSS_SW_RST);
  19. clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
  20. USBOTGSS_SW_RST, 0);
  21. }
  22. void am35x_musb_phy_power(struct udevice *dev, u8 on)
  23. {
  24. unsigned long start = get_timer(0);
  25. if (on) {
  26. /*
  27. * Start the on-chip PHY and its PLL.
  28. */
  29. clrsetbits_le32(&am35x_scm_general_regs->devconf2,
  30. CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
  31. CONF2_PHY_PLLON);
  32. debug("Waiting for PHY clock good...\n");
  33. while (!(readl(&am35x_scm_general_regs->devconf2)
  34. & CONF2_PHYCLKGD)) {
  35. if (get_timer(start) > CONFIG_SYS_HZ / 10) {
  36. printf("musb PHY clock good timed out\n");
  37. break;
  38. }
  39. }
  40. } else {
  41. /*
  42. * Power down the on-chip PHY.
  43. */
  44. clrsetbits_le32(&am35x_scm_general_regs->devconf2,
  45. CONF2_PHY_PLLON,
  46. CONF2_PHYPWRDN | CONF2_OTGPWRDN);
  47. }
  48. }
  49. void am35x_musb_clear_irq(struct udevice *dev)
  50. {
  51. clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
  52. 0, USBOTGSS_INT_CLR);
  53. readl(&am35x_scm_general_regs->lvl_intr_clr);
  54. }