emif-common.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * EMIF programming
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. */
  10. #include <common.h>
  11. #include <hang.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <net.h>
  15. #include <asm/emif.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/omap_common.h>
  19. #include <asm/omap_sec_common.h>
  20. #include <asm/utils.h>
  21. #include <linux/compiler.h>
  22. #include <asm/ti-common/ti-edma3.h>
  23. static int emif1_enabled = -1, emif2_enabled = -1;
  24. void set_lpmode_selfrefresh(u32 base)
  25. {
  26. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  27. u32 reg;
  28. reg = readl(&emif->emif_pwr_mgmt_ctrl);
  29. reg &= ~EMIF_REG_LP_MODE_MASK;
  30. reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  31. reg &= ~EMIF_REG_SR_TIM_MASK;
  32. writel(reg, &emif->emif_pwr_mgmt_ctrl);
  33. /* dummy read for the new SR_TIM to be loaded */
  34. readl(&emif->emif_pwr_mgmt_ctrl);
  35. }
  36. void force_emif_self_refresh()
  37. {
  38. set_lpmode_selfrefresh(EMIF1_BASE);
  39. if (!is_dra72x())
  40. set_lpmode_selfrefresh(EMIF2_BASE);
  41. }
  42. inline u32 emif_num(u32 base)
  43. {
  44. if (base == EMIF1_BASE)
  45. return 1;
  46. else if (base == EMIF2_BASE)
  47. return 2;
  48. else
  49. return 0;
  50. }
  51. static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  52. {
  53. u32 mr;
  54. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  55. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  56. writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  57. if (omap_revision() == OMAP4430_ES2_0)
  58. mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  59. else
  60. mr = readl(&emif->emif_lpddr2_mode_reg_data);
  61. debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  62. cs, mr_addr, mr);
  63. if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
  64. ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  65. ((mr & 0xff000000) >> 24) == (mr & 0xff))
  66. return mr & 0xff;
  67. else
  68. return mr;
  69. }
  70. static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  71. {
  72. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  73. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  74. writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  75. writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  76. }
  77. void emif_reset_phy(u32 base)
  78. {
  79. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  80. u32 iodft;
  81. iodft = readl(&emif->emif_iodft_tlgc);
  82. iodft |= EMIF_REG_RESET_PHY_MASK;
  83. writel(iodft, &emif->emif_iodft_tlgc);
  84. }
  85. static void do_lpddr2_init(u32 base, u32 cs)
  86. {
  87. u32 mr_addr;
  88. const struct lpddr2_mr_regs *mr_regs;
  89. get_lpddr2_mr_regs(&mr_regs);
  90. /* Wait till device auto initialization is complete */
  91. while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  92. ;
  93. set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
  94. /*
  95. * tZQINIT = 1 us
  96. * Enough loops assuming a maximum of 2GHz
  97. */
  98. sdelay(2000);
  99. set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
  100. set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
  101. /*
  102. * Enable refresh along with writing MR2
  103. * Encoding of RL in MR2 is (RL - 2)
  104. */
  105. mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  106. set_mr(base, cs, mr_addr, mr_regs->mr2);
  107. if (mr_regs->mr3 > 0)
  108. set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
  109. }
  110. static void lpddr2_init(u32 base, const struct emif_regs *regs)
  111. {
  112. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  113. /* Not NVM */
  114. clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
  115. /*
  116. * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
  117. * when EMIF_SDRAM_CONFIG register is written
  118. */
  119. setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
  120. /*
  121. * Set the SDRAM_CONFIG and PHY_CTRL for the
  122. * un-locked frequency & default RL
  123. */
  124. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  125. writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
  126. do_ext_phy_settings(base, regs);
  127. do_lpddr2_init(base, CS0);
  128. if (regs->sdram_config & EMIF_REG_EBANK_MASK)
  129. do_lpddr2_init(base, CS1);
  130. writel(regs->sdram_config, &emif->emif_sdram_config);
  131. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
  132. /* Enable refresh now */
  133. clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
  134. }
  135. __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
  136. {
  137. }
  138. void emif_update_timings(u32 base, const struct emif_regs *regs)
  139. {
  140. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  141. if (!is_dra7xx())
  142. writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
  143. else
  144. writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
  145. writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
  146. writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
  147. writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
  148. if (omap_revision() == OMAP4430_ES1_0) {
  149. /* ES1 bug EMIF should be in force idle during freq_update */
  150. writel(0, &emif->emif_pwr_mgmt_ctrl);
  151. } else {
  152. writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
  153. writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
  154. }
  155. writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
  156. writel(regs->zq_config, &emif->emif_zq_config);
  157. writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
  158. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
  159. if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
  160. writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
  161. &emif->emif_l3_config);
  162. } else if (omap_revision() >= OMAP4460_ES1_0) {
  163. writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
  164. &emif->emif_l3_config);
  165. } else {
  166. writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
  167. &emif->emif_l3_config);
  168. }
  169. }
  170. #ifndef CONFIG_OMAP44XX
  171. static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
  172. {
  173. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  174. /* keep sdram in self-refresh */
  175. writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
  176. & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
  177. __udelay(130);
  178. /*
  179. * Set invert_clkout (if activated)--DDR_PHYCTRL_1
  180. * Invert clock adds an additional half cycle delay on the
  181. * command interface. The additional half cycle, is usually
  182. * meant to enable leveling in the situation that DQS is later
  183. * than CK on the board.It also helps provide some additional
  184. * margin for leveling.
  185. */
  186. writel(regs->emif_ddr_phy_ctlr_1,
  187. &emif->emif_ddr_phy_ctrl_1);
  188. writel(regs->emif_ddr_phy_ctlr_1,
  189. &emif->emif_ddr_phy_ctrl_1_shdw);
  190. __udelay(130);
  191. writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
  192. & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
  193. /* Launch Full leveling */
  194. writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
  195. /* Wait till full leveling is complete */
  196. readl(&emif->emif_rd_wr_lvl_ctl);
  197. __udelay(130);
  198. /* Read data eye leveling no of samples */
  199. config_data_eye_leveling_samples(base);
  200. /*
  201. * Launch 8 incremental WR_LVL- to compensate for
  202. * PHY limitation.
  203. */
  204. writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
  205. &emif->emif_rd_wr_lvl_ctl);
  206. __udelay(130);
  207. /* Launch Incremental leveling */
  208. writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
  209. __udelay(130);
  210. }
  211. static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
  212. {
  213. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  214. u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
  215. u32 reg, i, phy;
  216. emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
  217. phy = readl(&emif->emif_ddr_phy_ctrl_1);
  218. /* Update PHY_REG_RDDQS_RATIO */
  219. emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
  220. if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
  221. for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
  222. reg = readl(emif_phy_status++);
  223. writel(reg, emif_ext_phy_ctrl_reg++);
  224. writel(reg, emif_ext_phy_ctrl_reg++);
  225. }
  226. /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
  227. emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
  228. emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
  229. if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
  230. for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
  231. reg = readl(emif_phy_status++);
  232. writel(reg, emif_ext_phy_ctrl_reg++);
  233. writel(reg, emif_ext_phy_ctrl_reg++);
  234. }
  235. /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
  236. emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
  237. emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
  238. if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
  239. for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
  240. reg = readl(emif_phy_status++);
  241. writel(reg, emif_ext_phy_ctrl_reg++);
  242. writel(reg, emif_ext_phy_ctrl_reg++);
  243. }
  244. /* Disable Leveling */
  245. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
  246. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
  247. writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
  248. }
  249. static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
  250. {
  251. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  252. /* Clear Error Status */
  253. clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
  254. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
  255. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
  256. clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
  257. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
  258. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
  259. /* Disable refreshed before leveling */
  260. clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
  261. EMIF_REG_INITREF_DIS_MASK);
  262. /* Start Full leveling */
  263. writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
  264. __udelay(300);
  265. /* Check for leveling timeout */
  266. if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
  267. printf("Leveling timeout on EMIF%d\n", emif_num(base));
  268. return;
  269. }
  270. /* Enable refreshes after leveling */
  271. clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
  272. debug("HW leveling success\n");
  273. /*
  274. * Update slave ratios in EXT_PHY_CTRLx registers
  275. * as per HW leveling output
  276. */
  277. update_hwleveling_output(base, regs);
  278. }
  279. static void dra7_reset_ddr_data(u32 base, u32 size)
  280. {
  281. #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
  282. enable_edma3_clocks();
  283. edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size);
  284. disable_edma3_clocks();
  285. #else
  286. memset((void *)base, 0, size);
  287. #endif
  288. }
  289. static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
  290. {
  291. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  292. u32 rgn, rgn_start, size, ctrl_reg;
  293. /* ECC available only on dra76x EMIF1 */
  294. if ((base != EMIF1_BASE) || !is_dra76x())
  295. return;
  296. if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
  297. /* Disable high-order interleaving */
  298. clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
  299. #ifdef CONFIG_DRA7XX
  300. /* Clear the status flags and other history */
  301. writel(readl(&emif->emif_1b_ecc_err_cnt),
  302. &emif->emif_1b_ecc_err_cnt);
  303. writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
  304. writel(0x2, &emif->emif_1b_ecc_err_addr_log);
  305. writel(0x1, &emif->emif_2b_ecc_err_addr_log);
  306. writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
  307. EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
  308. EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
  309. &emif->emif_irqstatus_sys);
  310. #endif
  311. writel(regs->emif_ecc_address_range_1,
  312. &emif->emif_ecc_address_range_1);
  313. writel(regs->emif_ecc_address_range_2,
  314. &emif->emif_ecc_address_range_2);
  315. /* Disable RMW and ECC verification for read accesses */
  316. ctrl_reg = (regs->emif_ecc_ctrl_reg &
  317. ~EMIF_ECC_REG_RMW_EN_MASK) |
  318. EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK;
  319. writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
  320. /* Set region1 memory with 0 */
  321. rgn_start = (regs->emif_ecc_address_range_1 &
  322. EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
  323. rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
  324. size = (regs->emif_ecc_address_range_1 &
  325. EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
  326. if (regs->emif_ecc_ctrl_reg &
  327. EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
  328. dra7_reset_ddr_data(rgn, size);
  329. /* Set region2 memory with 0 */
  330. rgn_start = (regs->emif_ecc_address_range_2 &
  331. EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
  332. rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
  333. size = (regs->emif_ecc_address_range_2 &
  334. EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
  335. if (regs->emif_ecc_ctrl_reg &
  336. EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
  337. dra7_reset_ddr_data(rgn, size);
  338. /* Default value enables RMW and ECC verification */
  339. writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
  340. }
  341. }
  342. static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
  343. {
  344. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  345. if (warm_reset()) {
  346. emif_reset_phy(base);
  347. writel(0x0, &emif->emif_pwr_mgmt_ctrl);
  348. }
  349. do_ext_phy_settings(base, regs);
  350. writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
  351. &emif->emif_sdram_ref_ctrl);
  352. /* Update timing registers */
  353. writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
  354. writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
  355. writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
  356. writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
  357. writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
  358. writel(regs->zq_config, &emif->emif_zq_config);
  359. writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
  360. writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
  361. writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
  362. writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
  363. writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
  364. writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
  365. writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
  366. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  367. __udelay(1000);
  368. writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
  369. if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) {
  370. /*
  371. * Perform Dummy ECC setup just to allow hardware
  372. * leveling of ECC memories
  373. */
  374. if (is_dra76x() && (base == EMIF1_BASE) &&
  375. (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) {
  376. writel(0, &emif->emif_ecc_address_range_1);
  377. writel(0, &emif->emif_ecc_address_range_2);
  378. writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK |
  379. EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK,
  380. &emif->emif_ecc_ctrl_reg);
  381. }
  382. dra7_ddr3_leveling(base, regs);
  383. /* Disable ECC */
  384. if (is_dra76x())
  385. writel(0, &emif->emif_ecc_ctrl_reg);
  386. }
  387. /* Enable ECC as necessary */
  388. dra7_enable_ecc(base, regs);
  389. }
  390. static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
  391. {
  392. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  393. writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
  394. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  395. /*
  396. * Set SDRAM_CONFIG and PHY control registers to locked frequency
  397. * and RL =7. As the default values of the Mode Registers are not
  398. * defined, contents of mode Registers must be fully initialized.
  399. * H/W takes care of this initialization
  400. */
  401. writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
  402. /* Update timing registers */
  403. writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
  404. writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
  405. writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
  406. writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
  407. writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
  408. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  409. do_ext_phy_settings(base, regs);
  410. writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
  411. omap5_ddr3_leveling(base, regs);
  412. }
  413. static void ddr3_init(u32 base, const struct emif_regs *regs)
  414. {
  415. if (is_omap54xx())
  416. omap5_ddr3_init(base, regs);
  417. else
  418. dra7_ddr3_init(base, regs);
  419. }
  420. #endif
  421. #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  422. #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
  423. /*
  424. * Organization and refresh requirements for LPDDR2 devices of different
  425. * types and densities. Derived from JESD209-2 section 2.4
  426. */
  427. const struct lpddr2_addressing addressing_table[] = {
  428. /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
  429. {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
  430. {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
  431. {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
  432. {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
  433. {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
  434. {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
  435. {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
  436. {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
  437. {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
  438. {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
  439. };
  440. static const u32 lpddr2_density_2_size_in_mbytes[] = {
  441. 8, /* 64Mb */
  442. 16, /* 128Mb */
  443. 32, /* 256Mb */
  444. 64, /* 512Mb */
  445. 128, /* 1Gb */
  446. 256, /* 2Gb */
  447. 512, /* 4Gb */
  448. 1024, /* 8Gb */
  449. 2048, /* 16Gb */
  450. 4096 /* 32Gb */
  451. };
  452. /*
  453. * Calculate the period of DDR clock from frequency value and set the
  454. * denominator and numerator in global variables for easy access later
  455. */
  456. static void set_ddr_clk_period(u32 freq)
  457. {
  458. /*
  459. * period = 1/freq
  460. * period_in_ns = 10^9/freq
  461. */
  462. *T_num = 1000000000;
  463. *T_den = freq;
  464. cancel_out(T_num, T_den, 200);
  465. }
  466. /*
  467. * Convert time in nano seconds to number of cycles of DDR clock
  468. */
  469. static inline u32 ns_2_cycles(u32 ns)
  470. {
  471. return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
  472. }
  473. /*
  474. * ns_2_cycles with the difference that the time passed is 2 times the actual
  475. * value(to avoid fractions). The cycles returned is for the original value of
  476. * the timing parameter
  477. */
  478. static inline u32 ns_x2_2_cycles(u32 ns)
  479. {
  480. return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
  481. }
  482. /*
  483. * Find addressing table index based on the device's type(S2 or S4) and
  484. * density
  485. */
  486. s8 addressing_table_index(u8 type, u8 density, u8 width)
  487. {
  488. u8 index;
  489. if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
  490. return -1;
  491. /*
  492. * Look at the way ADDR_TABLE_INDEX* values have been defined
  493. * in emif.h compared to LPDDR2_DENSITY_* values
  494. * The table is layed out in the increasing order of density
  495. * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
  496. * at the end
  497. */
  498. if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
  499. index = ADDR_TABLE_INDEX1GS2;
  500. else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
  501. index = ADDR_TABLE_INDEX2GS2;
  502. else
  503. index = density;
  504. debug("emif: addressing table index %d\n", index);
  505. return index;
  506. }
  507. /*
  508. * Find the the right timing table from the array of timing
  509. * tables of the device using DDR clock frequency
  510. */
  511. static const struct lpddr2_ac_timings *get_timings_table(const struct
  512. lpddr2_ac_timings *const *device_timings,
  513. u32 freq)
  514. {
  515. u32 i, temp, freq_nearest;
  516. const struct lpddr2_ac_timings *timings = 0;
  517. emif_assert(freq <= MAX_LPDDR2_FREQ);
  518. emif_assert(device_timings);
  519. /*
  520. * Start with the maximum allowed frequency - that is always safe
  521. */
  522. freq_nearest = MAX_LPDDR2_FREQ;
  523. /*
  524. * Find the timings table that has the max frequency value:
  525. * i. Above or equal to the DDR frequency - safe
  526. * ii. The lowest that satisfies condition (i) - optimal
  527. */
  528. for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
  529. temp = device_timings[i]->max_freq;
  530. if ((temp >= freq) && (temp <= freq_nearest)) {
  531. freq_nearest = temp;
  532. timings = device_timings[i];
  533. }
  534. }
  535. debug("emif: timings table: %d\n", freq_nearest);
  536. return timings;
  537. }
  538. /*
  539. * Finds the value of emif_sdram_config_reg
  540. * All parameters are programmed based on the device on CS0.
  541. * If there is a device on CS1, it will be same as that on CS0 or
  542. * it will be NVM. We don't support NVM yet.
  543. * If cs1_device pointer is NULL it is assumed that there is no device
  544. * on CS1
  545. */
  546. static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
  547. const struct lpddr2_device_details *cs1_device,
  548. const struct lpddr2_addressing *addressing,
  549. u8 RL)
  550. {
  551. u32 config_reg = 0;
  552. config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
  553. config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
  554. EMIF_REG_IBANK_POS_SHIFT;
  555. config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
  556. config_reg |= RL << EMIF_REG_CL_SHIFT;
  557. config_reg |= addressing->row_sz[cs0_device->io_width] <<
  558. EMIF_REG_ROWSIZE_SHIFT;
  559. config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
  560. config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
  561. EMIF_REG_EBANK_SHIFT;
  562. config_reg |= addressing->col_sz[cs0_device->io_width] <<
  563. EMIF_REG_PAGESIZE_SHIFT;
  564. return config_reg;
  565. }
  566. static u32 get_sdram_ref_ctrl(u32 freq,
  567. const struct lpddr2_addressing *addressing)
  568. {
  569. u32 ref_ctrl = 0, val = 0, freq_khz;
  570. freq_khz = freq / 1000;
  571. /*
  572. * refresh rate to be set is 'tREFI * freq in MHz
  573. * division by 10000 to account for khz and x10 in t_REFI_us_x10
  574. */
  575. val = addressing->t_REFI_us_x10 * freq_khz / 10000;
  576. ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
  577. return ref_ctrl;
  578. }
  579. static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
  580. const struct lpddr2_min_tck *min_tck,
  581. const struct lpddr2_addressing *addressing)
  582. {
  583. u32 tim1 = 0, val = 0;
  584. val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
  585. tim1 |= val << EMIF_REG_T_WTR_SHIFT;
  586. if (addressing->num_banks == BANKS8)
  587. val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
  588. (4 * (*T_num)) - 1;
  589. else
  590. val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
  591. tim1 |= val << EMIF_REG_T_RRD_SHIFT;
  592. val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
  593. tim1 |= val << EMIF_REG_T_RC_SHIFT;
  594. val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
  595. tim1 |= val << EMIF_REG_T_RAS_SHIFT;
  596. val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
  597. tim1 |= val << EMIF_REG_T_WR_SHIFT;
  598. val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
  599. tim1 |= val << EMIF_REG_T_RCD_SHIFT;
  600. val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
  601. tim1 |= val << EMIF_REG_T_RP_SHIFT;
  602. return tim1;
  603. }
  604. static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
  605. const struct lpddr2_min_tck *min_tck)
  606. {
  607. u32 tim2 = 0, val = 0;
  608. val = max(min_tck->tCKE, timings->tCKE) - 1;
  609. tim2 |= val << EMIF_REG_T_CKE_SHIFT;
  610. val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
  611. tim2 |= val << EMIF_REG_T_RTP_SHIFT;
  612. /*
  613. * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
  614. * same value
  615. */
  616. val = ns_2_cycles(timings->tXSR) - 1;
  617. tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
  618. tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
  619. val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
  620. tim2 |= val << EMIF_REG_T_XP_SHIFT;
  621. return tim2;
  622. }
  623. static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
  624. const struct lpddr2_min_tck *min_tck,
  625. const struct lpddr2_addressing *addressing)
  626. {
  627. u32 tim3 = 0, val = 0;
  628. val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
  629. tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
  630. val = ns_2_cycles(timings->tRFCab) - 1;
  631. tim3 |= val << EMIF_REG_T_RFC_SHIFT;
  632. val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
  633. tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
  634. val = ns_2_cycles(timings->tZQCS) - 1;
  635. tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
  636. val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
  637. tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
  638. return tim3;
  639. }
  640. static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
  641. const struct lpddr2_addressing *addressing,
  642. u8 volt_ramp)
  643. {
  644. u32 zq = 0, val = 0;
  645. if (volt_ramp)
  646. val =
  647. EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
  648. addressing->t_REFI_us_x10;
  649. else
  650. val =
  651. EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
  652. addressing->t_REFI_us_x10;
  653. zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
  654. zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
  655. zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
  656. zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
  657. /*
  658. * Assuming that two chipselects have a single calibration resistor
  659. * If there are indeed two calibration resistors, then this flag should
  660. * be enabled to take advantage of dual calibration feature.
  661. * This data should ideally come from board files. But considering
  662. * that none of the boards today have calibration resistors per CS,
  663. * it would be an unnecessary overhead.
  664. */
  665. zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
  666. zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
  667. zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
  668. return zq;
  669. }
  670. static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
  671. const struct lpddr2_addressing *addressing,
  672. u8 is_derated)
  673. {
  674. u32 alert = 0, interval;
  675. interval =
  676. TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
  677. if (is_derated)
  678. interval *= 4;
  679. alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
  680. alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
  681. alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
  682. alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
  683. alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
  684. alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
  685. return alert;
  686. }
  687. static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
  688. {
  689. u32 idle = 0, val = 0;
  690. if (volt_ramp)
  691. val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
  692. else
  693. /*Maximum value in normal conditions - suggested by hw team */
  694. val = 0x1FF;
  695. idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
  696. idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
  697. return idle;
  698. }
  699. static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
  700. {
  701. u32 phy = 0, val = 0;
  702. phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
  703. if (freq <= 100000000)
  704. val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
  705. else if (freq <= 200000000)
  706. val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
  707. else
  708. val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
  709. phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
  710. /* Other fields are constant magic values. Hardcode them together */
  711. phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
  712. EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
  713. return phy;
  714. }
  715. static u32 get_emif_mem_size(u32 base)
  716. {
  717. u32 size_mbytes = 0, temp;
  718. struct emif_device_details dev_details;
  719. struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
  720. u32 emif_nr = emif_num(base);
  721. emif_reset_phy(base);
  722. dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
  723. &cs0_dev_details);
  724. dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
  725. &cs1_dev_details);
  726. emif_reset_phy(base);
  727. if (dev_details.cs0_device_details) {
  728. temp = dev_details.cs0_device_details->density;
  729. size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
  730. }
  731. if (dev_details.cs1_device_details) {
  732. temp = dev_details.cs1_device_details->density;
  733. size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
  734. }
  735. /* convert to bytes */
  736. return size_mbytes << 20;
  737. }
  738. /* Gets the encoding corresponding to a given DMM section size */
  739. u32 get_dmm_section_size_map(u32 section_size)
  740. {
  741. /*
  742. * Section size mapping:
  743. * 0x0: 16-MiB section
  744. * 0x1: 32-MiB section
  745. * 0x2: 64-MiB section
  746. * 0x3: 128-MiB section
  747. * 0x4: 256-MiB section
  748. * 0x5: 512-MiB section
  749. * 0x6: 1-GiB section
  750. * 0x7: 2-GiB section
  751. */
  752. section_size >>= 24; /* divide by 16 MB */
  753. return log_2_n_round_down(section_size);
  754. }
  755. static void emif_calculate_regs(
  756. const struct emif_device_details *emif_dev_details,
  757. u32 freq, struct emif_regs *regs)
  758. {
  759. u32 temp, sys_freq;
  760. const struct lpddr2_addressing *addressing;
  761. const struct lpddr2_ac_timings *timings;
  762. const struct lpddr2_min_tck *min_tck;
  763. const struct lpddr2_device_details *cs0_dev_details =
  764. emif_dev_details->cs0_device_details;
  765. const struct lpddr2_device_details *cs1_dev_details =
  766. emif_dev_details->cs1_device_details;
  767. const struct lpddr2_device_timings *cs0_dev_timings =
  768. emif_dev_details->cs0_device_timings;
  769. emif_assert(emif_dev_details);
  770. emif_assert(regs);
  771. /*
  772. * You can not have a device on CS1 without one on CS0
  773. * So configuring EMIF without a device on CS0 doesn't
  774. * make sense
  775. */
  776. emif_assert(cs0_dev_details);
  777. emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
  778. /*
  779. * If there is a device on CS1 it should be same type as CS0
  780. * (or NVM. But NVM is not supported in this driver yet)
  781. */
  782. emif_assert((cs1_dev_details == NULL) ||
  783. (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
  784. (cs0_dev_details->type == cs1_dev_details->type));
  785. emif_assert(freq <= MAX_LPDDR2_FREQ);
  786. set_ddr_clk_period(freq);
  787. /*
  788. * The device on CS0 is used for all timing calculations
  789. * There is only one set of registers for timings per EMIF. So, if the
  790. * second CS(CS1) has a device, it should have the same timings as the
  791. * device on CS0
  792. */
  793. timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
  794. emif_assert(timings);
  795. min_tck = cs0_dev_timings->min_tck;
  796. temp = addressing_table_index(cs0_dev_details->type,
  797. cs0_dev_details->density,
  798. cs0_dev_details->io_width);
  799. emif_assert((temp >= 0));
  800. addressing = &(addressing_table[temp]);
  801. emif_assert(addressing);
  802. sys_freq = get_sys_clk_freq();
  803. regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
  804. cs1_dev_details,
  805. addressing, RL_BOOT);
  806. regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
  807. cs1_dev_details,
  808. addressing, RL_FINAL);
  809. regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
  810. regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
  811. regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
  812. regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
  813. regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
  814. regs->temp_alert_config =
  815. get_temp_alert_config(cs1_dev_details, addressing, 0);
  816. regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
  817. LPDDR2_VOLTAGE_STABLE);
  818. regs->emif_ddr_phy_ctlr_1_init =
  819. get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
  820. regs->emif_ddr_phy_ctlr_1 =
  821. get_ddr_phy_ctrl_1(freq, RL_FINAL);
  822. regs->freq = freq;
  823. print_timing_reg(regs->sdram_config_init);
  824. print_timing_reg(regs->sdram_config);
  825. print_timing_reg(regs->ref_ctrl);
  826. print_timing_reg(regs->sdram_tim1);
  827. print_timing_reg(regs->sdram_tim2);
  828. print_timing_reg(regs->sdram_tim3);
  829. print_timing_reg(regs->read_idle_ctrl);
  830. print_timing_reg(regs->temp_alert_config);
  831. print_timing_reg(regs->zq_config);
  832. print_timing_reg(regs->emif_ddr_phy_ctlr_1);
  833. print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
  834. }
  835. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  836. #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
  837. const char *get_lpddr2_type(u8 type_id)
  838. {
  839. switch (type_id) {
  840. case LPDDR2_TYPE_S4:
  841. return "LPDDR2-S4";
  842. case LPDDR2_TYPE_S2:
  843. return "LPDDR2-S2";
  844. default:
  845. return NULL;
  846. }
  847. }
  848. const char *get_lpddr2_io_width(u8 width_id)
  849. {
  850. switch (width_id) {
  851. case LPDDR2_IO_WIDTH_8:
  852. return "x8";
  853. case LPDDR2_IO_WIDTH_16:
  854. return "x16";
  855. case LPDDR2_IO_WIDTH_32:
  856. return "x32";
  857. default:
  858. return NULL;
  859. }
  860. }
  861. const char *get_lpddr2_manufacturer(u32 manufacturer)
  862. {
  863. switch (manufacturer) {
  864. case LPDDR2_MANUFACTURER_SAMSUNG:
  865. return "Samsung";
  866. case LPDDR2_MANUFACTURER_QIMONDA:
  867. return "Qimonda";
  868. case LPDDR2_MANUFACTURER_ELPIDA:
  869. return "Elpida";
  870. case LPDDR2_MANUFACTURER_ETRON:
  871. return "Etron";
  872. case LPDDR2_MANUFACTURER_NANYA:
  873. return "Nanya";
  874. case LPDDR2_MANUFACTURER_HYNIX:
  875. return "Hynix";
  876. case LPDDR2_MANUFACTURER_MOSEL:
  877. return "Mosel";
  878. case LPDDR2_MANUFACTURER_WINBOND:
  879. return "Winbond";
  880. case LPDDR2_MANUFACTURER_ESMT:
  881. return "ESMT";
  882. case LPDDR2_MANUFACTURER_SPANSION:
  883. return "Spansion";
  884. case LPDDR2_MANUFACTURER_SST:
  885. return "SST";
  886. case LPDDR2_MANUFACTURER_ZMOS:
  887. return "ZMOS";
  888. case LPDDR2_MANUFACTURER_INTEL:
  889. return "Intel";
  890. case LPDDR2_MANUFACTURER_NUMONYX:
  891. return "Numonyx";
  892. case LPDDR2_MANUFACTURER_MICRON:
  893. return "Micron";
  894. default:
  895. return NULL;
  896. }
  897. }
  898. static void display_sdram_details(u32 emif_nr, u32 cs,
  899. struct lpddr2_device_details *device)
  900. {
  901. const char *mfg_str;
  902. const char *type_str;
  903. char density_str[10];
  904. u32 density;
  905. debug("EMIF%d CS%d\t", emif_nr, cs);
  906. if (!device) {
  907. debug("None\n");
  908. return;
  909. }
  910. mfg_str = get_lpddr2_manufacturer(device->manufacturer);
  911. type_str = get_lpddr2_type(device->type);
  912. density = lpddr2_density_2_size_in_mbytes[device->density];
  913. if ((density / 1024 * 1024) == density) {
  914. density /= 1024;
  915. sprintf(density_str, "%d GB", density);
  916. } else
  917. sprintf(density_str, "%d MB", density);
  918. if (mfg_str && type_str)
  919. debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
  920. }
  921. static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
  922. struct lpddr2_device_details *lpddr2_device)
  923. {
  924. u32 mr = 0, temp;
  925. mr = get_mr(base, cs, LPDDR2_MR0);
  926. if (mr > 0xFF) {
  927. /* Mode register value bigger than 8 bit */
  928. return 0;
  929. }
  930. temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
  931. if (temp) {
  932. /* Not SDRAM */
  933. return 0;
  934. }
  935. temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
  936. if (temp) {
  937. /* DNV supported - But DNV is only supported for NVM */
  938. return 0;
  939. }
  940. mr = get_mr(base, cs, LPDDR2_MR4);
  941. if (mr > 0xFF) {
  942. /* Mode register value bigger than 8 bit */
  943. return 0;
  944. }
  945. mr = get_mr(base, cs, LPDDR2_MR5);
  946. if (mr > 0xFF) {
  947. /* Mode register value bigger than 8 bit */
  948. return 0;
  949. }
  950. if (!get_lpddr2_manufacturer(mr)) {
  951. /* Manufacturer not identified */
  952. return 0;
  953. }
  954. lpddr2_device->manufacturer = mr;
  955. mr = get_mr(base, cs, LPDDR2_MR6);
  956. if (mr >= 0xFF) {
  957. /* Mode register value bigger than 8 bit */
  958. return 0;
  959. }
  960. mr = get_mr(base, cs, LPDDR2_MR7);
  961. if (mr >= 0xFF) {
  962. /* Mode register value bigger than 8 bit */
  963. return 0;
  964. }
  965. mr = get_mr(base, cs, LPDDR2_MR8);
  966. if (mr >= 0xFF) {
  967. /* Mode register value bigger than 8 bit */
  968. return 0;
  969. }
  970. temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
  971. if (!get_lpddr2_type(temp)) {
  972. /* Not SDRAM */
  973. return 0;
  974. }
  975. lpddr2_device->type = temp;
  976. temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
  977. if (temp > LPDDR2_DENSITY_32Gb) {
  978. /* Density not supported */
  979. return 0;
  980. }
  981. lpddr2_device->density = temp;
  982. temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
  983. if (!get_lpddr2_io_width(temp)) {
  984. /* IO width unsupported value */
  985. return 0;
  986. }
  987. lpddr2_device->io_width = temp;
  988. /*
  989. * If all the above tests pass we should
  990. * have a device on this chip-select
  991. */
  992. return 1;
  993. }
  994. struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
  995. struct lpddr2_device_details *lpddr2_dev_details)
  996. {
  997. u32 phy;
  998. u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
  999. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  1000. if (!lpddr2_dev_details)
  1001. return NULL;
  1002. /* Do the minimum init for mode register accesses */
  1003. if (!(running_from_sdram() || warm_reset())) {
  1004. phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
  1005. writel(phy, &emif->emif_ddr_phy_ctrl_1);
  1006. }
  1007. if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
  1008. return NULL;
  1009. display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
  1010. return lpddr2_dev_details;
  1011. }
  1012. #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
  1013. static void do_sdram_init(u32 base)
  1014. {
  1015. const struct emif_regs *regs;
  1016. u32 in_sdram, emif_nr;
  1017. debug(">>do_sdram_init() %x\n", base);
  1018. in_sdram = running_from_sdram();
  1019. emif_nr = (base == EMIF1_BASE) ? 1 : 2;
  1020. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  1021. emif_get_reg_dump(emif_nr, &regs);
  1022. if (!regs) {
  1023. debug("EMIF: reg dump not provided\n");
  1024. return;
  1025. }
  1026. #else
  1027. /*
  1028. * The user has not provided the register values. We need to
  1029. * calculate it based on the timings and the DDR frequency
  1030. */
  1031. struct emif_device_details dev_details;
  1032. struct emif_regs calculated_regs;
  1033. /*
  1034. * Get device details:
  1035. * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
  1036. * - Obtained from user otherwise
  1037. */
  1038. struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
  1039. emif_reset_phy(base);
  1040. dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
  1041. &cs0_dev_details);
  1042. dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
  1043. &cs1_dev_details);
  1044. emif_reset_phy(base);
  1045. /* Return if no devices on this EMIF */
  1046. if (!dev_details.cs0_device_details &&
  1047. !dev_details.cs1_device_details) {
  1048. return;
  1049. }
  1050. /*
  1051. * Get device timings:
  1052. * - Default timings specified by JESD209-2 if
  1053. * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
  1054. * - Obtained from user otherwise
  1055. */
  1056. emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
  1057. &dev_details.cs1_device_timings);
  1058. /* Calculate the register values */
  1059. emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
  1060. regs = &calculated_regs;
  1061. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  1062. /*
  1063. * Initializing the DDR device can not happen from SDRAM.
  1064. * Changing the timing registers in EMIF can happen(going from one
  1065. * OPP to another)
  1066. */
  1067. if (!in_sdram && (!warm_reset() || is_dra7xx())) {
  1068. if (emif_sdram_type(regs->sdram_config) ==
  1069. EMIF_SDRAM_TYPE_LPDDR2)
  1070. lpddr2_init(base, regs);
  1071. #ifndef CONFIG_OMAP44XX
  1072. else
  1073. ddr3_init(base, regs);
  1074. #endif
  1075. }
  1076. #ifdef CONFIG_OMAP54XX
  1077. if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
  1078. EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
  1079. set_lpmode_selfrefresh(base);
  1080. emif_reset_phy(base);
  1081. omap5_ddr3_leveling(base, regs);
  1082. }
  1083. #endif
  1084. /* Write to the shadow registers */
  1085. emif_update_timings(base, regs);
  1086. debug("<<do_sdram_init() %x\n", base);
  1087. }
  1088. void emif_post_init_config(u32 base)
  1089. {
  1090. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  1091. u32 omap_rev = omap_revision();
  1092. /* reset phy on ES2.0 */
  1093. if (omap_rev == OMAP4430_ES2_0)
  1094. emif_reset_phy(base);
  1095. /* Put EMIF back in smart idle on ES1.0 */
  1096. if (omap_rev == OMAP4430_ES1_0)
  1097. writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
  1098. }
  1099. void dmm_init(u32 base)
  1100. {
  1101. const struct dmm_lisa_map_regs *lisa_map_regs;
  1102. u32 i, section, valid;
  1103. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  1104. emif_get_dmm_regs(&lisa_map_regs);
  1105. #else
  1106. u32 emif1_size, emif2_size, mapped_size, section_map = 0;
  1107. u32 section_cnt, sys_addr;
  1108. struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
  1109. mapped_size = 0;
  1110. section_cnt = 3;
  1111. sys_addr = CONFIG_SYS_SDRAM_BASE;
  1112. emif1_size = get_emif_mem_size(EMIF1_BASE);
  1113. emif2_size = get_emif_mem_size(EMIF2_BASE);
  1114. debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
  1115. if (!emif1_size && !emif2_size)
  1116. return;
  1117. /* symmetric interleaved section */
  1118. if (emif1_size && emif2_size) {
  1119. mapped_size = min(emif1_size, emif2_size);
  1120. section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
  1121. section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
  1122. /* only MSB */
  1123. section_map |= (sys_addr >> 24) <<
  1124. EMIF_SYS_ADDR_SHIFT;
  1125. section_map |= get_dmm_section_size_map(mapped_size * 2)
  1126. << EMIF_SYS_SIZE_SHIFT;
  1127. lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
  1128. emif1_size -= mapped_size;
  1129. emif2_size -= mapped_size;
  1130. sys_addr += (mapped_size * 2);
  1131. section_cnt--;
  1132. }
  1133. /*
  1134. * Single EMIF section(we can have a maximum of 1 single EMIF
  1135. * section- either EMIF1 or EMIF2 or none, but not both)
  1136. */
  1137. if (emif1_size) {
  1138. section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
  1139. section_map |= get_dmm_section_size_map(emif1_size)
  1140. << EMIF_SYS_SIZE_SHIFT;
  1141. /* only MSB */
  1142. section_map |= (mapped_size >> 24) <<
  1143. EMIF_SDRC_ADDR_SHIFT;
  1144. /* only MSB */
  1145. section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
  1146. section_cnt--;
  1147. }
  1148. if (emif2_size) {
  1149. section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
  1150. section_map |= get_dmm_section_size_map(emif2_size) <<
  1151. EMIF_SYS_SIZE_SHIFT;
  1152. /* only MSB */
  1153. section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
  1154. /* only MSB */
  1155. section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
  1156. section_cnt--;
  1157. }
  1158. if (section_cnt == 2) {
  1159. /* Only 1 section - either symmetric or single EMIF */
  1160. lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
  1161. lis_map_regs_calculated.dmm_lisa_map_2 = 0;
  1162. lis_map_regs_calculated.dmm_lisa_map_1 = 0;
  1163. } else {
  1164. /* 2 sections - 1 symmetric, 1 single EMIF */
  1165. lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
  1166. lis_map_regs_calculated.dmm_lisa_map_1 = 0;
  1167. }
  1168. /* TRAP for invalid TILER mappings in section 0 */
  1169. lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
  1170. if (omap_revision() >= OMAP4460_ES1_0)
  1171. lis_map_regs_calculated.is_ma_present = 1;
  1172. lisa_map_regs = &lis_map_regs_calculated;
  1173. #endif
  1174. struct dmm_lisa_map_regs *hw_lisa_map_regs =
  1175. (struct dmm_lisa_map_regs *)base;
  1176. writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  1177. writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  1178. writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  1179. writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  1180. writel(lisa_map_regs->dmm_lisa_map_3,
  1181. &hw_lisa_map_regs->dmm_lisa_map_3);
  1182. writel(lisa_map_regs->dmm_lisa_map_2,
  1183. &hw_lisa_map_regs->dmm_lisa_map_2);
  1184. writel(lisa_map_regs->dmm_lisa_map_1,
  1185. &hw_lisa_map_regs->dmm_lisa_map_1);
  1186. writel(lisa_map_regs->dmm_lisa_map_0,
  1187. &hw_lisa_map_regs->dmm_lisa_map_0);
  1188. if (lisa_map_regs->is_ma_present) {
  1189. hw_lisa_map_regs =
  1190. (struct dmm_lisa_map_regs *)MA_BASE;
  1191. writel(lisa_map_regs->dmm_lisa_map_3,
  1192. &hw_lisa_map_regs->dmm_lisa_map_3);
  1193. writel(lisa_map_regs->dmm_lisa_map_2,
  1194. &hw_lisa_map_regs->dmm_lisa_map_2);
  1195. writel(lisa_map_regs->dmm_lisa_map_1,
  1196. &hw_lisa_map_regs->dmm_lisa_map_1);
  1197. writel(lisa_map_regs->dmm_lisa_map_0,
  1198. &hw_lisa_map_regs->dmm_lisa_map_0);
  1199. setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
  1200. }
  1201. /*
  1202. * EMIF should be configured only when
  1203. * memory is mapped on it. Using emif1_enabled
  1204. * and emif2_enabled variables for this.
  1205. */
  1206. emif1_enabled = 0;
  1207. emif2_enabled = 0;
  1208. for (i = 0; i < 4; i++) {
  1209. section = __raw_readl(DMM_BASE + i*4);
  1210. valid = (section & EMIF_SDRC_MAP_MASK) >>
  1211. (EMIF_SDRC_MAP_SHIFT);
  1212. if (valid == 3) {
  1213. emif1_enabled = 1;
  1214. emif2_enabled = 1;
  1215. break;
  1216. }
  1217. if (valid == 1)
  1218. emif1_enabled = 1;
  1219. if (valid == 2)
  1220. emif2_enabled = 1;
  1221. }
  1222. }
  1223. static void do_bug0039_workaround(u32 base)
  1224. {
  1225. u32 val, i, clkctrl;
  1226. struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
  1227. const struct read_write_regs *bug_00339_regs;
  1228. u32 iterations;
  1229. u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
  1230. u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
  1231. if (is_dra7xx())
  1232. phy_status_base++;
  1233. bug_00339_regs = get_bug_regs(&iterations);
  1234. /* Put EMIF in to idle */
  1235. clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
  1236. __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
  1237. /* Copy the phy status registers in to phy ctrl shadow registers */
  1238. for (i = 0; i < iterations; i++) {
  1239. val = __raw_readl(phy_status_base +
  1240. bug_00339_regs[i].read_reg - 1);
  1241. __raw_writel(val, phy_ctrl_base +
  1242. ((bug_00339_regs[i].write_reg - 1) << 1));
  1243. __raw_writel(val, phy_ctrl_base +
  1244. (bug_00339_regs[i].write_reg << 1) - 1);
  1245. }
  1246. /* Disable leveling */
  1247. writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
  1248. __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
  1249. }
  1250. /*
  1251. * SDRAM initialization:
  1252. * SDRAM initialization has two parts:
  1253. * 1. Configuring the SDRAM device
  1254. * 2. Update the AC timings related parameters in the EMIF module
  1255. * (1) should be done only once and should not be done while we are
  1256. * running from SDRAM.
  1257. * (2) can and should be done more than once if OPP changes.
  1258. * Particularly, this may be needed when we boot without SPL and
  1259. * and using Configuration Header(CH). ROM code supports only at 50% OPP
  1260. * at boot (low power boot). So u-boot has to switch to OPP100 and update
  1261. * the frequency. So,
  1262. * Doing (1) and (2) makes sense - first time initialization
  1263. * Doing (2) and not (1) makes sense - OPP change (when using CH)
  1264. * Doing (1) and not (2) doen't make sense
  1265. * See do_sdram_init() for the details
  1266. */
  1267. void sdram_init(void)
  1268. {
  1269. u32 in_sdram, size_prog, size_detect;
  1270. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  1271. u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
  1272. debug(">>sdram_init()\n");
  1273. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  1274. return;
  1275. in_sdram = running_from_sdram();
  1276. debug("in_sdram = %d\n", in_sdram);
  1277. if (!in_sdram) {
  1278. if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
  1279. bypass_dpll((*prcm)->cm_clkmode_dpll_core);
  1280. else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
  1281. writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
  1282. }
  1283. if (!in_sdram)
  1284. dmm_init(DMM_BASE);
  1285. if (emif1_enabled)
  1286. do_sdram_init(EMIF1_BASE);
  1287. if (emif2_enabled)
  1288. do_sdram_init(EMIF2_BASE);
  1289. if (!(in_sdram || warm_reset())) {
  1290. if (emif1_enabled)
  1291. emif_post_init_config(EMIF1_BASE);
  1292. if (emif2_enabled)
  1293. emif_post_init_config(EMIF2_BASE);
  1294. }
  1295. /* for the shadow registers to take effect */
  1296. if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
  1297. freq_update_core();
  1298. /* Do some testing after the init */
  1299. if (!in_sdram) {
  1300. size_prog = omap_sdram_size();
  1301. size_prog = log_2_n_round_down(size_prog);
  1302. size_prog = (1 << size_prog);
  1303. size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  1304. size_prog);
  1305. /* Compare with the size programmed */
  1306. if (size_detect != size_prog) {
  1307. printf("SDRAM: identified size not same as expected"
  1308. " size identified: %x expected: %x\n",
  1309. size_detect,
  1310. size_prog);
  1311. } else
  1312. debug("get_ram_size() successful");
  1313. }
  1314. #if defined(CONFIG_TI_SECURE_DEVICE)
  1315. /*
  1316. * On HS devices, do static EMIF firewall configuration
  1317. * but only do it if not already running in SDRAM
  1318. */
  1319. if (!in_sdram)
  1320. if (0 != secure_emif_reserve())
  1321. hang();
  1322. /* On HS devices, ensure static EMIF firewall APIs are locked */
  1323. if (0 != secure_emif_firewall_lock())
  1324. hang();
  1325. #endif
  1326. if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
  1327. (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
  1328. if (emif1_enabled)
  1329. do_bug0039_workaround(EMIF1_BASE);
  1330. if (emif2_enabled)
  1331. do_bug0039_workaround(EMIF2_BASE);
  1332. }
  1333. debug("<<sdram_init()\n");
  1334. }