clocks-common.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Clock initialization for OMAP4
  5. *
  6. * (C) Copyright 2010
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Aneesh V <aneesh@ti.com>
  10. *
  11. * Based on previous work by:
  12. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  13. * Rajendra Nayak <rnayak@ti.com>
  14. */
  15. #include <common.h>
  16. #include <hang.h>
  17. #include <i2c.h>
  18. #include <init.h>
  19. #include <log.h>
  20. #include <asm/omap_common.h>
  21. #include <asm/gpio.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/utils.h>
  25. #include <asm/omap_gpio.h>
  26. #include <asm/emif.h>
  27. #ifndef CONFIG_SPL_BUILD
  28. /*
  29. * printing to console doesn't work unless
  30. * this code is executed from SPL
  31. */
  32. #define printf(fmt, args...)
  33. #define puts(s)
  34. #endif
  35. const u32 sys_clk_array[8] = {
  36. 12000000, /* 12 MHz */
  37. 20000000, /* 20 MHz */
  38. 16800000, /* 16.8 MHz */
  39. 19200000, /* 19.2 MHz */
  40. 26000000, /* 26 MHz */
  41. 27000000, /* 27 MHz */
  42. 38400000, /* 38.4 MHz */
  43. };
  44. static inline u32 __get_sys_clk_index(void)
  45. {
  46. s8 ind;
  47. /*
  48. * For ES1 the ROM code calibration of sys clock is not reliable
  49. * due to hw issue. So, use hard-coded value. If this value is not
  50. * correct for any board over-ride this function in board file
  51. * From ES2.0 onwards you will get this information from
  52. * CM_SYS_CLKSEL
  53. */
  54. if (omap_revision() == OMAP4430_ES1_0)
  55. ind = OMAP_SYS_CLK_IND_38_4_MHZ;
  56. else {
  57. /* SYS_CLKSEL - 1 to match the dpll param array indices */
  58. ind = (readl((*prcm)->cm_sys_clksel) &
  59. CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
  60. }
  61. return ind;
  62. }
  63. u32 get_sys_clk_index(void)
  64. __attribute__ ((weak, alias("__get_sys_clk_index")));
  65. u32 get_sys_clk_freq(void)
  66. {
  67. u8 index = get_sys_clk_index();
  68. return sys_clk_array[index];
  69. }
  70. void setup_post_dividers(u32 const base, const struct dpll_params *params)
  71. {
  72. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  73. /* Setup post-dividers */
  74. if (params->m2 >= 0)
  75. writel(params->m2, &dpll_regs->cm_div_m2_dpll);
  76. if (params->m3 >= 0)
  77. writel(params->m3, &dpll_regs->cm_div_m3_dpll);
  78. if (params->m4_h11 >= 0)
  79. writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
  80. if (params->m5_h12 >= 0)
  81. writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
  82. if (params->m6_h13 >= 0)
  83. writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
  84. if (params->m7_h14 >= 0)
  85. writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
  86. if (params->h21 >= 0)
  87. writel(params->h21, &dpll_regs->cm_div_h21_dpll);
  88. if (params->h22 >= 0)
  89. writel(params->h22, &dpll_regs->cm_div_h22_dpll);
  90. if (params->h23 >= 0)
  91. writel(params->h23, &dpll_regs->cm_div_h23_dpll);
  92. if (params->h24 >= 0)
  93. writel(params->h24, &dpll_regs->cm_div_h24_dpll);
  94. }
  95. static inline void do_bypass_dpll(u32 const base)
  96. {
  97. struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
  98. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  99. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  100. DPLL_EN_FAST_RELOCK_BYPASS <<
  101. CM_CLKMODE_DPLL_EN_SHIFT);
  102. }
  103. static inline void wait_for_bypass(u32 const base)
  104. {
  105. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  106. if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
  107. LDELAY)) {
  108. printf("Bypassing DPLL failed %x\n", base);
  109. }
  110. }
  111. static inline void do_lock_dpll(u32 const base)
  112. {
  113. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  114. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  115. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  116. DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
  117. }
  118. static inline void wait_for_lock(u32 const base)
  119. {
  120. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  121. if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
  122. &dpll_regs->cm_idlest_dpll, LDELAY)) {
  123. printf("DPLL locking failed for %x\n", base);
  124. hang();
  125. }
  126. }
  127. inline u32 check_for_lock(u32 const base)
  128. {
  129. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  130. u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
  131. return lock;
  132. }
  133. const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
  134. {
  135. u32 sysclk_ind = get_sys_clk_index();
  136. return &dpll_data->mpu[sysclk_ind];
  137. }
  138. const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
  139. {
  140. u32 sysclk_ind = get_sys_clk_index();
  141. return &dpll_data->core[sysclk_ind];
  142. }
  143. const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
  144. {
  145. u32 sysclk_ind = get_sys_clk_index();
  146. return &dpll_data->per[sysclk_ind];
  147. }
  148. const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
  149. {
  150. u32 sysclk_ind = get_sys_clk_index();
  151. return &dpll_data->iva[sysclk_ind];
  152. }
  153. const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
  154. {
  155. u32 sysclk_ind = get_sys_clk_index();
  156. return &dpll_data->usb[sysclk_ind];
  157. }
  158. const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
  159. {
  160. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  161. u32 sysclk_ind = get_sys_clk_index();
  162. return &dpll_data->abe[sysclk_ind];
  163. #else
  164. return dpll_data->abe;
  165. #endif
  166. }
  167. static const struct dpll_params *get_ddr_dpll_params
  168. (struct dplls const *dpll_data)
  169. {
  170. u32 sysclk_ind = get_sys_clk_index();
  171. if (!dpll_data->ddr)
  172. return NULL;
  173. return &dpll_data->ddr[sysclk_ind];
  174. }
  175. #ifdef CONFIG_DRIVER_TI_CPSW
  176. static const struct dpll_params *get_gmac_dpll_params
  177. (struct dplls const *dpll_data)
  178. {
  179. u32 sysclk_ind = get_sys_clk_index();
  180. if (!dpll_data->gmac)
  181. return NULL;
  182. return &dpll_data->gmac[sysclk_ind];
  183. }
  184. #endif
  185. static void do_setup_dpll(u32 const base, const struct dpll_params *params,
  186. u8 lock, char *dpll)
  187. {
  188. u32 temp, M, N;
  189. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  190. if (!params)
  191. return;
  192. temp = readl(&dpll_regs->cm_clksel_dpll);
  193. if (check_for_lock(base)) {
  194. /*
  195. * The Dpll has already been locked by rom code using CH.
  196. * Check if M,N are matching with Ideal nominal opp values.
  197. * If matches, skip the rest otherwise relock.
  198. */
  199. M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
  200. N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
  201. if ((M != (params->m)) || (N != (params->n))) {
  202. debug("\n %s Dpll locked, but not for ideal M = %d,"
  203. "N = %d values, current values are M = %d,"
  204. "N= %d" , dpll, params->m, params->n,
  205. M, N);
  206. } else {
  207. /* Dpll locked with ideal values for nominal opps. */
  208. debug("\n %s Dpll already locked with ideal"
  209. "nominal opp values", dpll);
  210. bypass_dpll(base);
  211. goto setup_post_dividers;
  212. }
  213. }
  214. bypass_dpll(base);
  215. /* Set M & N */
  216. temp &= ~CM_CLKSEL_DPLL_M_MASK;
  217. temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
  218. temp &= ~CM_CLKSEL_DPLL_N_MASK;
  219. temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
  220. writel(temp, &dpll_regs->cm_clksel_dpll);
  221. setup_post_dividers:
  222. setup_post_dividers(base, params);
  223. /* Lock */
  224. if (lock)
  225. do_lock_dpll(base);
  226. /* Wait till the DPLL locks */
  227. if (lock)
  228. wait_for_lock(base);
  229. }
  230. u32 omap_ddr_clk(void)
  231. {
  232. u32 ddr_clk, sys_clk_khz, omap_rev, divider;
  233. const struct dpll_params *core_dpll_params;
  234. omap_rev = omap_revision();
  235. sys_clk_khz = get_sys_clk_freq() / 1000;
  236. core_dpll_params = get_core_dpll_params(*dplls_data);
  237. debug("sys_clk %d\n ", sys_clk_khz * 1000);
  238. /* Find Core DPLL locked frequency first */
  239. ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
  240. (core_dpll_params->n + 1);
  241. if (omap_rev < OMAP5430_ES1_0) {
  242. /*
  243. * DDR frequency is PHY_ROOT_CLK/2
  244. * PHY_ROOT_CLK = Fdpll/2/M2
  245. */
  246. divider = 4;
  247. } else {
  248. /*
  249. * DDR frequency is PHY_ROOT_CLK
  250. * PHY_ROOT_CLK = Fdpll/2/M2
  251. */
  252. divider = 2;
  253. }
  254. ddr_clk = ddr_clk / divider / core_dpll_params->m2;
  255. ddr_clk *= 1000; /* convert to Hz */
  256. debug("ddr_clk %d\n ", ddr_clk);
  257. return ddr_clk;
  258. }
  259. /*
  260. * Lock MPU dpll
  261. *
  262. * Resulting MPU frequencies:
  263. * 4430 ES1.0 : 600 MHz
  264. * 4430 ES2.x : 792 MHz (OPP Turbo)
  265. * 4460 : 920 MHz (OPP Turbo) - DCC disabled
  266. */
  267. void configure_mpu_dpll(void)
  268. {
  269. const struct dpll_params *params;
  270. struct dpll_regs *mpu_dpll_regs;
  271. u32 omap_rev;
  272. omap_rev = omap_revision();
  273. /*
  274. * DCC and clock divider settings for 4460.
  275. * DCC is required, if more than a certain frequency is required.
  276. * For, 4460 > 1GHZ.
  277. * 5430 > 1.4GHZ.
  278. */
  279. if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
  280. mpu_dpll_regs =
  281. (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
  282. bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
  283. clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  284. MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
  285. setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  286. MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
  287. clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
  288. CM_CLKSEL_DCC_EN_MASK);
  289. }
  290. params = get_mpu_dpll_params(*dplls_data);
  291. do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
  292. debug("MPU DPLL locked\n");
  293. }
  294. #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
  295. defined(CONFIG_USB_MUSB_OMAP2PLUS)
  296. static void setup_usb_dpll(void)
  297. {
  298. const struct dpll_params *params;
  299. u32 sys_clk_khz, sd_div, num, den;
  300. sys_clk_khz = get_sys_clk_freq() / 1000;
  301. /*
  302. * USB:
  303. * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
  304. * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
  305. * - where CLKINP is sys_clk in MHz
  306. * Use CLKINP in KHz and adjust the denominator accordingly so
  307. * that we have enough accuracy and at the same time no overflow
  308. */
  309. params = get_usb_dpll_params(*dplls_data);
  310. num = params->m * sys_clk_khz;
  311. den = (params->n + 1) * 250 * 1000;
  312. num += den - 1;
  313. sd_div = num / den;
  314. clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
  315. CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
  316. sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
  317. /* Now setup the dpll with the regular function */
  318. do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
  319. }
  320. #endif
  321. static void setup_dplls(void)
  322. {
  323. u32 temp;
  324. const struct dpll_params *params;
  325. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  326. debug("setup_dplls\n");
  327. /* CORE dpll */
  328. params = get_core_dpll_params(*dplls_data); /* default - safest */
  329. /*
  330. * Do not lock the core DPLL now. Just set it up.
  331. * Core DPLL will be locked after setting up EMIF
  332. * using the FREQ_UPDATE method(freq_update_core())
  333. */
  334. if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
  335. EMIF_SDRAM_TYPE_LPDDR2)
  336. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  337. DPLL_NO_LOCK, "core");
  338. else
  339. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  340. DPLL_LOCK, "core");
  341. /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
  342. temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
  343. (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
  344. (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
  345. writel(temp, (*prcm)->cm_clksel_core);
  346. debug("Core DPLL configured\n");
  347. /* lock PER dpll */
  348. params = get_per_dpll_params(*dplls_data);
  349. do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
  350. params, DPLL_LOCK, "per");
  351. debug("PER DPLL locked\n");
  352. /* MPU dpll */
  353. configure_mpu_dpll();
  354. #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
  355. defined(CONFIG_USB_MUSB_OMAP2PLUS)
  356. setup_usb_dpll();
  357. #endif
  358. params = get_ddr_dpll_params(*dplls_data);
  359. do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
  360. params, DPLL_LOCK, "ddr");
  361. #ifdef CONFIG_DRIVER_TI_CPSW
  362. params = get_gmac_dpll_params(*dplls_data);
  363. do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
  364. DPLL_LOCK, "gmac");
  365. #endif
  366. }
  367. u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
  368. {
  369. u32 offset_code;
  370. volt_offset -= pmic->base_offset;
  371. offset_code = (volt_offset + pmic->step - 1) / pmic->step;
  372. /*
  373. * Offset codes 1-6 all give the base voltage in Palmas
  374. * Offset code 0 switches OFF the SMPS
  375. */
  376. return offset_code + pmic->start_code;
  377. }
  378. void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
  379. {
  380. u32 offset_code;
  381. u32 offset = volt_mv;
  382. int ret = 0;
  383. if (!volt_mv)
  384. return;
  385. pmic->pmic_bus_init();
  386. /* See if we can first get the GPIO if needed */
  387. if (pmic->gpio_en)
  388. ret = gpio_request(pmic->gpio, "PMIC_GPIO");
  389. if (ret < 0) {
  390. printf("%s: gpio %d request failed %d\n", __func__,
  391. pmic->gpio, ret);
  392. return;
  393. }
  394. /* Pull the GPIO low to select SET0 register, while we program SET1 */
  395. if (pmic->gpio_en)
  396. gpio_direction_output(pmic->gpio, 0);
  397. /* convert to uV for better accuracy in the calculations */
  398. offset *= 1000;
  399. offset_code = get_offset_code(offset, pmic);
  400. debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
  401. offset_code);
  402. if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
  403. printf("Scaling voltage failed for 0x%x\n", vcore_reg);
  404. if (pmic->gpio_en)
  405. gpio_direction_output(pmic->gpio, 1);
  406. }
  407. int __weak get_voltrail_opp(int rail_offset)
  408. {
  409. /*
  410. * By default return OPP_NOM for all voltage rails.
  411. */
  412. return OPP_NOM;
  413. }
  414. static u32 optimize_vcore_voltage(struct volts const *v, int opp)
  415. {
  416. u32 val;
  417. if (!v->value[opp])
  418. return 0;
  419. if (!v->efuse.reg[opp])
  420. return v->value[opp];
  421. switch (v->efuse.reg_bits) {
  422. case 16:
  423. val = readw(v->efuse.reg[opp]);
  424. break;
  425. case 32:
  426. val = readl(v->efuse.reg[opp]);
  427. break;
  428. default:
  429. printf("Error: efuse 0x%08x bits=%d unknown\n",
  430. v->efuse.reg[opp], v->efuse.reg_bits);
  431. return v->value[opp];
  432. }
  433. if (!val) {
  434. printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
  435. v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
  436. return v->value[opp];
  437. }
  438. debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
  439. __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
  440. val);
  441. return val;
  442. }
  443. #ifdef CONFIG_IODELAY_RECALIBRATION
  444. void __weak recalibrate_iodelay(void)
  445. {
  446. }
  447. #endif
  448. /*
  449. * Setup the voltages for the main SoC core power domains.
  450. * We start with the maximum voltages allowed here, as set in the corresponding
  451. * vcores_data struct, and then scale (usually down) to the fused values that
  452. * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
  453. * are initialised.
  454. * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
  455. * compiled conditionally. Note that the new code writes the scaled (or zeroed)
  456. * values back to the vcores_data struct for eventual reuse. Zero values mean
  457. * that the corresponding rails are not controlled separately, and are not sent
  458. * to the PMIC.
  459. */
  460. void scale_vcores(struct vcores_data const *vcores)
  461. {
  462. int i, opp, j, ol;
  463. struct volts *pv = (struct volts *)vcores;
  464. struct volts *px;
  465. for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
  466. opp = get_voltrail_opp(i);
  467. debug("%d -> ", pv->value[opp]);
  468. if (pv->value[opp]) {
  469. /* Handle non-empty members only */
  470. pv->value[opp] = optimize_vcore_voltage(pv, opp);
  471. px = (struct volts *)vcores;
  472. j = 0;
  473. while (px < pv) {
  474. /*
  475. * Scan already handled non-empty members to see
  476. * if we have a group and find the max voltage,
  477. * which is set to the first occurance of the
  478. * particular SMPS; the other group voltages are
  479. * zeroed.
  480. */
  481. ol = get_voltrail_opp(j);
  482. if (px->value[ol] &&
  483. (pv->pmic->i2c_slave_addr ==
  484. px->pmic->i2c_slave_addr) &&
  485. (pv->addr == px->addr)) {
  486. /* Same PMIC, same SMPS */
  487. if (pv->value[opp] > px->value[ol])
  488. px->value[ol] = pv->value[opp];
  489. pv->value[opp] = 0;
  490. }
  491. px++;
  492. j++;
  493. }
  494. }
  495. debug("%d\n", pv->value[opp]);
  496. pv++;
  497. }
  498. opp = get_voltrail_opp(VOLT_CORE);
  499. debug("cor: %d\n", vcores->core.value[opp]);
  500. do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
  501. vcores->core.pmic);
  502. /*
  503. * IO delay recalibration should be done immediately after
  504. * adjusting AVS voltages for VDD_CORE_L.
  505. * Respective boards should call __recalibrate_iodelay()
  506. * with proper mux, virtual and manual mode configurations.
  507. */
  508. #ifdef CONFIG_IODELAY_RECALIBRATION
  509. recalibrate_iodelay();
  510. #endif
  511. opp = get_voltrail_opp(VOLT_MPU);
  512. debug("mpu: %d\n", vcores->mpu.value[opp]);
  513. do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
  514. vcores->mpu.pmic);
  515. /* Configure MPU ABB LDO after scale */
  516. abb_setup(vcores->mpu.efuse.reg[opp],
  517. (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
  518. (*prcm)->prm_abbldo_mpu_setup,
  519. (*prcm)->prm_abbldo_mpu_ctrl,
  520. (*prcm)->prm_irqstatus_mpu_2,
  521. vcores->mpu.abb_tx_done_mask,
  522. OMAP_ABB_FAST_OPP);
  523. opp = get_voltrail_opp(VOLT_MM);
  524. debug("mm: %d\n", vcores->mm.value[opp]);
  525. do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
  526. vcores->mm.pmic);
  527. /* Configure MM ABB LDO after scale */
  528. abb_setup(vcores->mm.efuse.reg[opp],
  529. (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
  530. (*prcm)->prm_abbldo_mm_setup,
  531. (*prcm)->prm_abbldo_mm_ctrl,
  532. (*prcm)->prm_irqstatus_mpu,
  533. vcores->mm.abb_tx_done_mask,
  534. OMAP_ABB_FAST_OPP);
  535. opp = get_voltrail_opp(VOLT_GPU);
  536. debug("gpu: %d\n", vcores->gpu.value[opp]);
  537. do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
  538. vcores->gpu.pmic);
  539. /* Configure GPU ABB LDO after scale */
  540. abb_setup(vcores->gpu.efuse.reg[opp],
  541. (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
  542. (*prcm)->prm_abbldo_gpu_setup,
  543. (*prcm)->prm_abbldo_gpu_ctrl,
  544. (*prcm)->prm_irqstatus_mpu,
  545. vcores->gpu.abb_tx_done_mask,
  546. OMAP_ABB_FAST_OPP);
  547. opp = get_voltrail_opp(VOLT_EVE);
  548. debug("eve: %d\n", vcores->eve.value[opp]);
  549. do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
  550. vcores->eve.pmic);
  551. /* Configure EVE ABB LDO after scale */
  552. abb_setup(vcores->eve.efuse.reg[opp],
  553. (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
  554. (*prcm)->prm_abbldo_eve_setup,
  555. (*prcm)->prm_abbldo_eve_ctrl,
  556. (*prcm)->prm_irqstatus_mpu,
  557. vcores->eve.abb_tx_done_mask,
  558. OMAP_ABB_FAST_OPP);
  559. opp = get_voltrail_opp(VOLT_IVA);
  560. debug("iva: %d\n", vcores->iva.value[opp]);
  561. do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
  562. vcores->iva.pmic);
  563. /* Configure IVA ABB LDO after scale */
  564. abb_setup(vcores->iva.efuse.reg[opp],
  565. (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
  566. (*prcm)->prm_abbldo_iva_setup,
  567. (*prcm)->prm_abbldo_iva_ctrl,
  568. (*prcm)->prm_irqstatus_mpu,
  569. vcores->iva.abb_tx_done_mask,
  570. OMAP_ABB_FAST_OPP);
  571. }
  572. static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
  573. {
  574. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  575. enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
  576. debug("Enable clock domain - %x\n", clkctrl_reg);
  577. }
  578. static inline void disable_clock_domain(u32 const clkctrl_reg)
  579. {
  580. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  581. CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
  582. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  583. debug("Disable clock domain - %x\n", clkctrl_reg);
  584. }
  585. static inline void wait_for_clk_enable(u32 clkctrl_addr)
  586. {
  587. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
  588. u32 bound = LDELAY;
  589. while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
  590. (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
  591. clkctrl = readl(clkctrl_addr);
  592. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  593. MODULE_CLKCTRL_IDLEST_SHIFT;
  594. if (--bound == 0) {
  595. printf("Clock enable failed for 0x%x idlest 0x%x\n",
  596. clkctrl_addr, clkctrl);
  597. return;
  598. }
  599. }
  600. }
  601. static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
  602. u32 wait_for_enable)
  603. {
  604. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  605. enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
  606. debug("Enable clock module - %x\n", clkctrl_addr);
  607. if (wait_for_enable)
  608. wait_for_clk_enable(clkctrl_addr);
  609. }
  610. static inline void wait_for_clk_disable(u32 clkctrl_addr)
  611. {
  612. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
  613. u32 bound = LDELAY;
  614. while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
  615. clkctrl = readl(clkctrl_addr);
  616. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  617. MODULE_CLKCTRL_IDLEST_SHIFT;
  618. if (--bound == 0) {
  619. printf("Clock disable failed for 0x%x idlest 0x%x\n",
  620. clkctrl_addr, clkctrl);
  621. return;
  622. }
  623. }
  624. }
  625. static inline void disable_clock_module(u32 const clkctrl_addr,
  626. u32 wait_for_disable)
  627. {
  628. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  629. MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
  630. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  631. debug("Disable clock module - %x\n", clkctrl_addr);
  632. if (wait_for_disable)
  633. wait_for_clk_disable(clkctrl_addr);
  634. }
  635. void freq_update_core(void)
  636. {
  637. u32 freq_config1 = 0;
  638. const struct dpll_params *core_dpll_params;
  639. u32 omap_rev = omap_revision();
  640. core_dpll_params = get_core_dpll_params(*dplls_data);
  641. /* Put EMIF clock domain in sw wakeup mode */
  642. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  643. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  644. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  645. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  646. freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
  647. SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
  648. freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
  649. SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
  650. freq_config1 |= (core_dpll_params->m2 <<
  651. SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
  652. SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
  653. writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
  654. if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
  655. (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
  656. puts("FREQ UPDATE procedure failed!!");
  657. hang();
  658. }
  659. /*
  660. * Putting EMIF in HW_AUTO is seen to be causing issues with
  661. * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
  662. * in OMAP5430 ES1.0 silicon
  663. */
  664. if (omap_rev != OMAP5430_ES1_0) {
  665. /* Put EMIF clock domain back in hw auto mode */
  666. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  667. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  668. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  669. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  670. }
  671. }
  672. void bypass_dpll(u32 const base)
  673. {
  674. do_bypass_dpll(base);
  675. wait_for_bypass(base);
  676. }
  677. void lock_dpll(u32 const base)
  678. {
  679. do_lock_dpll(base);
  680. wait_for_lock(base);
  681. }
  682. static void setup_clocks_for_console(void)
  683. {
  684. /* Do not add any spl_debug prints in this function */
  685. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  686. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  687. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  688. /* Enable all UARTs - console will be on one of them */
  689. clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
  690. MODULE_CLKCTRL_MODULEMODE_MASK,
  691. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  692. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  693. clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
  694. MODULE_CLKCTRL_MODULEMODE_MASK,
  695. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  696. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  697. clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
  698. MODULE_CLKCTRL_MODULEMODE_MASK,
  699. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  700. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  701. clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
  702. MODULE_CLKCTRL_MODULEMODE_MASK,
  703. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  704. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  705. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  706. CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
  707. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  708. }
  709. void do_enable_clocks(u32 const *clk_domains,
  710. u32 const *clk_modules_hw_auto,
  711. u32 const *clk_modules_explicit_en,
  712. u8 wait_for_enable)
  713. {
  714. u32 i, max = 100;
  715. /* Put the clock domains in SW_WKUP mode */
  716. for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
  717. enable_clock_domain(clk_domains[i],
  718. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  719. }
  720. /* Clock modules that need to be put in HW_AUTO */
  721. for (i = 0; (i < max) && clk_modules_hw_auto &&
  722. clk_modules_hw_auto[i]; i++) {
  723. enable_clock_module(clk_modules_hw_auto[i],
  724. MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
  725. wait_for_enable);
  726. };
  727. /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
  728. for (i = 0; (i < max) && clk_modules_explicit_en &&
  729. clk_modules_explicit_en[i]; i++) {
  730. enable_clock_module(clk_modules_explicit_en[i],
  731. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
  732. wait_for_enable);
  733. };
  734. /* Put the clock domains in HW_AUTO mode now */
  735. for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
  736. enable_clock_domain(clk_domains[i],
  737. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  738. }
  739. }
  740. void do_disable_clocks(u32 const *clk_domains,
  741. u32 const *clk_modules_disable,
  742. u8 wait_for_disable)
  743. {
  744. u32 i, max = 100;
  745. /* Clock modules that need to be put in SW_DISABLE */
  746. for (i = 0; (i < max) && clk_modules_disable[i]; i++)
  747. disable_clock_module(clk_modules_disable[i],
  748. wait_for_disable);
  749. /* Put the clock domains in SW_SLEEP mode */
  750. for (i = 0; (i < max) && clk_domains[i]; i++)
  751. disable_clock_domain(clk_domains[i]);
  752. }
  753. /**
  754. * setup_early_clocks() - Setup early clocks needed for SoC
  755. *
  756. * Setup clocks for console, SPL basic initialization clocks and initialize
  757. * the timer. This is invoked prior prcm_init.
  758. */
  759. void setup_early_clocks(void)
  760. {
  761. switch (omap_hw_init_context()) {
  762. case OMAP_INIT_CONTEXT_SPL:
  763. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  764. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  765. setup_clocks_for_console();
  766. enable_basic_clocks();
  767. timer_init();
  768. /* Fall through */
  769. }
  770. }
  771. void prcm_init(void)
  772. {
  773. switch (omap_hw_init_context()) {
  774. case OMAP_INIT_CONTEXT_SPL:
  775. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  776. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  777. scale_vcores(*omap_vcores);
  778. setup_dplls();
  779. setup_warmreset_time();
  780. break;
  781. default:
  782. break;
  783. }
  784. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
  785. enable_basic_uboot_clocks();
  786. }
  787. #if !defined(CONFIG_DM_I2C)
  788. void gpi2c_init(void)
  789. {
  790. static int gpi2c = 1;
  791. if (gpi2c) {
  792. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  793. CONFIG_SYS_OMAP24_I2C_SLAVE);
  794. gpi2c = 0;
  795. }
  796. }
  797. #endif