ddr.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DDR Configuration for AM33xx devices.
  4. *
  5. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/ddr_defs.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. #include <asm/emif.h>
  14. /**
  15. * Base address for EMIF instances
  16. */
  17. static struct emif_reg_struct *emif_reg[2] = {
  18. (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  19. (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  20. /**
  21. * Base addresses for DDR PHY cmd/data regs
  22. */
  23. static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  24. (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  25. (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  26. static struct ddr_data_regs *ddr_data_reg[2] = {
  27. (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  28. (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  29. /**
  30. * Base address for ddr io control instances
  31. */
  32. static struct ddr_cmdtctrl *ioctrl_reg = {
  33. (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  34. static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  35. {
  36. u32 mr;
  37. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  38. writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  39. mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  40. debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  41. if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
  42. ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  43. ((mr & 0xff000000) >> 24) == (mr & 0xff))
  44. return mr & 0xff;
  45. else
  46. return mr;
  47. }
  48. static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  49. {
  50. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  51. writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  52. writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  53. }
  54. static void configure_mr(int nr, u32 cs)
  55. {
  56. u32 mr_addr;
  57. while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  58. ;
  59. set_mr(nr, cs, LPDDR2_MR10, 0x56);
  60. set_mr(nr, cs, LPDDR2_MR1, 0x43);
  61. set_mr(nr, cs, LPDDR2_MR2, 0x2);
  62. mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  63. set_mr(nr, cs, mr_addr, 0x2);
  64. }
  65. /*
  66. * Configure EMIF4D5 registers and MR registers For details about these magic
  67. * values please see the EMIF registers section of the TRM.
  68. */
  69. void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  70. {
  71. #ifdef CONFIG_AM43XX
  72. struct prm_device_inst *prm_device =
  73. (struct prm_device_inst *)PRM_DEVICE_INST;
  74. #endif
  75. writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  76. writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  77. writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  78. writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  79. writel(regs->emif_rd_wr_lvl_rmp_win,
  80. &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  81. writel(regs->emif_rd_wr_lvl_rmp_ctl,
  82. &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  83. writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  84. writel(regs->emif_rd_wr_exec_thresh,
  85. &emif_reg[nr]->emif_rd_wr_exec_thresh);
  86. /*
  87. * for most SOCs these registers won't need to be changed so only
  88. * write to these registers if someone explicitly has set the
  89. * register's value.
  90. */
  91. if(regs->emif_cos_config) {
  92. writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
  93. writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
  94. writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
  95. writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
  96. }
  97. /*
  98. * Sequence to ensure that the PHY is in a known state prior to
  99. * startting hardware leveling. Also acts as to latch some state from
  100. * the EMIF into the PHY.
  101. */
  102. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  103. writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
  104. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  105. clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
  106. EMIF_REG_INITREF_DIS_MASK);
  107. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  108. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  109. /* Wait 1ms because of L3 timeout error */
  110. udelay(1000);
  111. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  112. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  113. #ifdef CONFIG_AM43XX
  114. /*
  115. * Disable EMIF_DEVOFF
  116. * -> Cold Boot: This is just rewriting the default register value.
  117. * -> RTC Resume: Must disable DEVOFF before leveling.
  118. */
  119. writel(0, &prm_device->emif_ctrl);
  120. #endif
  121. /* Perform hardware leveling for DDR3 */
  122. if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
  123. writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
  124. 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
  125. writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
  126. 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
  127. writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  128. /* Enable read leveling */
  129. writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  130. /* Wait 1ms because of L3 timeout error */
  131. udelay(1000);
  132. /*
  133. * Enable full read and write leveling. Wait for read and write
  134. * leveling bit to clear RDWRLVLFULL_START bit 31
  135. */
  136. while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
  137. != 0)
  138. ;
  139. /* Check the timeout register to see if leveling is complete */
  140. if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
  141. puts("DDR3 H/W leveling incomplete with errors\n");
  142. } else {
  143. /* DDR2 */
  144. configure_mr(nr, 0);
  145. configure_mr(nr, 1);
  146. }
  147. }
  148. /**
  149. * Configure SDRAM
  150. */
  151. void config_sdram(const struct emif_regs *regs, int nr)
  152. {
  153. #ifdef CONFIG_TI816X
  154. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  155. writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
  156. writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
  157. writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */
  158. writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */
  159. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  160. #else
  161. if (regs->zq_config) {
  162. writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  163. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  164. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  165. /* Trigger initialization */
  166. writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
  167. /* Wait 1ms because of L3 timeout error */
  168. udelay(1000);
  169. /* Write proper sdram_ref_cref_ctrl value */
  170. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  171. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  172. }
  173. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  174. writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  175. writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  176. /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
  177. if (regs->ocp_config)
  178. writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
  179. #endif
  180. }
  181. /**
  182. * Set SDRAM timings
  183. */
  184. void set_sdram_timings(const struct emif_regs *regs, int nr)
  185. {
  186. writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
  187. writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
  188. writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
  189. writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
  190. writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
  191. writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
  192. }
  193. /*
  194. * Configure EXT PHY registers for software leveling
  195. */
  196. static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
  197. {
  198. u32 *ext_phy_ctrl_base = 0;
  199. u32 *emif_ext_phy_ctrl_base = 0;
  200. __maybe_unused const u32 *ext_phy_ctrl_const_regs;
  201. u32 i = 0;
  202. __maybe_unused u32 size;
  203. ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
  204. emif_ext_phy_ctrl_base =
  205. (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  206. /* Configure external phy control timing registers */
  207. for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
  208. writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
  209. /* Update shadow registers */
  210. writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
  211. }
  212. #ifdef CONFIG_AM43XX
  213. /*
  214. * External phy 6-24 registers do not change with ddr frequency.
  215. * These only need to be set on DDR2 on AM43xx.
  216. */
  217. emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
  218. if (!size)
  219. return;
  220. for (i = 0; i < size; i++) {
  221. writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
  222. /* Update shadow registers */
  223. writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
  224. }
  225. #endif
  226. }
  227. /*
  228. * Configure EXT PHY registers for hardware leveling
  229. */
  230. static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
  231. {
  232. /*
  233. * Enable hardware leveling on the EMIF. For details about these
  234. * magic values please see the EMIF registers section of the TRM.
  235. */
  236. if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
  237. /* PHY_INVERT_CLKOUT = 1 */
  238. writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  239. writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
  240. } else {
  241. /* PHY_INVERT_CLKOUT = 0 */
  242. writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
  243. writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
  244. }
  245. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
  246. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
  247. writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
  248. writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
  249. writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
  250. writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
  251. writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
  252. writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
  253. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
  254. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
  255. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
  256. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
  257. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
  258. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
  259. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
  260. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
  261. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
  262. writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
  263. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
  264. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
  265. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
  266. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
  267. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
  268. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
  269. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
  270. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
  271. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
  272. writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
  273. writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
  274. writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
  275. /*
  276. * Sequence to ensure that the PHY is again in a known state after
  277. * hardware leveling.
  278. */
  279. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  280. writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
  281. writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
  282. }
  283. /**
  284. * Configure DDR PHY
  285. */
  286. void config_ddr_phy(const struct emif_regs *regs, int nr)
  287. {
  288. /*
  289. * Disable initialization and refreshes for now until we finish
  290. * programming EMIF regs and set time between rising edge of
  291. * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
  292. * We currently hardcode a value based on a max expected frequency
  293. * of 400MHz.
  294. */
  295. writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
  296. &emif_reg[nr]->emif_sdram_ref_ctrl);
  297. writel(regs->emif_ddr_phy_ctlr_1,
  298. &emif_reg[nr]->emif_ddr_phy_ctrl_1);
  299. writel(regs->emif_ddr_phy_ctlr_1,
  300. &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
  301. if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
  302. if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
  303. ext_phy_settings_hwlvl(regs, nr);
  304. else
  305. ext_phy_settings_swlvl(regs, nr);
  306. }
  307. }
  308. /**
  309. * Configure DDR CMD control registers
  310. */
  311. void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
  312. {
  313. if (!cmd)
  314. return;
  315. writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
  316. writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
  317. writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
  318. writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
  319. writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
  320. writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
  321. }
  322. /**
  323. * Configure DDR DATA registers
  324. */
  325. void config_ddr_data(const struct ddr_data *data, int nr)
  326. {
  327. int i;
  328. if (!data)
  329. return;
  330. for (i = 0; i < DDR_DATA_REGS_NR; i++) {
  331. writel(data->datardsratio0,
  332. &(ddr_data_reg[nr]+i)->dt0rdsratio0);
  333. writel(data->datawdsratio0,
  334. &(ddr_data_reg[nr]+i)->dt0wdsratio0);
  335. writel(data->datawiratio0,
  336. &(ddr_data_reg[nr]+i)->dt0wiratio0);
  337. writel(data->datagiratio0,
  338. &(ddr_data_reg[nr]+i)->dt0giratio0);
  339. writel(data->datafwsratio0,
  340. &(ddr_data_reg[nr]+i)->dt0fwsratio0);
  341. writel(data->datawrsratio0,
  342. &(ddr_data_reg[nr]+i)->dt0wrsratio0);
  343. }
  344. }
  345. void config_io_ctrl(const struct ctrl_ioregs *ioregs)
  346. {
  347. if (!ioregs)
  348. return;
  349. writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
  350. writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
  351. writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
  352. writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
  353. writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
  354. #ifdef CONFIG_AM43XX
  355. writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
  356. writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
  357. writel(ioregs->emif_sdram_config_ext,
  358. &ioctrl_reg->emif_sdram_config_ext);
  359. #endif
  360. }