board-g12a.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <net.h>
  10. #include <asm/arch/boot.h>
  11. #include <asm/arch/eth.h>
  12. #include <asm/arch/g12a.h>
  13. #include <asm/arch/mem.h>
  14. #include <asm/arch/meson-vpu.h>
  15. #include <asm/io.h>
  16. #include <asm/armv8/mmu.h>
  17. #include <linux/sizes.h>
  18. #include <usb.h>
  19. #include <linux/usb/otg.h>
  20. #include <asm/arch/usb.h>
  21. #include <usb/dwc2_udc.h>
  22. #include <phy.h>
  23. #include <clk.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int meson_get_boot_device(void)
  26. {
  27. return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
  28. }
  29. /* Configure the reserved memory zones exported by the secure registers
  30. * into EFI and DTB reserved memory entries.
  31. */
  32. void meson_init_reserved_memory(void *fdt)
  33. {
  34. u64 bl31_size, bl31_start;
  35. u64 bl32_size, bl32_start;
  36. u32 reg;
  37. /*
  38. * Get ARM Trusted Firmware reserved memory zones in :
  39. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  40. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  41. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  42. */
  43. reg = readl(G12A_AO_SEC_GP_CFG3);
  44. bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
  45. >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  46. bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  47. bl31_start = readl(G12A_AO_SEC_GP_CFG5);
  48. bl32_start = readl(G12A_AO_SEC_GP_CFG4);
  49. /* Add BL31 reserved zone */
  50. if (bl31_start && bl31_size)
  51. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  52. /* Add BL32 reserved zone */
  53. if (bl32_start && bl32_size)
  54. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  55. #if defined(CONFIG_VIDEO_MESON)
  56. meson_vpu_rsv_fb(fdt);
  57. #endif
  58. }
  59. phys_size_t get_effective_memsize(void)
  60. {
  61. /* Size is reported in MiB, convert it in bytes */
  62. return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
  63. >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
  64. }
  65. static struct mm_region g12a_mem_map[] = {
  66. {
  67. .virt = 0x0UL,
  68. .phys = 0x0UL,
  69. .size = 0xf5000000UL,
  70. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  71. PTE_BLOCK_INNER_SHARE
  72. }, {
  73. .virt = 0xf5000000UL,
  74. .phys = 0xf5000000UL,
  75. .size = 0x0b000000UL,
  76. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  77. PTE_BLOCK_NON_SHARE |
  78. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  79. }, {
  80. /* List terminator */
  81. 0,
  82. }
  83. };
  84. struct mm_region *mem_map = g12a_mem_map;
  85. static void g12a_enable_external_mdio(void)
  86. {
  87. writel(0x0, ETH_PHY_CNTL2);
  88. }
  89. static void g12a_enable_internal_mdio(void)
  90. {
  91. /* Fire up the PHY PLL */
  92. writel(0x29c0040a, ETH_PLL_CNTL0);
  93. writel(0x927e0000, ETH_PLL_CNTL1);
  94. writel(0xac5f49e5, ETH_PLL_CNTL2);
  95. writel(0x00000000, ETH_PLL_CNTL3);
  96. writel(0x00000000, ETH_PLL_CNTL4);
  97. writel(0x20200000, ETH_PLL_CNTL5);
  98. writel(0x0000c002, ETH_PLL_CNTL6);
  99. writel(0x00000023, ETH_PLL_CNTL7);
  100. writel(0x39c0040a, ETH_PLL_CNTL0);
  101. writel(0x19c0040a, ETH_PLL_CNTL0);
  102. /* Select the internal MDIO */
  103. writel(0x33000180, ETH_PHY_CNTL0);
  104. writel(0x00074043, ETH_PHY_CNTL1);
  105. writel(0x00000260, ETH_PHY_CNTL2);
  106. }
  107. /* Configure the Ethernet MAC with the requested interface mode
  108. * with some optional flags.
  109. */
  110. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  111. {
  112. switch (mode) {
  113. case PHY_INTERFACE_MODE_RGMII:
  114. case PHY_INTERFACE_MODE_RGMII_ID:
  115. case PHY_INTERFACE_MODE_RGMII_RXID:
  116. case PHY_INTERFACE_MODE_RGMII_TXID:
  117. /* Set RGMII mode */
  118. setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
  119. G12A_ETH_REG_0_TX_PHASE(1) |
  120. G12A_ETH_REG_0_TX_RATIO(4) |
  121. G12A_ETH_REG_0_PHY_CLK_EN |
  122. G12A_ETH_REG_0_CLK_EN);
  123. g12a_enable_external_mdio();
  124. break;
  125. case PHY_INTERFACE_MODE_RMII:
  126. /* Set RMII mode */
  127. out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
  128. G12A_ETH_REG_0_INVERT_RMII_CLK |
  129. G12A_ETH_REG_0_CLK_EN);
  130. /* Use G12A RMII Internal PHY */
  131. if (flags & MESON_USE_INTERNAL_RMII_PHY)
  132. g12a_enable_internal_mdio();
  133. else
  134. g12a_enable_external_mdio();
  135. break;
  136. default:
  137. printf("Invalid Ethernet interface mode\n");
  138. return;
  139. }
  140. /* Enable power gate */
  141. clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
  142. }
  143. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
  144. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  145. static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
  146. int board_usb_init(int index, enum usb_init_type init)
  147. {
  148. struct fdtdec_phandle_args args;
  149. const void *blob = gd->fdt_blob;
  150. int node, dwc2_node;
  151. struct udevice *dev, *clk_dev;
  152. struct clk clk;
  153. int ret;
  154. /* find the usb glue node */
  155. node = fdt_node_offset_by_compatible(blob, -1,
  156. "amlogic,meson-g12a-usb-ctrl");
  157. if (node < 0) {
  158. debug("Not found usb-control node\n");
  159. return -ENODEV;
  160. }
  161. if (!fdtdec_get_is_enabled(blob, node)) {
  162. debug("usb is disabled in the device tree\n");
  163. return -ENODEV;
  164. }
  165. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  166. if (ret) {
  167. debug("Not found usb-control device\n");
  168. return ret;
  169. }
  170. /* find the dwc2 node */
  171. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  172. "amlogic,meson-g12a-usb");
  173. if (dwc2_node < 0) {
  174. debug("Not found dwc2 node\n");
  175. return -ENODEV;
  176. }
  177. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  178. debug("dwc2 is disabled in the device tree\n");
  179. return -ENODEV;
  180. }
  181. meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  182. if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  183. debug("usbotg: can't get base address\n");
  184. return -ENODATA;
  185. }
  186. /* Enable clock */
  187. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  188. "#clock-cells", 0, 0, &args);
  189. if (ret) {
  190. debug("usbotg has no clocks defined in the device tree\n");
  191. return ret;
  192. }
  193. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  194. if (ret)
  195. return ret;
  196. if (args.args_count != 1) {
  197. debug("Can't find clock ID in the device tree\n");
  198. return -ENODATA;
  199. }
  200. clk.dev = clk_dev;
  201. clk.id = args.args[0];
  202. ret = clk_enable(&clk);
  203. if (ret) {
  204. debug("Failed to enable usbotg clock\n");
  205. return ret;
  206. }
  207. meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  208. "g-rx-fifo-size", 0);
  209. meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  210. "g-np-tx-fifo-size", 0);
  211. meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  212. "g-tx-fifo-size", 0);
  213. /* Switch to peripheral mode */
  214. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  215. if (ret)
  216. return ret;
  217. return dwc2_udc_probe(&meson_g12a_dwc2_data);
  218. }
  219. int board_usb_cleanup(int index, enum usb_init_type init)
  220. {
  221. const void *blob = gd->fdt_blob;
  222. struct udevice *dev;
  223. int node;
  224. int ret;
  225. /* find the usb glue node */
  226. node = fdt_node_offset_by_compatible(blob, -1,
  227. "amlogic,meson-g12a-usb-ctrl");
  228. if (node < 0)
  229. return -ENODEV;
  230. if (!fdtdec_get_is_enabled(blob, node))
  231. return -ENODEV;
  232. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  233. if (ret)
  234. return ret;
  235. /* Switch to OTG mode */
  236. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
  237. if (ret)
  238. return ret;
  239. return 0;
  240. }
  241. #endif