init.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <asm/arch/misc.h>
  14. #include <asm/sections.h>
  15. #include <dm/uclass.h>
  16. #include <linux/io.h>
  17. #include <dt-bindings/clock/mt7629-clk.h>
  18. #define L2_CFG_BASE 0x10200000
  19. #define L2_CFG_SIZE 0x1000
  20. #define L2_SHARE_CFG_MP0 0x7f0
  21. #define L2_SHARE_MODE_OFF BIT(8)
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int mtk_pll_early_init(void)
  24. {
  25. unsigned long pll_rates[] = {
  26. [CLK_APMIXED_ARMPLL] = 1250000000,
  27. [CLK_APMIXED_MAINPLL] = 1120000000,
  28. [CLK_APMIXED_UNIV2PLL] = 1200000000,
  29. [CLK_APMIXED_ETH1PLL] = 500000000,
  30. [CLK_APMIXED_ETH2PLL] = 700000000,
  31. [CLK_APMIXED_SGMIPLL] = 650000000,
  32. };
  33. struct udevice *dev;
  34. int ret, i;
  35. ret = uclass_get_device_by_driver(UCLASS_CLK,
  36. DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  37. if (ret)
  38. return ret;
  39. /* configure default rate then enable apmixedsys */
  40. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  41. struct clk clk = { .id = i, .dev = dev };
  42. ret = clk_set_rate(&clk, pll_rates[i]);
  43. if (ret)
  44. return ret;
  45. ret = clk_enable(&clk);
  46. if (ret)
  47. return ret;
  48. }
  49. /* setup mcu bus */
  50. ret = uclass_get_device_by_driver(UCLASS_SYSCON,
  51. DM_GET_DRIVER(mtk_mcucfg), &dev);
  52. if (ret)
  53. return ret;
  54. return 0;
  55. }
  56. int mtk_soc_early_init(void)
  57. {
  58. struct udevice *dev;
  59. int ret;
  60. /* initialize early clocks */
  61. ret = mtk_pll_early_init();
  62. if (ret)
  63. return ret;
  64. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  65. if (ret)
  66. return ret;
  67. return 0;
  68. }
  69. int mach_cpu_init(void)
  70. {
  71. void __iomem *base;
  72. base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
  73. /* disable L2C shared mode */
  74. writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
  75. return 0;
  76. }
  77. int dram_init(void)
  78. {
  79. struct ram_info ram;
  80. struct udevice *dev;
  81. int ret;
  82. ret = uclass_first_device_err(UCLASS_RAM, &dev);
  83. if (ret)
  84. return ret;
  85. ret = ram_get_info(dev, &ram);
  86. if (ret)
  87. return ret;
  88. debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
  89. gd->ram_size = ram.size;
  90. return 0;
  91. }
  92. int print_cpuinfo(void)
  93. {
  94. void __iomem *chipid;
  95. u32 hwcode, swver;
  96. chipid = ioremap(VER_BASE, VER_SIZE);
  97. hwcode = readl(chipid + APHW_CODE);
  98. swver = readl(chipid + APSW_VER);
  99. printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
  100. return 0;
  101. }