ddr3_spd.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: DDR3 SPD configuration
  4. *
  5. * (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <i2c.h>
  10. #include <ddr_spd.h>
  11. #include <asm/arch/ddr3.h>
  12. #include <asm/arch/hardware.h>
  13. #define DUMP_DDR_CONFIG 0 /* set to 1 to debug */
  14. #define debug_ddr_cfg(fmt, args...) \
  15. debug_cond(DUMP_DDR_CONFIG, fmt, ##args)
  16. static void dump_phy_config(struct ddr3_phy_config *ptr)
  17. {
  18. debug_ddr_cfg("\npllcr 0x%08X\n", ptr->pllcr);
  19. debug_ddr_cfg("pgcr1_mask 0x%08X\n", ptr->pgcr1_mask);
  20. debug_ddr_cfg("pgcr1_val 0x%08X\n", ptr->pgcr1_val);
  21. debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0);
  22. debug_ddr_cfg("ptr1 0x%08X\n", ptr->ptr1);
  23. debug_ddr_cfg("ptr2 0x%08X\n", ptr->ptr2);
  24. debug_ddr_cfg("ptr3 0x%08X\n", ptr->ptr3);
  25. debug_ddr_cfg("ptr4 0x%08X\n", ptr->ptr4);
  26. debug_ddr_cfg("dcr_mask 0x%08X\n", ptr->dcr_mask);
  27. debug_ddr_cfg("dcr_val 0x%08X\n", ptr->dcr_val);
  28. debug_ddr_cfg("dtpr0 0x%08X\n", ptr->dtpr0);
  29. debug_ddr_cfg("dtpr1 0x%08X\n", ptr->dtpr1);
  30. debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2);
  31. debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0);
  32. debug_ddr_cfg("mr1 0x%08X\n", ptr->mr1);
  33. debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2);
  34. debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr);
  35. debug_ddr_cfg("pgcr2 0x%08X\n", ptr->pgcr2);
  36. debug_ddr_cfg("zq0cr1 0x%08X\n", ptr->zq0cr1);
  37. debug_ddr_cfg("zq1cr1 0x%08X\n", ptr->zq1cr1);
  38. debug_ddr_cfg("zq2cr1 0x%08X\n", ptr->zq2cr1);
  39. debug_ddr_cfg("pir_v1 0x%08X\n", ptr->pir_v1);
  40. debug_ddr_cfg("pir_v2 0x%08X\n\n", ptr->pir_v2);
  41. };
  42. static void dump_emif_config(struct ddr3_emif_config *ptr)
  43. {
  44. debug_ddr_cfg("\nsdcfg 0x%08X\n", ptr->sdcfg);
  45. debug_ddr_cfg("sdtim1 0x%08X\n", ptr->sdtim1);
  46. debug_ddr_cfg("sdtim2 0x%08X\n", ptr->sdtim2);
  47. debug_ddr_cfg("sdtim3 0x%08X\n", ptr->sdtim3);
  48. debug_ddr_cfg("sdtim4 0x%08X\n", ptr->sdtim4);
  49. debug_ddr_cfg("zqcfg 0x%08X\n", ptr->zqcfg);
  50. debug_ddr_cfg("sdrfc 0x%08X\n\n", ptr->sdrfc);
  51. };
  52. #define TEMP NORMAL_TEMP
  53. #define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */
  54. #define PLLGS_VAL (4000.0 / VBUS_CLKPERIOD) /* 4 us */
  55. #define PLLPD_VAL (1000.0 / VBUS_CLKPERIOD) /* 1 us */
  56. #define PLLLOCK_VAL (100000.0 / VBUS_CLKPERIOD) /* 100 us */
  57. #define PLLRST_VAL (9000.0 / VBUS_CLKPERIOD) /* 9 us */
  58. #define PHYRST_VAL 0x10
  59. #define DDR_TERM RZQ_4_TERM
  60. #define SDRAM_DRIVE RZQ_7_IMP
  61. #define DYN_ODT ODT_DISABLE
  62. enum srt {
  63. NORMAL_TEMP,
  64. EXTENDED_TEMP
  65. };
  66. enum out_impedance {
  67. RZQ_6_IMP = 0,
  68. RZQ_7_IMP
  69. };
  70. enum die_term {
  71. ODT_DISABLE = 0,
  72. RZQ_4_TERM,
  73. RZQ_2_TERM,
  74. RZQ_6_TERM,
  75. RZQ_12_TERM,
  76. RZQ_8_TERM
  77. };
  78. struct ddr3_sodimm {
  79. u32 t_ck;
  80. u32 freqsel;
  81. u32 t_xp;
  82. u32 t_cke;
  83. u32 t_pllpd;
  84. u32 t_pllgs;
  85. u32 t_phyrst;
  86. u32 t_plllock;
  87. u32 t_pllrst;
  88. u32 t_rfc;
  89. u32 t_xs;
  90. u32 t_dinit0;
  91. u32 t_dinit1;
  92. u32 t_dinit2;
  93. u32 t_dinit3;
  94. u32 t_rtp;
  95. u32 t_wtr;
  96. u32 t_rp;
  97. u32 t_rcd;
  98. u32 t_ras;
  99. u32 t_rrd;
  100. u32 t_rc;
  101. u32 t_faw;
  102. u32 t_mrd;
  103. u32 t_mod;
  104. u32 t_wlo;
  105. u32 t_wlmrd;
  106. u32 t_xsdll;
  107. u32 t_xpdll;
  108. u32 t_ckesr;
  109. u32 t_dllk;
  110. u32 t_wr;
  111. u32 t_wr_bin;
  112. u32 cas;
  113. u32 cwl;
  114. u32 asr;
  115. u32 pasr;
  116. u32 t_refprd;
  117. u8 sdram_type;
  118. u8 ibank;
  119. u8 pagesize;
  120. u8 t_rrd2;
  121. u8 t_ras_max;
  122. u8 t_zqcs;
  123. u32 refresh_rate;
  124. u8 t_csta;
  125. u8 rank;
  126. u8 mirrored;
  127. u8 buswidth;
  128. };
  129. static u8 cas_latancy(u16 temp)
  130. {
  131. int loop;
  132. u8 cas_bin = 0;
  133. for (loop = 0; loop < 32; loop += 2, temp >>= 1) {
  134. if (temp & 0x0001)
  135. cas_bin = (loop > 15) ? loop - 15 : loop;
  136. }
  137. return cas_bin;
  138. }
  139. static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf)
  140. {
  141. return (((buf->organization & 0x38) >> 3) + 1) *
  142. (256 << (buf->density_banks & 0xf));
  143. }
  144. static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd,
  145. struct ddr3_spd_cb *spd_cb)
  146. {
  147. u32 mtb, clk_freq;
  148. if ((buf->mem_type != 0x0b) ||
  149. ((buf->density_banks & 0x70) != 0x00))
  150. return 1;
  151. spd->sdram_type = 0x03;
  152. spd->ibank = 0x03;
  153. mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor;
  154. spd->t_ck = buf->tck_min * mtb;
  155. spd_cb->ddrspdclock = 2000000 / spd->t_ck;
  156. clk_freq = spd_cb->ddrspdclock / 2;
  157. spd->rank = ((buf->organization & 0x38) >> 3) + 1;
  158. if (spd->rank > 2)
  159. return 1;
  160. spd->pagesize = (buf->addressing & 0x07) + 1;
  161. if (spd->pagesize > 3)
  162. return 1;
  163. spd->buswidth = 8 << (buf->bus_width & 0x7);
  164. if ((spd->buswidth < 16) || (spd->buswidth > 64))
  165. return 1;
  166. spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1;
  167. printf("DDR3A Speed will be configured for %d Operation.\n",
  168. spd_cb->ddrspdclock);
  169. if (spd_cb->ddrspdclock == 1333) {
  170. spd->t_xp = ((3 * spd->t_ck) > 6000) ?
  171. 3 : ((5999 / spd->t_ck) + 1);
  172. spd->t_cke = ((3 * spd->t_ck) > 5625) ?
  173. 3 : ((5624 / spd->t_ck) + 1);
  174. } else if (spd_cb->ddrspdclock == 1600) {
  175. spd->t_xp = ((3 * spd->t_ck) > 6000) ?
  176. 3 : ((5999 / spd->t_ck) + 1);
  177. spd->t_cke = ((3 * spd->t_ck) > 5000) ?
  178. 3 : ((4999 / spd->t_ck) + 1);
  179. } else {
  180. printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock);
  181. return 1;
  182. }
  183. spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck;
  184. spd->t_ckesr = spd->t_cke + 1;
  185. /* SPD Calculated Values */
  186. spd->cas = cas_latancy((buf->caslat_msb << 8) |
  187. buf->caslat_lsb);
  188. spd->t_wr = (buf->twr_min * mtb) / spd->t_ck;
  189. spd->t_wr_bin = (spd->t_wr / 2) & 0x07;
  190. spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1;
  191. spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1;
  192. spd->t_rp = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1;
  193. spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) *
  194. mtb) / spd->t_ck;
  195. spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) *
  196. mtb) - 1) / spd->t_ck + 1;
  197. spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb /
  198. 1000;
  199. spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck;
  200. spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck;
  201. spd->t_xs = (((spd->t_rfc + 10) * 1000) / spd->t_ck);
  202. spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1;
  203. spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck;
  204. spd->t_rrd2 = ((((buf->tfaw_msb << 8) |
  205. buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1;
  206. /* Hard-coded values */
  207. spd->t_mrd = 0x00;
  208. spd->t_mod = 0x00;
  209. spd->t_wlo = 0x0C;
  210. spd->t_wlmrd = 0x28;
  211. spd->t_xsdll = 0x200;
  212. spd->t_ras_max = 0x0F;
  213. spd->t_csta = 0x05;
  214. spd->t_dllk = 0x200;
  215. /* CAS Write Latency */
  216. if (spd->t_ck >= 2500)
  217. spd->cwl = 0;
  218. else if (spd->t_ck >= 1875)
  219. spd->cwl = 1;
  220. else if (spd->t_ck >= 1500)
  221. spd->cwl = 2;
  222. else if (spd->t_ck >= 1250)
  223. spd->cwl = 3;
  224. else if (spd->t_ck >= 1071)
  225. spd->cwl = 4;
  226. else
  227. spd->cwl = 5;
  228. /* SD:RAM Thermal and Refresh Options */
  229. spd->asr = (buf->therm_ref_opt & 0x04) >> 2;
  230. spd->pasr = (buf->therm_ref_opt & 0x80) >> 7;
  231. spd->t_zqcs = 64;
  232. spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250;
  233. spd->t_refprd = spd->t_refprd / spd->t_ck;
  234. spd->refresh_rate = spd->t_refprd;
  235. spd->t_refprd = spd->t_refprd * 5;
  236. /* Set MISC PHY space registers fields */
  237. if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275))
  238. spd->freqsel = 0x03;
  239. else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385))
  240. spd->freqsel = 0x01;
  241. else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534))
  242. spd->freqsel = 0x00;
  243. spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */
  244. spd->t_dinit1 = spd->t_xs;
  245. spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */
  246. /* Time from ZQ initialization command to first command (1 us) */
  247. spd->t_dinit3 = 1000000 / spd->t_ck;
  248. spd->t_pllgs = PLLGS_VAL + 1;
  249. spd->t_pllpd = PLLPD_VAL + 1;
  250. spd->t_plllock = PLLLOCK_VAL + 1;
  251. spd->t_pllrst = PLLRST_VAL;
  252. spd->t_phyrst = PHYRST_VAL;
  253. spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024;
  254. return 0;
  255. }
  256. static void init_ddr3param(struct ddr3_spd_cb *spd_cb,
  257. struct ddr3_sodimm *spd)
  258. {
  259. spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13;
  260. spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK);
  261. spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23));
  262. spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |
  263. ((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f);
  264. spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |
  265. (spd->t_pllrst & 0x1fff);
  266. spd_cb->phy_cfg.ptr2 = 0;
  267. spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) |
  268. (spd->t_dinit0 & 0xfffff);
  269. spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) |
  270. (spd->t_dinit2 & 0x3ffff);
  271. spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK;
  272. spd_cb->phy_cfg.dcr_val = 1 << 10;
  273. if (spd->mirrored) {
  274. spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK;
  275. spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29);
  276. }
  277. spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 |
  278. (spd->t_rrd & 0xf) << 22 |
  279. (spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 |
  280. (spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 |
  281. (spd->t_rtp & 0xf);
  282. spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 |
  283. (spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 |
  284. (spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 |
  285. (spd->t_mrd & 0x3);
  286. spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 |
  287. (spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15;
  288. spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ?
  289. spd->t_xp : spd->t_xpdll) &
  290. 0x1f) << 10;
  291. spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ?
  292. spd->t_xs : spd->t_xsdll) &
  293. 0x3ff);
  294. spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |
  295. 0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 |
  296. (spd->cas & 0x01) << 2;
  297. spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 |
  298. ((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 |
  299. (DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 |
  300. (SDRAM_DRIVE & 1) << 1 | 0 << 0;
  301. spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 |
  302. (spd->cwl & 7) << 3 | (spd->pasr & 7);
  303. spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;
  304. spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);
  305. spd_cb->phy_cfg.zq0cr1 = 0x0000005D;
  306. spd_cb->phy_cfg.zq1cr1 = 0x0000005B;
  307. spd_cb->phy_cfg.zq2cr1 = 0x0000005B;
  308. spd_cb->phy_cfg.pir_v1 = 0x00000033;
  309. spd_cb->phy_cfg.pir_v2 = 0x0000FF81;
  310. /* EMIF Registers */
  311. spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 |
  312. (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 |
  313. (spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 |
  314. (spd->buswidth & 3) << 12 | (spd->pagesize & 3);
  315. if (spd->rank == 2)
  316. spd_cb->emif_cfg.sdcfg |= 1 << 3;
  317. spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 |
  318. ((spd->t_ras - 1) & 0x7f) << 18 |
  319. ((spd->t_rc - 1) & 0xff) << 10 |
  320. (spd->t_rrd2 & 0x3f) << 4 |
  321. ((spd->t_wtr - 1) & 0xf);
  322. spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 |
  323. ((spd->t_rcd - 1) & 0x1f);
  324. spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 |
  325. ((spd->t_xs - 1) & 0x3ff) << 18 |
  326. ((spd->t_xsdll - 1) & 0x3ff) << 8 |
  327. ((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf);
  328. spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 |
  329. ((spd->t_ckesr - 1) & 0xf) << 24 |
  330. ((spd->t_zqcs - 1) & 0xff) << 16 |
  331. ((spd->t_rfc - 1) & 0x3ff) << 4 |
  332. (spd->t_ras_max & 0xf);
  333. spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff;
  334. /* TODO zqcfg value fixed ,May be required correction for K2E evm. */
  335. spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200;
  336. }
  337. static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
  338. {
  339. int ret;
  340. #ifndef CONFIG_DM_I2C
  341. int old_bus;
  342. i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
  343. old_bus = i2c_get_bus_num();
  344. i2c_set_bus_num(1);
  345. ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256);
  346. i2c_set_bus_num(old_bus);
  347. #else
  348. struct udevice *dev;
  349. ret = i2c_get_chip_for_busnum(1, 0x53, 1, &dev);
  350. if (!ret)
  351. ret = dm_i2c_read(dev, 0, (unsigned char *)spd_params, 256);
  352. #endif
  353. if (ret) {
  354. printf("Cannot read DIMM params\n");
  355. return 1;
  356. }
  357. if (ddr3_spd_check(spd_params))
  358. return 1;
  359. return 0;
  360. }
  361. int ddr3_get_size(void)
  362. {
  363. ddr3_spd_eeprom_t spd_params;
  364. if (ddr3_read_spd(&spd_params))
  365. return 0;
  366. return ddr3_get_size_in_mb(&spd_params) / 1024;
  367. }
  368. int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb)
  369. {
  370. struct ddr3_sodimm spd;
  371. ddr3_spd_eeprom_t spd_params;
  372. memset(&spd, 0, sizeof(spd));
  373. if (ddr3_read_spd(&spd_params))
  374. return 1;
  375. if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) {
  376. printf("Timing caclulation error\n");
  377. return 1;
  378. }
  379. strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18);
  380. spd_cb->dimm_name[18] = '\0';
  381. init_ddr3param(spd_cb, &spd);
  382. dump_emif_config(&spd_cb->emif_cfg);
  383. dump_phy_config(&spd_cb->phy_cfg);
  384. return 0;
  385. }