soc.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/mach-imx/hab.h>
  15. #define PMC0_BASE_ADDR 0x410a1000
  16. #define PMC0_CTRL 0x28
  17. #define PMC0_CTRL_LDOEN BIT(31)
  18. #define PMC0_CTRL_LDOOKDIS BIT(30)
  19. #define PMC0_CTRL_PMC1ON BIT(24)
  20. #define PMC1_BASE_ADDR 0x40400000
  21. #define PMC1_RUN 0x8
  22. #define PMC1_STOP 0x10
  23. #define PMC1_VLPS 0x14
  24. #define PMC1_LDOVL_SHIFT 16
  25. #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
  26. #define PMC1_LDOVL_900 0x1e
  27. #define PMC1_LDOVL_950 0x23
  28. #define PMC1_STATUS 0x20
  29. #define PMC1_STATUS_LDOVLF BIT(8)
  30. static char *get_reset_cause(char *);
  31. #if defined(CONFIG_IMX_HAB)
  32. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  33. .bank = 29,
  34. .word = 6,
  35. };
  36. #endif
  37. #define ROM_VERSION_ADDR 0x80
  38. u32 get_cpu_rev(void)
  39. {
  40. /* Check the ROM version for cpu revision */
  41. u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
  42. return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
  43. }
  44. #ifdef CONFIG_REVISION_TAG
  45. u32 __weak get_board_rev(void)
  46. {
  47. return get_cpu_rev();
  48. }
  49. #endif
  50. enum bt_mode get_boot_mode(void)
  51. {
  52. u32 bt0_cfg = 0;
  53. bt0_cfg = readl(CMC0_RBASE + 0x40);
  54. bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
  55. if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
  56. /* No low power boot */
  57. if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
  58. return DUAL_BOOT;
  59. else
  60. return SINGLE_BOOT;
  61. }
  62. return LOW_POWER_BOOT;
  63. }
  64. int arch_cpu_init(void)
  65. {
  66. return 0;
  67. }
  68. #ifdef CONFIG_BOARD_POSTCLK_INIT
  69. int board_postclk_init(void)
  70. {
  71. return 0;
  72. }
  73. #endif
  74. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  75. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  76. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  77. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  78. static void disable_wdog(u32 wdog_base)
  79. {
  80. writel(UNLOCK_WORD0, (wdog_base + 0x04));
  81. writel(UNLOCK_WORD1, (wdog_base + 0x04));
  82. writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
  83. writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
  84. writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
  85. writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
  86. writel(REFRESH_WORD1, (wdog_base + 0x04));
  87. }
  88. void init_wdog(void)
  89. {
  90. /*
  91. * ROM will configure WDOG1, disable it or enable it
  92. * depending on FUSE. The update bit is set for reconfigurable.
  93. * We have to use unlock sequence to reconfigure it.
  94. * WDOG2 is not touched by ROM, so it will have default value
  95. * which is enabled. We can directly configure it.
  96. * To simplify the codes, we still use same reconfigure
  97. * process as WDOG1. Because the update bit is not set for
  98. * WDOG2, the unlock sequence won't take effect really.
  99. * It actually directly configure the wdog.
  100. * In this function, we will disable both WDOG1 and WDOG2,
  101. * and set update bit for both. So that kernel can reconfigure them.
  102. */
  103. disable_wdog(WDG1_RBASE);
  104. disable_wdog(WDG2_RBASE);
  105. }
  106. static bool ldo_mode_is_enabled(void)
  107. {
  108. unsigned int reg;
  109. reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
  110. if (reg & PMC0_CTRL_LDOEN)
  111. return true;
  112. else
  113. return false;
  114. }
  115. #if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
  116. #if defined(CONFIG_LDO_ENABLED_MODE)
  117. static void init_ldo_mode(void)
  118. {
  119. unsigned int reg;
  120. if (ldo_mode_is_enabled())
  121. return;
  122. /* Set LDOOKDIS */
  123. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
  124. /* Set LDOVL to 0.95V in PMC1_RUN */
  125. reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
  126. reg &= ~PMC1_LDOVL_MASK;
  127. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  128. writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
  129. /* Wait for LDOVLF to be cleared */
  130. reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
  131. while (reg & PMC1_STATUS_LDOVLF)
  132. ;
  133. /* Set LDOVL to 0.95V in PMC1_STOP */
  134. reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
  135. reg &= ~PMC1_LDOVL_MASK;
  136. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  137. writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
  138. /* Set LDOVL to 0.90V in PMC1_VLPS */
  139. reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
  140. reg &= ~PMC1_LDOVL_MASK;
  141. reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
  142. writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
  143. /* Set LDOEN bit */
  144. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
  145. /* Set the PMC1ON bit */
  146. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
  147. }
  148. #endif
  149. void s_init(void)
  150. {
  151. /* Disable wdog */
  152. init_wdog();
  153. /* clock configuration. */
  154. clock_init();
  155. if (soc_rev() < CHIP_REV_2_0) {
  156. /* enable dumb pmic */
  157. writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
  158. }
  159. #if defined(CONFIG_LDO_ENABLED_MODE)
  160. init_ldo_mode();
  161. #endif
  162. return;
  163. }
  164. #endif
  165. #ifndef CONFIG_ULP_WATCHDOG
  166. void reset_cpu(ulong addr)
  167. {
  168. setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
  169. while (1)
  170. ;
  171. }
  172. #endif
  173. #if defined(CONFIG_DISPLAY_CPUINFO)
  174. const char *get_imx_type(u32 imxtype)
  175. {
  176. return "7ULP";
  177. }
  178. int print_cpuinfo(void)
  179. {
  180. u32 cpurev;
  181. char cause[18];
  182. cpurev = get_cpu_rev();
  183. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  184. get_imx_type((cpurev & 0xFF000) >> 12),
  185. (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
  186. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  187. printf("Reset cause: %s\n", get_reset_cause(cause));
  188. printf("Boot mode: ");
  189. switch (get_boot_mode()) {
  190. case LOW_POWER_BOOT:
  191. printf("Low power boot\n");
  192. break;
  193. case DUAL_BOOT:
  194. printf("Dual boot\n");
  195. break;
  196. case SINGLE_BOOT:
  197. default:
  198. printf("Single boot\n");
  199. break;
  200. }
  201. if (ldo_mode_is_enabled())
  202. printf("PMC1: LDO enabled mode\n");
  203. else
  204. printf("PMC1: LDO bypass mode\n");
  205. return 0;
  206. }
  207. #endif
  208. #define CMC_SRS_TAMPER (1 << 31)
  209. #define CMC_SRS_SECURITY (1 << 30)
  210. #define CMC_SRS_TZWDG (1 << 29)
  211. #define CMC_SRS_JTAG_RST (1 << 28)
  212. #define CMC_SRS_CORE1 (1 << 16)
  213. #define CMC_SRS_LOCKUP (1 << 15)
  214. #define CMC_SRS_SW (1 << 14)
  215. #define CMC_SRS_WDG (1 << 13)
  216. #define CMC_SRS_PIN_RESET (1 << 8)
  217. #define CMC_SRS_WARM (1 << 4)
  218. #define CMC_SRS_HVD (1 << 3)
  219. #define CMC_SRS_LVD (1 << 2)
  220. #define CMC_SRS_POR (1 << 1)
  221. #define CMC_SRS_WUP (1 << 0)
  222. static u32 reset_cause = -1;
  223. static char *get_reset_cause(char *ret)
  224. {
  225. u32 cause1, cause = 0, srs = 0;
  226. u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
  227. u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
  228. if (!ret)
  229. return "null";
  230. srs = readl(reg_srs);
  231. cause1 = readl(reg_ssrs);
  232. writel(cause1, reg_ssrs);
  233. reset_cause = cause1;
  234. cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
  235. switch (cause) {
  236. case CMC_SRS_POR:
  237. sprintf(ret, "%s", "POR");
  238. break;
  239. case CMC_SRS_WUP:
  240. sprintf(ret, "%s", "WUP");
  241. break;
  242. case CMC_SRS_WARM:
  243. cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
  244. CMC_SRS_JTAG_RST);
  245. switch (cause) {
  246. case CMC_SRS_WDG:
  247. sprintf(ret, "%s", "WARM-WDG");
  248. break;
  249. case CMC_SRS_SW:
  250. sprintf(ret, "%s", "WARM-SW");
  251. break;
  252. case CMC_SRS_JTAG_RST:
  253. sprintf(ret, "%s", "WARM-JTAG");
  254. break;
  255. default:
  256. sprintf(ret, "%s", "WARM-UNKN");
  257. break;
  258. }
  259. break;
  260. default:
  261. sprintf(ret, "%s-%X", "UNKN", cause1);
  262. break;
  263. }
  264. debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
  265. return ret;
  266. }
  267. #ifdef CONFIG_ENV_IS_IN_MMC
  268. __weak int board_mmc_get_env_dev(int devno)
  269. {
  270. return CONFIG_SYS_MMC_ENV_DEV;
  271. }
  272. int mmc_get_env_dev(void)
  273. {
  274. int devno = 0;
  275. u32 bt1_cfg = 0;
  276. /* If not boot from sd/mmc, use default value */
  277. if (get_boot_mode() == LOW_POWER_BOOT)
  278. return CONFIG_SYS_MMC_ENV_DEV;
  279. bt1_cfg = readl(CMC1_RBASE + 0x40);
  280. devno = (bt1_cfg >> 9) & 0x7;
  281. return board_mmc_get_env_dev(devno);
  282. }
  283. #endif
  284. enum boot_device get_boot_device(void)
  285. {
  286. struct bootrom_sw_info **p =
  287. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
  288. enum boot_device boot_dev = SD1_BOOT;
  289. u8 boot_type = (*p)->boot_dev_type;
  290. u8 boot_instance = (*p)->boot_dev_instance;
  291. switch (boot_type) {
  292. case BOOT_TYPE_SD:
  293. boot_dev = boot_instance + SD1_BOOT;
  294. break;
  295. case BOOT_TYPE_MMC:
  296. boot_dev = boot_instance + MMC1_BOOT;
  297. break;
  298. case BOOT_TYPE_USB:
  299. boot_dev = USB_BOOT;
  300. break;
  301. default:
  302. break;
  303. }
  304. return boot_dev;
  305. }