pcc.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <errno.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/pcc.h>
  12. #include <asm/arch/sys_proto.h>
  13. #define PCC_CLKSRC_TYPES 2
  14. #define PCC_CLKSRC_NUM 7
  15. static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
  16. { SCG_NIC1_BUS_CLK,
  17. SCG_NIC1_CLK,
  18. SCG_DDR_CLK,
  19. SCG_APLL_PFD2_CLK,
  20. SCG_APLL_PFD1_CLK,
  21. SCG_APLL_PFD0_CLK,
  22. USB_PLL_OUT,
  23. },
  24. { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
  25. MIPI_PLL_OUT,
  26. SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
  27. SCG_ROSC_CLK,
  28. SCG_NIC1_BUS_CLK,
  29. SCG_NIC1_CLK,
  30. SCG_APLL_PFD3_CLK,
  31. },
  32. };
  33. static struct pcc_entry pcc_arrays[] = {
  34. {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  35. {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  36. {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  37. {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  38. {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  39. {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  40. {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  41. {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  42. {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  43. {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  44. {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  45. {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  46. {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  47. {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  48. {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  49. {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  50. {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  51. {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  52. {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  53. {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  54. {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  55. {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  56. {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  57. {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
  58. {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
  59. {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  60. {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  61. {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  62. {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  63. {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  64. {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
  65. {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  66. {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
  67. {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
  68. {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  69. {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  70. {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  71. {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  72. {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
  73. {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
  74. {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
  75. };
  76. int pcc_clock_enable(enum pcc_clk clk, bool enable)
  77. {
  78. u32 reg, val;
  79. if (clk >= ARRAY_SIZE(pcc_arrays))
  80. return -EINVAL;
  81. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  82. val = readl(reg);
  83. clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
  84. clk, reg, val, enable);
  85. if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
  86. return -EPERM;
  87. if (enable)
  88. val |= PCC_CGC_MASK;
  89. else
  90. val &= ~PCC_CGC_MASK;
  91. writel(val, reg);
  92. clk_debug("pcc_clock_enable: val 0x%x\n", val);
  93. return 0;
  94. }
  95. /* The clock source select needs clock is disabled */
  96. int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
  97. {
  98. u32 reg, val, i, clksrc_type;
  99. if (clk >= ARRAY_SIZE(pcc_arrays))
  100. return -EINVAL;
  101. clksrc_type = pcc_arrays[clk].clksrc;
  102. if (clksrc_type >= CLKSRC_NO_PCS) {
  103. printf("No PCS field for the PCC %d, clksrc type %d\n",
  104. clk, clksrc_type);
  105. return -EPERM;
  106. }
  107. for (i = 0; i < PCC_CLKSRC_NUM; i++) {
  108. if (pcc_clksrc[clksrc_type][i] == src) {
  109. /* Find the clock src, then set it to PCS */
  110. break;
  111. }
  112. }
  113. if (i == PCC_CLKSRC_NUM) {
  114. printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
  115. return -EINVAL;
  116. }
  117. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  118. val = readl(reg);
  119. clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
  120. clk, reg, val, clksrc_type);
  121. if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
  122. (val & PCC_CGC_MASK)) {
  123. printf("Not permit to select clock source val = 0x%x\n", val);
  124. return -EPERM;
  125. }
  126. val &= ~PCC_PCS_MASK;
  127. val |= ((i + 1) << PCC_PCS_OFFSET);
  128. writel(val, reg);
  129. clk_debug("pcc_clock_sel: val 0x%x\n", val);
  130. return 0;
  131. }
  132. int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
  133. {
  134. u32 reg, val;
  135. if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
  136. (div == 1 && frac != 0))
  137. return -EINVAL;
  138. if (pcc_arrays[clk].div >= PCC_NO_DIV) {
  139. printf("No DIV/FRAC field for the PCC %d\n", clk);
  140. return -EPERM;
  141. }
  142. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  143. val = readl(reg);
  144. if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
  145. (val & PCC_CGC_MASK)) {
  146. printf("Not permit to set div/frac val = 0x%x\n", val);
  147. return -EPERM;
  148. }
  149. if (frac)
  150. val |= PCC_FRAC_MASK;
  151. else
  152. val &= ~PCC_FRAC_MASK;
  153. val &= ~PCC_PCD_MASK;
  154. val |= (div - 1) & PCC_PCD_MASK;
  155. writel(val, reg);
  156. return 0;
  157. }
  158. bool pcc_clock_is_enable(enum pcc_clk clk)
  159. {
  160. u32 reg, val;
  161. if (clk >= ARRAY_SIZE(pcc_arrays))
  162. return -EINVAL;
  163. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  164. val = readl(reg);
  165. if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
  166. return true;
  167. return false;
  168. }
  169. int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
  170. {
  171. u32 reg, val, clksrc_type;
  172. if (clk >= ARRAY_SIZE(pcc_arrays))
  173. return -EINVAL;
  174. clksrc_type = pcc_arrays[clk].clksrc;
  175. if (clksrc_type >= CLKSRC_NO_PCS) {
  176. printf("No PCS field for the PCC %d, clksrc type %d\n",
  177. clk, clksrc_type);
  178. return -EPERM;
  179. }
  180. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  181. val = readl(reg);
  182. clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
  183. clk, reg, val, clksrc_type);
  184. if (!(val & PCC_PR_MASK)) {
  185. printf("This pcc slot is not present = 0x%x\n", val);
  186. return -EPERM;
  187. }
  188. val &= PCC_PCS_MASK;
  189. val = (val >> PCC_PCS_OFFSET);
  190. if (!val) {
  191. printf("Clock source is off\n");
  192. return -EIO;
  193. }
  194. *src = pcc_clksrc[clksrc_type][val - 1];
  195. clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
  196. return 0;
  197. }
  198. u32 pcc_clock_get_rate(enum pcc_clk clk)
  199. {
  200. u32 reg, val, rate, frac, div;
  201. enum scg_clk parent;
  202. int ret;
  203. ret = pcc_clock_get_clksrc(clk, &parent);
  204. if (ret)
  205. return 0;
  206. rate = scg_clk_get_rate(parent);
  207. clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
  208. if (pcc_arrays[clk].div == PCC_HAS_DIV) {
  209. reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
  210. val = readl(reg);
  211. frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
  212. div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
  213. /*
  214. * Theoretically don't have overflow in the calc,
  215. * the rate won't exceed 2G
  216. */
  217. rate = rate * (frac + 1) / (div + 1);
  218. }
  219. clk_debug("pcc_clock_get_rate: rate %u\n", rate);
  220. return rate;
  221. }