clock_slice.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author:
  6. * Peng Fan <Peng.Fan@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <div64.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  17. static struct clk_root_map root_array[] = {
  18. {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
  19. {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
  20. PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
  21. PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
  22. },
  23. {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
  24. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
  25. PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
  26. PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
  27. },
  28. {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
  29. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
  30. PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
  31. PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
  32. },
  33. {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
  34. {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
  35. PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
  36. PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
  37. },
  38. {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
  39. {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
  40. PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
  41. PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
  42. },
  43. {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
  44. {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
  45. PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
  46. PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
  47. },
  48. {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
  49. {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
  50. PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
  51. PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
  52. },
  53. {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
  54. {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
  55. PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
  56. PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
  57. },
  58. {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
  59. {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
  60. },
  61. {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
  62. {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
  63. },
  64. {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
  65. {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
  66. PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
  67. PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
  68. },
  69. {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
  70. {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
  71. PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
  72. PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
  73. },
  74. {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
  75. {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
  76. PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
  77. PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
  78. },
  79. {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
  80. {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
  81. PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
  82. PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
  83. },
  84. {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
  85. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
  86. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
  87. EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
  88. },
  89. {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
  90. {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
  91. PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
  92. PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
  93. },
  94. {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
  95. {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
  96. EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
  97. PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
  98. },
  99. {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
  100. {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
  101. PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
  102. PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
  103. },
  104. {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
  105. {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
  106. PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
  107. PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
  108. },
  109. {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
  110. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
  111. PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
  112. PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
  113. },
  114. {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
  115. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
  116. PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
  117. PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
  118. },
  119. {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
  120. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
  121. PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
  122. PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
  123. },
  124. {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
  125. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
  126. PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
  127. PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
  128. },
  129. {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
  130. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
  131. PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
  132. PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
  133. },
  134. {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
  135. {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
  136. PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
  137. PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
  138. },
  139. {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
  140. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
  141. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
  142. EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
  143. },
  144. {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
  145. {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
  146. PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
  147. PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
  148. },
  149. {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
  150. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
  151. EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
  152. EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
  153. },
  154. {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
  155. {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
  156. PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
  157. PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
  158. },
  159. {EIM_CLK_ROOT, CCM_IP_CHANNEL,
  160. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  161. PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
  162. PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
  163. },
  164. {NAND_CLK_ROOT, CCM_IP_CHANNEL,
  165. {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
  166. PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
  167. PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
  168. },
  169. {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
  170. {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
  171. PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
  172. PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
  173. },
  174. {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
  175. {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
  176. PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
  177. PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
  178. },
  179. {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
  180. {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
  181. PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
  182. PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
  183. },
  184. {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
  185. {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
  186. PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
  187. PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
  188. },
  189. {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
  190. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
  191. PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
  192. EXT_CLK_1, EXT_CLK_4}
  193. },
  194. {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
  195. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
  196. PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
  197. EXT_CLK_1, EXT_CLK_3}
  198. },
  199. {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
  200. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
  201. PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
  202. PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
  203. },
  204. {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
  205. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
  206. PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
  207. PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
  208. },
  209. {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
  210. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
  211. PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
  212. PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
  213. },
  214. {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
  215. {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
  216. PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
  217. PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
  218. },
  219. {UART1_CLK_ROOT, CCM_IP_CHANNEL,
  220. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  221. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  222. EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
  223. },
  224. {UART2_CLK_ROOT, CCM_IP_CHANNEL,
  225. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  226. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  227. EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
  228. },
  229. {UART3_CLK_ROOT, CCM_IP_CHANNEL,
  230. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  231. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  232. EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
  233. },
  234. {UART4_CLK_ROOT, CCM_IP_CHANNEL,
  235. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  236. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  237. EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
  238. },
  239. {UART5_CLK_ROOT, CCM_IP_CHANNEL,
  240. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  241. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  242. EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
  243. },
  244. {UART6_CLK_ROOT, CCM_IP_CHANNEL,
  245. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  246. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  247. EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
  248. },
  249. {UART7_CLK_ROOT, CCM_IP_CHANNEL,
  250. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  251. PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
  252. EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
  253. },
  254. {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
  255. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  256. PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
  257. PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
  258. },
  259. {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
  260. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  261. PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
  262. PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
  263. },
  264. {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
  265. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  266. PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
  267. PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
  268. },
  269. {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
  270. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
  271. PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
  272. PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
  273. },
  274. {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
  275. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
  276. PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
  277. REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
  278. },
  279. {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
  280. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
  281. PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
  282. REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
  283. },
  284. {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
  285. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
  286. PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
  287. REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
  288. },
  289. {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
  290. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
  291. PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
  292. REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
  293. },
  294. {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
  295. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
  296. PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
  297. REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
  298. },
  299. {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
  300. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
  301. PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
  302. REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
  303. },
  304. {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
  305. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  306. PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
  307. PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
  308. },
  309. {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
  310. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  311. PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
  312. PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
  313. },
  314. {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
  315. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
  316. PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
  317. PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
  318. },
  319. {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
  320. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
  321. PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
  322. PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
  323. },
  324. {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
  325. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
  326. PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
  327. PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
  328. },
  329. {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
  330. {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
  331. PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
  332. PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
  333. },
  334. {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
  335. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  336. PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
  337. EXT_CLK_1, EXT_CLK_3}
  338. },
  339. {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
  340. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  341. PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
  342. REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
  343. },
  344. {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
  345. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  346. PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
  347. PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
  348. },
  349. {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
  350. {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
  351. PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
  352. PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
  353. },
  354. {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
  355. {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
  356. PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
  357. PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
  358. },
  359. {IPP_DO_CLKO1, CCM_IP_CHANNEL,
  360. {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
  361. PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
  362. PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
  363. },
  364. {IPP_DO_CLKO2, CCM_IP_CHANNEL,
  365. {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
  366. PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
  367. PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
  368. },
  369. };
  370. /* select which entry of root_array */
  371. static int select(enum clk_root_index clock_id)
  372. {
  373. int i, size;
  374. struct clk_root_map *p = root_array;
  375. size = ARRAY_SIZE(root_array);
  376. for (i = 0; i < size; i++, p++) {
  377. if (clock_id == p->entry)
  378. return i;
  379. }
  380. return -EINVAL;
  381. }
  382. static int src_supported(int entry, enum clk_root_src clock_src)
  383. {
  384. int i, size;
  385. struct clk_root_map *p = &root_array[entry];
  386. if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
  387. size = 2;
  388. else
  389. size = 8;
  390. for (i = 0; i < size; i++) {
  391. if (p->src_mux[i] == clock_src)
  392. return i;
  393. }
  394. return -EINVAL;
  395. }
  396. /* Set src for clock root slice. */
  397. int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
  398. {
  399. int root_entry, src_entry;
  400. u32 reg;
  401. if (clock_id >= CLK_ROOT_MAX)
  402. return -EINVAL;
  403. root_entry = select(clock_id);
  404. if (root_entry < 0)
  405. return -EINVAL;
  406. src_entry = src_supported(root_entry, clock_src);
  407. if (src_entry < 0)
  408. return -EINVAL;
  409. reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
  410. reg &= ~CLK_ROOT_MUX_MASK;
  411. reg |= src_entry << CLK_ROOT_MUX_SHIFT;
  412. __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
  413. return 0;
  414. }
  415. /* Get src of a clock root slice. */
  416. int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
  417. {
  418. u32 val;
  419. int root_entry;
  420. struct clk_root_map *p;
  421. if (clock_id >= CLK_ROOT_MAX)
  422. return -EINVAL;
  423. val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  424. val &= CLK_ROOT_MUX_MASK;
  425. val >>= CLK_ROOT_MUX_SHIFT;
  426. root_entry = select(clock_id);
  427. if (root_entry < 0)
  428. return -EINVAL;
  429. p = &root_array[root_entry];
  430. *p_clock_src = p->src_mux[val];
  431. return 0;
  432. }
  433. int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
  434. {
  435. int root_entry;
  436. struct clk_root_map *p;
  437. u32 reg;
  438. if (clock_id >= CLK_ROOT_MAX)
  439. return -EINVAL;
  440. root_entry = select(clock_id);
  441. if (root_entry < 0)
  442. return -EINVAL;
  443. p = &root_array[root_entry];
  444. if ((p->type == CCM_CORE_CHANNEL) ||
  445. (p->type == CCM_DRAM_PHYM_CHANNEL) ||
  446. (p->type == CCM_DRAM_CHANNEL)) {
  447. if (pre_div != CLK_ROOT_PRE_DIV1) {
  448. printf("Error pre div!\n");
  449. return -EINVAL;
  450. }
  451. }
  452. reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
  453. reg &= ~CLK_ROOT_PRE_DIV_MASK;
  454. reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
  455. __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
  456. return 0;
  457. }
  458. int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
  459. {
  460. u32 val;
  461. int root_entry;
  462. struct clk_root_map *p;
  463. if (clock_id >= CLK_ROOT_MAX)
  464. return -EINVAL;
  465. root_entry = select(clock_id);
  466. if (root_entry < 0)
  467. return -EINVAL;
  468. p = &root_array[root_entry];
  469. if ((p->type == CCM_CORE_CHANNEL) ||
  470. (p->type == CCM_DRAM_PHYM_CHANNEL) ||
  471. (p->type == CCM_DRAM_CHANNEL)) {
  472. *pre_div = 0;
  473. return 0;
  474. }
  475. val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  476. val &= CLK_ROOT_PRE_DIV_MASK;
  477. val >>= CLK_ROOT_PRE_DIV_SHIFT;
  478. *pre_div = val;
  479. return 0;
  480. }
  481. int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
  482. {
  483. u32 reg;
  484. if (clock_id >= CLK_ROOT_MAX)
  485. return -EINVAL;
  486. if (clock_id == DRAM_PHYM_CLK_ROOT) {
  487. if (div != CLK_ROOT_POST_DIV1) {
  488. printf("Error post div!\n");
  489. return -EINVAL;
  490. }
  491. }
  492. /* Only 3 bit post div. */
  493. if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
  494. printf("Error post div!\n");
  495. return -EINVAL;
  496. }
  497. reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
  498. reg &= ~CLK_ROOT_POST_DIV_MASK;
  499. reg |= div << CLK_ROOT_POST_DIV_SHIFT;
  500. __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
  501. return 0;
  502. }
  503. int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
  504. {
  505. u32 val;
  506. if (clock_id >= CLK_ROOT_MAX)
  507. return -EINVAL;
  508. if (clock_id == DRAM_PHYM_CLK_ROOT) {
  509. *div = 0;
  510. return 0;
  511. }
  512. val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  513. if (clock_id == DRAM_CLK_ROOT)
  514. val &= DRAM_CLK_ROOT_POST_DIV_MASK;
  515. else
  516. val &= CLK_ROOT_POST_DIV_MASK;
  517. val >>= CLK_ROOT_POST_DIV_SHIFT;
  518. *div = val;
  519. return 0;
  520. }
  521. int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
  522. int auto_en)
  523. {
  524. u32 val;
  525. int root_entry;
  526. struct clk_root_map *p;
  527. if (clock_id >= CLK_ROOT_MAX)
  528. return -EINVAL;
  529. root_entry = select(clock_id);
  530. if (root_entry < 0)
  531. return -EINVAL;
  532. p = &root_array[root_entry];
  533. if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
  534. printf("Auto postdiv not supported.!\n");
  535. return -EINVAL;
  536. }
  537. /*
  538. * Each time only one filed can be changed, no use target_root_set.
  539. */
  540. val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  541. val &= ~CLK_ROOT_AUTO_DIV_MASK;
  542. val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
  543. if (auto_en)
  544. val |= CLK_ROOT_AUTO_EN;
  545. else
  546. val &= ~CLK_ROOT_AUTO_EN;
  547. __raw_writel(val, &imx_ccm->root[clock_id].target_root);
  548. return 0;
  549. }
  550. int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
  551. int *auto_en)
  552. {
  553. u32 val;
  554. int root_entry;
  555. struct clk_root_map *p;
  556. if (clock_id >= CLK_ROOT_MAX)
  557. return -EINVAL;
  558. root_entry = select(clock_id);
  559. if (root_entry < 0)
  560. return -EINVAL;
  561. p = &root_array[root_entry];
  562. /*
  563. * Only bus/ahb channel supports auto div.
  564. * If unsupported, just set auto_en and div with 0.
  565. */
  566. if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
  567. *auto_en = 0;
  568. *div = 0;
  569. return 0;
  570. }
  571. val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  572. if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
  573. *auto_en = 0;
  574. else
  575. *auto_en = 1;
  576. val &= CLK_ROOT_AUTO_DIV_MASK;
  577. val >>= CLK_ROOT_AUTO_DIV_SHIFT;
  578. *div = val;
  579. return 0;
  580. }
  581. int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
  582. {
  583. if (clock_id >= CLK_ROOT_MAX)
  584. return -EINVAL;
  585. *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  586. return 0;
  587. }
  588. int clock_set_target_val(enum clk_root_index clock_id, u32 val)
  589. {
  590. if (clock_id >= CLK_ROOT_MAX)
  591. return -EINVAL;
  592. __raw_writel(val, &imx_ccm->root[clock_id].target_root);
  593. return 0;
  594. }
  595. /* Auto_div and auto_en is ignored, they are rarely used. */
  596. int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
  597. enum root_post_div post_div, enum clk_root_src clock_src)
  598. {
  599. u32 val;
  600. int root_entry, src_entry;
  601. struct clk_root_map *p;
  602. if (clock_id >= CLK_ROOT_MAX)
  603. return -EINVAL;
  604. root_entry = select(clock_id);
  605. if (root_entry < 0)
  606. return -EINVAL;
  607. p = &root_array[root_entry];
  608. if ((p->type == CCM_CORE_CHANNEL) ||
  609. (p->type == CCM_DRAM_PHYM_CHANNEL) ||
  610. (p->type == CCM_DRAM_CHANNEL)) {
  611. if (pre_div != CLK_ROOT_PRE_DIV1) {
  612. printf("Error pre div!\n");
  613. return -EINVAL;
  614. }
  615. }
  616. /* Only 3 bit post div. */
  617. if (p->type == CCM_DRAM_CHANNEL) {
  618. if (post_div > CLK_ROOT_POST_DIV7) {
  619. printf("Error post div!\n");
  620. return -EINVAL;
  621. }
  622. }
  623. if (p->type == CCM_DRAM_PHYM_CHANNEL) {
  624. if (post_div != CLK_ROOT_POST_DIV1) {
  625. printf("Error post div!\n");
  626. return -EINVAL;
  627. }
  628. }
  629. src_entry = src_supported(root_entry, clock_src);
  630. if (src_entry < 0)
  631. return -EINVAL;
  632. val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
  633. post_div << CLK_ROOT_POST_DIV_SHIFT |
  634. src_entry << CLK_ROOT_MUX_SHIFT;
  635. __raw_writel(val, &imx_ccm->root[clock_id].target_root);
  636. return 0;
  637. }
  638. int clock_root_enabled(enum clk_root_index clock_id)
  639. {
  640. u32 val;
  641. if (clock_id >= CLK_ROOT_MAX)
  642. return -EINVAL;
  643. /*
  644. * No enable bit for DRAM controller and PHY. Just return enabled.
  645. */
  646. if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
  647. return 1;
  648. val = __raw_readl(&imx_ccm->root[clock_id].target_root);
  649. return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
  650. }
  651. /* CCGR gate operation */
  652. int clock_enable(enum clk_ccgr_index index, bool enable)
  653. {
  654. if (index >= CCGR_MAX)
  655. return -EINVAL;
  656. if (enable)
  657. __raw_writel(CCM_CLK_ON_MSK,
  658. &imx_ccm->ccgr_array[index].ccgr_set);
  659. else
  660. __raw_writel(CCM_CLK_ON_MSK,
  661. &imx_ccm->ccgr_array[index].ccgr_clr);
  662. return 0;
  663. }