clock.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author:
  6. * Peng Fan <Peng.Fan@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <command.h>
  11. #include <div64.h>
  12. #include <log.h>
  13. #include <asm/io.h>
  14. #include <linux/errno.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  20. ANATOP_BASE_ADDR;
  21. struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  22. #ifdef CONFIG_FSL_ESDHC_IMX
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #endif
  25. int get_clocks(void)
  26. {
  27. #ifdef CONFIG_FSL_ESDHC_IMX
  28. #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
  29. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  30. #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
  31. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  32. #else
  33. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  34. #endif
  35. #endif
  36. return 0;
  37. }
  38. u32 get_ahb_clk(void)
  39. {
  40. return get_root_clk(AHB_CLK_ROOT);
  41. }
  42. static u32 get_ipg_clk(void)
  43. {
  44. /*
  45. * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
  46. * each other.
  47. */
  48. return get_ahb_clk() / 2;
  49. }
  50. u32 imx_get_uartclk(void)
  51. {
  52. return get_root_clk(UART_CLK_ROOT);
  53. }
  54. u32 imx_get_fecclk(void)
  55. {
  56. return get_root_clk(ENET_AXI_CLK_ROOT);
  57. }
  58. #ifdef CONFIG_MXC_OCOTP
  59. void enable_ocotp_clk(unsigned char enable)
  60. {
  61. clock_enable(CCGR_OCOTP, enable);
  62. }
  63. void enable_thermal_clk(void)
  64. {
  65. enable_ocotp_clk(1);
  66. }
  67. #endif
  68. void enable_usboh3_clk(unsigned char enable)
  69. {
  70. u32 target;
  71. if (enable) {
  72. /* disable the clock gate first */
  73. clock_enable(CCGR_USB_HSIC, 0);
  74. /* 120Mhz */
  75. target = CLK_ROOT_ON |
  76. USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  77. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  78. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  79. clock_set_target_val(USB_HSIC_CLK_ROOT, target);
  80. /* enable the clock gate */
  81. clock_enable(CCGR_USB_CTRL, 1);
  82. clock_enable(CCGR_USB_HSIC, 1);
  83. clock_enable(CCGR_USB_PHY1, 1);
  84. clock_enable(CCGR_USB_PHY2, 1);
  85. } else {
  86. clock_enable(CCGR_USB_CTRL, 0);
  87. clock_enable(CCGR_USB_HSIC, 0);
  88. clock_enable(CCGR_USB_PHY1, 0);
  89. clock_enable(CCGR_USB_PHY2, 0);
  90. }
  91. }
  92. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  93. {
  94. u32 reg, div_sel;
  95. u32 num, denom;
  96. /*
  97. * Alought there are four choices for the bypass src,
  98. * we choose OSC_24M which is the default set in ROM.
  99. */
  100. switch (pll) {
  101. case PLL_CORE:
  102. reg = readl(&ccm_anatop->pll_arm);
  103. if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
  104. return 0;
  105. if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
  106. return MXC_HCLK;
  107. div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
  108. CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
  109. return (infreq * div_sel) / 2;
  110. case PLL_SYS:
  111. reg = readl(&ccm_anatop->pll_480);
  112. if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
  113. return 0;
  114. if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
  115. return MXC_HCLK;
  116. if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
  117. CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
  118. return 480000000u;
  119. else
  120. return 528000000u;
  121. case PLL_ENET:
  122. reg = readl(&ccm_anatop->pll_enet);
  123. if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
  124. return 0;
  125. if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
  126. return MXC_HCLK;
  127. return 1000000000u;
  128. case PLL_DDR:
  129. reg = readl(&ccm_anatop->pll_ddr);
  130. if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
  131. return 0;
  132. num = ccm_anatop->pll_ddr_num;
  133. denom = ccm_anatop->pll_ddr_denom;
  134. if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
  135. return MXC_HCLK;
  136. div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
  137. CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
  138. return infreq * (div_sel + num / denom);
  139. case PLL_USB:
  140. return 480000000u;
  141. default:
  142. printf("Unsupported pll clocks %d\n", pll);
  143. break;
  144. }
  145. return 0;
  146. }
  147. static u32 mxc_get_pll_sys_derive(int derive)
  148. {
  149. u32 freq, div, frac;
  150. u32 reg;
  151. div = 1;
  152. reg = readl(&ccm_anatop->pll_480);
  153. freq = decode_pll(PLL_SYS, MXC_HCLK);
  154. switch (derive) {
  155. case PLL_SYS_MAIN_480M_CLK:
  156. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
  157. return 0;
  158. else
  159. return freq;
  160. case PLL_SYS_MAIN_240M_CLK:
  161. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
  162. return 0;
  163. else
  164. return freq / 2;
  165. case PLL_SYS_MAIN_120M_CLK:
  166. if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
  167. return 0;
  168. else
  169. return freq / 4;
  170. case PLL_SYS_PFD0_392M_CLK:
  171. reg = readl(&ccm_anatop->pfd_480a);
  172. if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
  173. return 0;
  174. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  175. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  176. break;
  177. case PLL_SYS_PFD0_196M_CLK:
  178. if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
  179. return 0;
  180. reg = readl(&ccm_anatop->pfd_480a);
  181. frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
  182. CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
  183. div = 2;
  184. break;
  185. case PLL_SYS_PFD1_332M_CLK:
  186. reg = readl(&ccm_anatop->pfd_480a);
  187. if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
  188. return 0;
  189. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  190. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  191. break;
  192. case PLL_SYS_PFD1_166M_CLK:
  193. if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
  194. return 0;
  195. reg = readl(&ccm_anatop->pfd_480a);
  196. frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
  197. CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
  198. div = 2;
  199. break;
  200. case PLL_SYS_PFD2_270M_CLK:
  201. reg = readl(&ccm_anatop->pfd_480a);
  202. if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
  203. return 0;
  204. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  205. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  206. break;
  207. case PLL_SYS_PFD2_135M_CLK:
  208. if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
  209. return 0;
  210. reg = readl(&ccm_anatop->pfd_480a);
  211. frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
  212. CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
  213. div = 2;
  214. break;
  215. case PLL_SYS_PFD3_CLK:
  216. reg = readl(&ccm_anatop->pfd_480a);
  217. if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
  218. return 0;
  219. frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
  220. CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
  221. break;
  222. case PLL_SYS_PFD4_CLK:
  223. reg = readl(&ccm_anatop->pfd_480b);
  224. if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
  225. return 0;
  226. frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
  227. CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
  228. break;
  229. case PLL_SYS_PFD5_CLK:
  230. reg = readl(&ccm_anatop->pfd_480b);
  231. if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
  232. return 0;
  233. frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
  234. CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
  235. break;
  236. case PLL_SYS_PFD6_CLK:
  237. reg = readl(&ccm_anatop->pfd_480b);
  238. if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
  239. return 0;
  240. frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
  241. CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
  242. break;
  243. case PLL_SYS_PFD7_CLK:
  244. reg = readl(&ccm_anatop->pfd_480b);
  245. if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
  246. return 0;
  247. frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
  248. CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
  249. break;
  250. default:
  251. printf("Error derived pll_sys clock %d\n", derive);
  252. return 0;
  253. }
  254. return ((freq / frac) * 18) / div;
  255. }
  256. static u32 mxc_get_pll_enet_derive(int derive)
  257. {
  258. u32 freq, reg;
  259. freq = decode_pll(PLL_ENET, MXC_HCLK);
  260. reg = readl(&ccm_anatop->pll_enet);
  261. switch (derive) {
  262. case PLL_ENET_MAIN_500M_CLK:
  263. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
  264. return freq / 2;
  265. break;
  266. case PLL_ENET_MAIN_250M_CLK:
  267. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
  268. return freq / 4;
  269. break;
  270. case PLL_ENET_MAIN_125M_CLK:
  271. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
  272. return freq / 8;
  273. break;
  274. case PLL_ENET_MAIN_100M_CLK:
  275. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
  276. return freq / 10;
  277. break;
  278. case PLL_ENET_MAIN_50M_CLK:
  279. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
  280. return freq / 20;
  281. break;
  282. case PLL_ENET_MAIN_40M_CLK:
  283. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
  284. return freq / 25;
  285. break;
  286. case PLL_ENET_MAIN_25M_CLK:
  287. if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
  288. return freq / 40;
  289. break;
  290. default:
  291. printf("Error derived pll_enet clock %d\n", derive);
  292. break;
  293. }
  294. return 0;
  295. }
  296. static u32 mxc_get_pll_ddr_derive(int derive)
  297. {
  298. u32 freq, reg;
  299. freq = decode_pll(PLL_DDR, MXC_HCLK);
  300. reg = readl(&ccm_anatop->pll_ddr);
  301. switch (derive) {
  302. case PLL_DRAM_MAIN_1066M_CLK:
  303. return freq;
  304. case PLL_DRAM_MAIN_533M_CLK:
  305. if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
  306. return freq / 2;
  307. break;
  308. default:
  309. printf("Error derived pll_ddr clock %d\n", derive);
  310. break;
  311. }
  312. return 0;
  313. }
  314. static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
  315. {
  316. switch (pll) {
  317. case PLL_SYS:
  318. return mxc_get_pll_sys_derive(derive);
  319. case PLL_ENET:
  320. return mxc_get_pll_enet_derive(derive);
  321. case PLL_DDR:
  322. return mxc_get_pll_ddr_derive(derive);
  323. default:
  324. printf("Error pll.\n");
  325. return 0;
  326. }
  327. }
  328. static u32 get_root_src_clk(enum clk_root_src root_src)
  329. {
  330. switch (root_src) {
  331. case OSC_24M_CLK:
  332. return 24000000u;
  333. case PLL_ARM_MAIN_800M_CLK:
  334. return decode_pll(PLL_CORE, MXC_HCLK);
  335. case PLL_SYS_MAIN_480M_CLK:
  336. case PLL_SYS_MAIN_240M_CLK:
  337. case PLL_SYS_MAIN_120M_CLK:
  338. case PLL_SYS_PFD0_392M_CLK:
  339. case PLL_SYS_PFD0_196M_CLK:
  340. case PLL_SYS_PFD1_332M_CLK:
  341. case PLL_SYS_PFD1_166M_CLK:
  342. case PLL_SYS_PFD2_270M_CLK:
  343. case PLL_SYS_PFD2_135M_CLK:
  344. case PLL_SYS_PFD3_CLK:
  345. case PLL_SYS_PFD4_CLK:
  346. case PLL_SYS_PFD5_CLK:
  347. case PLL_SYS_PFD6_CLK:
  348. case PLL_SYS_PFD7_CLK:
  349. return mxc_get_pll_derive(PLL_SYS, root_src);
  350. case PLL_ENET_MAIN_500M_CLK:
  351. case PLL_ENET_MAIN_250M_CLK:
  352. case PLL_ENET_MAIN_125M_CLK:
  353. case PLL_ENET_MAIN_100M_CLK:
  354. case PLL_ENET_MAIN_50M_CLK:
  355. case PLL_ENET_MAIN_40M_CLK:
  356. case PLL_ENET_MAIN_25M_CLK:
  357. return mxc_get_pll_derive(PLL_ENET, root_src);
  358. case PLL_DRAM_MAIN_1066M_CLK:
  359. case PLL_DRAM_MAIN_533M_CLK:
  360. return mxc_get_pll_derive(PLL_DDR, root_src);
  361. case PLL_AUDIO_MAIN_CLK:
  362. return decode_pll(PLL_AUDIO, MXC_HCLK);
  363. case PLL_VIDEO_MAIN_CLK:
  364. return decode_pll(PLL_VIDEO, MXC_HCLK);
  365. case PLL_USB_MAIN_480M_CLK:
  366. return decode_pll(PLL_USB, MXC_HCLK);
  367. case REF_1M_CLK:
  368. return 1000000;
  369. case OSC_32K_CLK:
  370. return MXC_CLK32;
  371. case EXT_CLK_1:
  372. case EXT_CLK_2:
  373. case EXT_CLK_3:
  374. case EXT_CLK_4:
  375. printf("No EXT CLK supported??\n");
  376. break;
  377. };
  378. return 0;
  379. }
  380. u32 get_root_clk(enum clk_root_index clock_id)
  381. {
  382. enum clk_root_src root_src;
  383. u32 post_podf, pre_podf, auto_podf, root_src_clk;
  384. int auto_en;
  385. if (clock_root_enabled(clock_id) <= 0)
  386. return 0;
  387. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  388. return 0;
  389. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  390. return 0;
  391. if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
  392. return 0;
  393. if (auto_en == 0)
  394. auto_podf = 0;
  395. if (clock_get_src(clock_id, &root_src) < 0)
  396. return 0;
  397. root_src_clk = get_root_src_clk(root_src);
  398. /*
  399. * bypass clk is ignored.
  400. */
  401. return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
  402. (auto_podf + 1);
  403. }
  404. static u32 get_ddrc_clk(void)
  405. {
  406. u32 reg, freq;
  407. enum root_post_div post_div;
  408. reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
  409. if (reg & CLK_ROOT_MUX_MASK)
  410. /* DRAM_ALT_CLK_ROOT */
  411. freq = get_root_clk(DRAM_ALT_CLK_ROOT);
  412. else
  413. /* PLL_DRAM_MAIN_1066M_CLK */
  414. freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
  415. post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
  416. return freq / (post_div + 1) / 2;
  417. }
  418. unsigned int mxc_get_clock(enum mxc_clock clk)
  419. {
  420. switch (clk) {
  421. case MXC_ARM_CLK:
  422. return get_root_clk(ARM_A7_CLK_ROOT);
  423. case MXC_AXI_CLK:
  424. return get_root_clk(MAIN_AXI_CLK_ROOT);
  425. case MXC_AHB_CLK:
  426. return get_root_clk(AHB_CLK_ROOT);
  427. case MXC_IPG_CLK:
  428. return get_ipg_clk();
  429. case MXC_I2C_CLK:
  430. return get_root_clk(I2C1_CLK_ROOT);
  431. case MXC_UART_CLK:
  432. return get_root_clk(UART1_CLK_ROOT);
  433. case MXC_CSPI_CLK:
  434. return get_root_clk(ECSPI1_CLK_ROOT);
  435. case MXC_DDR_CLK:
  436. return get_ddrc_clk();
  437. case MXC_ESDHC_CLK:
  438. return get_root_clk(USDHC1_CLK_ROOT);
  439. case MXC_ESDHC2_CLK:
  440. return get_root_clk(USDHC2_CLK_ROOT);
  441. case MXC_ESDHC3_CLK:
  442. return get_root_clk(USDHC3_CLK_ROOT);
  443. default:
  444. printf("Unsupported mxc_clock %d\n", clk);
  445. break;
  446. }
  447. return 0;
  448. }
  449. #ifdef CONFIG_SYS_I2C_MXC
  450. /* i2c_num can be 0 - 3 */
  451. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  452. {
  453. u32 target;
  454. if (i2c_num >= 4)
  455. return -EINVAL;
  456. if (enable) {
  457. clock_enable(CCGR_I2C1 + i2c_num, 0);
  458. /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
  459. target = CLK_ROOT_ON |
  460. I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  461. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  462. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  463. clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
  464. clock_enable(CCGR_I2C1 + i2c_num, 1);
  465. } else {
  466. clock_enable(CCGR_I2C1 + i2c_num, 0);
  467. }
  468. return 0;
  469. }
  470. #endif
  471. static void init_clk_esdhc(void)
  472. {
  473. u32 target;
  474. /* disable the clock gate first */
  475. clock_enable(CCGR_USDHC1, 0);
  476. clock_enable(CCGR_USDHC2, 0);
  477. clock_enable(CCGR_USDHC3, 0);
  478. /* 196: 392/2 */
  479. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  480. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  481. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  482. clock_set_target_val(USDHC1_CLK_ROOT, target);
  483. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  484. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  485. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  486. clock_set_target_val(USDHC2_CLK_ROOT, target);
  487. target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
  488. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  489. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  490. clock_set_target_val(USDHC3_CLK_ROOT, target);
  491. /* enable the clock gate */
  492. clock_enable(CCGR_USDHC1, 1);
  493. clock_enable(CCGR_USDHC2, 1);
  494. clock_enable(CCGR_USDHC3, 1);
  495. }
  496. static void init_clk_uart(void)
  497. {
  498. u32 target;
  499. /* disable the clock gate first */
  500. clock_enable(CCGR_UART1, 0);
  501. clock_enable(CCGR_UART2, 0);
  502. clock_enable(CCGR_UART3, 0);
  503. clock_enable(CCGR_UART4, 0);
  504. clock_enable(CCGR_UART5, 0);
  505. clock_enable(CCGR_UART6, 0);
  506. clock_enable(CCGR_UART7, 0);
  507. /* 24Mhz */
  508. target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
  509. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  510. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  511. clock_set_target_val(UART1_CLK_ROOT, target);
  512. target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
  513. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  514. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  515. clock_set_target_val(UART2_CLK_ROOT, target);
  516. target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
  517. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  518. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  519. clock_set_target_val(UART3_CLK_ROOT, target);
  520. target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
  521. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  522. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  523. clock_set_target_val(UART4_CLK_ROOT, target);
  524. target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
  525. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  526. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  527. clock_set_target_val(UART5_CLK_ROOT, target);
  528. target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
  529. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  530. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  531. clock_set_target_val(UART6_CLK_ROOT, target);
  532. target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
  533. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  534. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  535. clock_set_target_val(UART7_CLK_ROOT, target);
  536. /* enable the clock gate */
  537. clock_enable(CCGR_UART1, 1);
  538. clock_enable(CCGR_UART2, 1);
  539. clock_enable(CCGR_UART3, 1);
  540. clock_enable(CCGR_UART4, 1);
  541. clock_enable(CCGR_UART5, 1);
  542. clock_enable(CCGR_UART6, 1);
  543. clock_enable(CCGR_UART7, 1);
  544. }
  545. static void init_clk_weim(void)
  546. {
  547. u32 target;
  548. /* disable the clock gate first */
  549. clock_enable(CCGR_WEIM, 0);
  550. /* 120Mhz */
  551. target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
  552. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  553. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  554. clock_set_target_val(EIM_CLK_ROOT, target);
  555. /* enable the clock gate */
  556. clock_enable(CCGR_WEIM, 1);
  557. }
  558. static void init_clk_ecspi(void)
  559. {
  560. u32 target;
  561. /* disable the clock gate first */
  562. clock_enable(CCGR_ECSPI1, 0);
  563. clock_enable(CCGR_ECSPI2, 0);
  564. clock_enable(CCGR_ECSPI3, 0);
  565. clock_enable(CCGR_ECSPI4, 0);
  566. /* 60Mhz: 240/4 */
  567. target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  568. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  569. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  570. clock_set_target_val(ECSPI1_CLK_ROOT, target);
  571. target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  572. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  573. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  574. clock_set_target_val(ECSPI2_CLK_ROOT, target);
  575. target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  576. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  577. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  578. clock_set_target_val(ECSPI3_CLK_ROOT, target);
  579. target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
  580. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  581. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  582. clock_set_target_val(ECSPI4_CLK_ROOT, target);
  583. /* enable the clock gate */
  584. clock_enable(CCGR_ECSPI1, 1);
  585. clock_enable(CCGR_ECSPI2, 1);
  586. clock_enable(CCGR_ECSPI3, 1);
  587. clock_enable(CCGR_ECSPI4, 1);
  588. }
  589. static void init_clk_wdog(void)
  590. {
  591. u32 target;
  592. /* disable the clock gate first */
  593. clock_enable(CCGR_WDOG1, 0);
  594. clock_enable(CCGR_WDOG2, 0);
  595. clock_enable(CCGR_WDOG3, 0);
  596. clock_enable(CCGR_WDOG4, 0);
  597. /* 24Mhz */
  598. target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
  599. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  600. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  601. clock_set_target_val(WDOG_CLK_ROOT, target);
  602. /* enable the clock gate */
  603. clock_enable(CCGR_WDOG1, 1);
  604. clock_enable(CCGR_WDOG2, 1);
  605. clock_enable(CCGR_WDOG3, 1);
  606. clock_enable(CCGR_WDOG4, 1);
  607. }
  608. #ifdef CONFIG_MXC_EPDC
  609. static void init_clk_epdc(void)
  610. {
  611. u32 target;
  612. /* disable the clock gate first */
  613. clock_enable(CCGR_EPDC, 0);
  614. /* 24Mhz */
  615. target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  616. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  617. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
  618. clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
  619. /* enable the clock gate */
  620. clock_enable(CCGR_EPDC, 1);
  621. }
  622. #endif
  623. static int enable_pll_enet(void)
  624. {
  625. u32 reg;
  626. s32 timeout = 100000;
  627. reg = readl(&ccm_anatop->pll_enet);
  628. /* If pll_enet powered up, no need to set it again */
  629. if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
  630. reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
  631. writel(reg, &ccm_anatop->pll_enet);
  632. while (timeout--) {
  633. if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
  634. break;
  635. }
  636. if (timeout <= 0) {
  637. /* If timeout, we set pwdn for pll_enet. */
  638. reg |= ANADIG_PLL_ENET_PWDN_MASK;
  639. return -ETIME;
  640. }
  641. }
  642. /* Clear bypass */
  643. writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
  644. writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
  645. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
  646. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
  647. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
  648. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
  649. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
  650. | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
  651. &ccm_anatop->pll_enet_set);
  652. return 0;
  653. }
  654. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  655. u32 post_div)
  656. {
  657. u32 reg = 0;
  658. ulong start;
  659. debug("pll5 div = %d, num = %d, denom = %d\n",
  660. pll_div, pll_num, pll_denom);
  661. /* Power up PLL5 video and disable its output */
  662. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
  663. CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
  664. CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
  665. CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
  666. CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
  667. CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
  668. &ccm_anatop->pll_video_clr);
  669. /* Set div, num and denom */
  670. switch (post_div) {
  671. case 1:
  672. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  673. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
  674. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  675. &ccm_anatop->pll_video_set);
  676. break;
  677. case 2:
  678. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  679. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  680. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  681. &ccm_anatop->pll_video_set);
  682. break;
  683. case 3:
  684. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  685. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  686. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
  687. &ccm_anatop->pll_video_set);
  688. break;
  689. case 4:
  690. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  691. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
  692. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
  693. &ccm_anatop->pll_video_set);
  694. break;
  695. case 0:
  696. default:
  697. writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
  698. CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
  699. CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
  700. &ccm_anatop->pll_video_set);
  701. break;
  702. }
  703. writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
  704. &ccm_anatop->pll_video_num);
  705. writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
  706. &ccm_anatop->pll_video_denom);
  707. /* Wait PLL5 lock */
  708. start = get_timer(0); /* Get current timestamp */
  709. do {
  710. reg = readl(&ccm_anatop->pll_video);
  711. if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
  712. /* Enable PLL out */
  713. writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
  714. &ccm_anatop->pll_video_set);
  715. return 0;
  716. }
  717. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  718. printf("Lock PLL5 timeout\n");
  719. return 1;
  720. }
  721. int set_clk_qspi(void)
  722. {
  723. u32 target;
  724. /* disable the clock gate first */
  725. clock_enable(CCGR_QSPI, 0);
  726. /* 49M: 392/2/4 */
  727. target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  728. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  729. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  730. clock_set_target_val(QSPI_CLK_ROOT, target);
  731. /* enable the clock gate */
  732. clock_enable(CCGR_QSPI, 1);
  733. return 0;
  734. }
  735. int set_clk_nand(void)
  736. {
  737. u32 target;
  738. /* disable the clock gate first */
  739. clock_enable(CCGR_RAWNAND, 0);
  740. enable_pll_enet();
  741. /* 100: 500/5 */
  742. target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
  743. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  744. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
  745. clock_set_target_val(NAND_CLK_ROOT, target);
  746. /* enable the clock gate */
  747. clock_enable(CCGR_RAWNAND, 1);
  748. return 0;
  749. }
  750. void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
  751. {
  752. u32 hck = MXC_HCLK/1000;
  753. u32 min = hck * 27;
  754. u32 max = hck * 54;
  755. u32 temp, best = 0;
  756. u32 i, j, pred = 1, postd = 1;
  757. u32 pll_div, pll_num, pll_denom, post_div = 0;
  758. u32 target;
  759. debug("mxs_set_lcdclk, freq = %d\n", freq);
  760. clock_enable(CCGR_LCDIF, 0);
  761. temp = (freq * 8 * 8);
  762. if (temp < min) {
  763. for (i = 1; i <= 4; i++) {
  764. if ((temp * (1 << i)) > min) {
  765. post_div = i;
  766. freq = (freq * (1 << i));
  767. break;
  768. }
  769. }
  770. if (5 == i) {
  771. printf("Fail to set rate to %dkhz", freq);
  772. return;
  773. }
  774. }
  775. for (i = 1; i <= 8; i++) {
  776. for (j = 1; j <= 8; j++) {
  777. temp = freq * i * j;
  778. if (temp > max || temp < min)
  779. continue;
  780. if (best == 0 || temp < best) {
  781. best = temp;
  782. pred = i;
  783. postd = j;
  784. }
  785. }
  786. }
  787. if (best == 0) {
  788. printf("Fail to set rate to %dkhz", freq);
  789. return;
  790. }
  791. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  792. pll_div = best / hck;
  793. pll_denom = 1000000;
  794. pll_num = (best - hck * pll_div) * pll_denom / hck;
  795. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  796. return;
  797. target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
  798. CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
  799. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
  800. clock_enable(CCGR_LCDIF, 1);
  801. }
  802. #ifdef CONFIG_FEC_MXC
  803. int set_clk_enet(enum enet_freq type)
  804. {
  805. u32 target;
  806. int ret;
  807. u32 enet1_ref, enet2_ref;
  808. /* disable the clock first */
  809. clock_enable(CCGR_ENET1, 0);
  810. clock_enable(CCGR_ENET2, 0);
  811. switch (type) {
  812. case ENET_125MHZ:
  813. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  814. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  815. break;
  816. case ENET_50MHZ:
  817. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  818. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  819. break;
  820. case ENET_25MHZ:
  821. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  822. enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  823. break;
  824. default:
  825. return -EINVAL;
  826. }
  827. ret = enable_pll_enet();
  828. if (ret != 0)
  829. return ret;
  830. /* set enet axi clock 196M: 392/2 */
  831. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
  832. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  833. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
  834. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  835. target = CLK_ROOT_ON | enet1_ref |
  836. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  837. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  838. clock_set_target_val(ENET1_REF_CLK_ROOT, target);
  839. target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  840. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  841. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  842. clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
  843. target = CLK_ROOT_ON | enet2_ref |
  844. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  845. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  846. clock_set_target_val(ENET2_REF_CLK_ROOT, target);
  847. target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  848. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  849. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  850. clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
  851. #ifdef CONFIG_FEC_MXC_25M_REF_CLK
  852. target = CLK_ROOT_ON |
  853. ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
  854. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  855. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  856. clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
  857. #endif
  858. /* enable clock */
  859. clock_enable(CCGR_ENET1, 1);
  860. clock_enable(CCGR_ENET2, 1);
  861. return 0;
  862. }
  863. #endif
  864. /* Configure PLL/PFD freq */
  865. void clock_init(void)
  866. {
  867. /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  868. * In u-boot, we have to:
  869. * 1. Configure PFD3- PFD7 for freq we needed in u-boot
  870. * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
  871. * interface. The clocks for these peripherals are enabled after this intialization.
  872. * 3. Other peripherals with set clock rate interface does not be set in this function.
  873. */
  874. u32 reg;
  875. /*
  876. * Configure PFD4 to 392M
  877. * 480M * 18 / 0x16 = 392M
  878. */
  879. reg = readl(&ccm_anatop->pfd_480b);
  880. reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
  881. CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
  882. reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
  883. writel(reg, &ccm_anatop->pfd_480b);
  884. init_clk_esdhc();
  885. init_clk_uart();
  886. init_clk_weim();
  887. init_clk_ecspi();
  888. init_clk_wdog();
  889. #ifdef CONFIG_MXC_EPDC
  890. init_clk_epdc();
  891. #endif
  892. enable_usboh3_clk(1);
  893. clock_enable(CCGR_SNVS, 1);
  894. #ifdef CONFIG_NAND_MXS
  895. clock_enable(CCGR_RAWNAND, 1);
  896. #endif
  897. if (IS_ENABLED(CONFIG_IMX_RDC)) {
  898. clock_enable(CCGR_RDC, 1);
  899. clock_enable(CCGR_SEMA1, 1);
  900. clock_enable(CCGR_SEMA2, 1);
  901. }
  902. }
  903. #ifdef CONFIG_IMX_HAB
  904. void hab_caam_clock_enable(unsigned char enable)
  905. {
  906. if (enable)
  907. clock_enable(CCGR_CAAM, 1);
  908. else
  909. clock_enable(CCGR_CAAM, 0);
  910. }
  911. #endif
  912. #ifdef CONFIG_MXC_EPDC
  913. void epdc_clock_enable(void)
  914. {
  915. clock_enable(CCGR_EPDC, 1);
  916. }
  917. void epdc_clock_disable(void)
  918. {
  919. clock_enable(CCGR_EPDC, 0);
  920. }
  921. #endif
  922. #ifndef CONFIG_SPL_BUILD
  923. /*
  924. * Dump some core clockes.
  925. */
  926. int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  927. char *const argv[])
  928. {
  929. u32 freq;
  930. freq = decode_pll(PLL_CORE, MXC_HCLK);
  931. printf("PLL_CORE %8d MHz\n", freq / 1000000);
  932. freq = decode_pll(PLL_SYS, MXC_HCLK);
  933. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  934. freq = decode_pll(PLL_ENET, MXC_HCLK);
  935. printf("PLL_NET %8d MHz\n", freq / 1000000);
  936. printf("\n");
  937. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  938. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  939. #ifdef CONFIG_MXC_SPI
  940. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  941. #endif
  942. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  943. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  944. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  945. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  946. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  947. printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  948. return 0;
  949. }
  950. U_BOOT_CMD(
  951. clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
  952. "display clocks",
  953. ""
  954. );
  955. #endif