ddr.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Gateworks Corporation
  4. * Author: Tim Harvey <tharvey@gateworks.com>
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <log.h>
  9. #include <linux/types.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/mx6-ddr.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/io.h>
  14. #include <asm/types.h>
  15. #include <wait_bit.h>
  16. #if defined(CONFIG_MX6_DDRCAL)
  17. static void reset_read_data_fifos(void)
  18. {
  19. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  20. /* Reset data FIFOs twice. */
  21. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  22. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  23. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  24. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  25. }
  26. static void precharge_all(const bool cs0_enable, const bool cs1_enable)
  27. {
  28. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  29. /*
  30. * Issue the Precharge-All command to the DDR device for both
  31. * chip selects. Note, CON_REQ bit should also remain set. If
  32. * only using one chip select, then precharge only the desired
  33. * chip select.
  34. */
  35. if (cs0_enable) { /* CS0 */
  36. writel(0x04008050, &mmdc0->mdscr);
  37. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  38. }
  39. if (cs1_enable) { /* CS1 */
  40. writel(0x04008058, &mmdc0->mdscr);
  41. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  42. }
  43. }
  44. static void force_delay_measurement(int bus_size)
  45. {
  46. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  47. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  48. writel(0x800, &mmdc0->mpmur0);
  49. if (bus_size == 0x2)
  50. writel(0x800, &mmdc1->mpmur0);
  51. }
  52. static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
  53. {
  54. u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
  55. /*
  56. * DQS gating absolute offset should be modified from reflecting
  57. * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
  58. */
  59. val_ctrl = readl(reg_ctrl);
  60. val_ctrl &= 0xf0000000;
  61. dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
  62. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  63. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  64. val_ctrl |= dg_dl_abs_offset + dg_hc_del;
  65. dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
  66. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  67. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  68. val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
  69. writel(val_ctrl, reg_ctrl);
  70. }
  71. static void correct_mpwldectr_result(void *reg)
  72. {
  73. /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
  74. const unsigned int limit = 0x148;
  75. u32 val = readl(reg);
  76. u32 old = val;
  77. if ((val & 0x17f) > limit)
  78. val &= 0xffff << 16;
  79. if (((val >> 16) & 0x17f) > limit)
  80. val &= 0xffff;
  81. if (old != val)
  82. writel(val, reg);
  83. }
  84. int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  85. {
  86. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  87. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  88. u32 esdmisc_val, zq_val;
  89. u32 errors = 0;
  90. u32 ldectrl[4] = {0};
  91. u32 ddr_mr1 = 0x4;
  92. u32 rwalat_max;
  93. /*
  94. * Stash old values in case calibration fails,
  95. * we need to restore them
  96. */
  97. ldectrl[0] = readl(&mmdc0->mpwldectrl0);
  98. ldectrl[1] = readl(&mmdc0->mpwldectrl1);
  99. if (sysinfo->dsize == 2) {
  100. ldectrl[2] = readl(&mmdc1->mpwldectrl0);
  101. ldectrl[3] = readl(&mmdc1->mpwldectrl1);
  102. }
  103. /* disable DDR logic power down timer */
  104. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  105. /* disable Adopt power down timer */
  106. setbits_le32(&mmdc0->mapsr, 0x1);
  107. debug("Starting write leveling calibration.\n");
  108. /*
  109. * 2. disable auto refresh and ZQ calibration
  110. * before proceeding with Write Leveling calibration
  111. */
  112. esdmisc_val = readl(&mmdc0->mdref);
  113. writel(0x0000C000, &mmdc0->mdref);
  114. zq_val = readl(&mmdc0->mpzqhwctrl);
  115. writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
  116. /* 3. increase walat and ralat to maximum */
  117. rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
  118. setbits_le32(&mmdc0->mdmisc, rwalat_max);
  119. if (sysinfo->dsize == 2)
  120. setbits_le32(&mmdc1->mdmisc, rwalat_max);
  121. /*
  122. * 4 & 5. Configure the external DDR device to enter write-leveling
  123. * mode through Load Mode Register command.
  124. * Register setting:
  125. * Bits[31:16] MR1 value (0x0080 write leveling enable)
  126. * Bit[9] set WL_EN to enable MMDC DQS output
  127. * Bits[6:4] set CMD bits for Load Mode Register programming
  128. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  129. */
  130. writel(0x00808231, &mmdc0->mdscr);
  131. /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
  132. writel(0x00000001, &mmdc0->mpwlgcr);
  133. /*
  134. * 7. Upon completion of this process the MMDC de-asserts
  135. * the MPWLGCR[HW_WL_EN]
  136. */
  137. wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
  138. /*
  139. * 8. check for any errors: check both PHYs for x64 configuration,
  140. * if x32, check only PHY0
  141. */
  142. if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
  143. errors |= 1;
  144. if (sysinfo->dsize == 2)
  145. if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
  146. errors |= 2;
  147. debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
  148. /* check to see if cal failed */
  149. if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
  150. (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
  151. ((sysinfo->dsize < 2) ||
  152. ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
  153. (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
  154. debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
  155. writel(ldectrl[0], &mmdc0->mpwldectrl0);
  156. writel(ldectrl[1], &mmdc0->mpwldectrl1);
  157. if (sysinfo->dsize == 2) {
  158. writel(ldectrl[2], &mmdc1->mpwldectrl0);
  159. writel(ldectrl[3], &mmdc1->mpwldectrl1);
  160. }
  161. errors |= 4;
  162. }
  163. correct_mpwldectr_result(&mmdc0->mpwldectrl0);
  164. correct_mpwldectr_result(&mmdc0->mpwldectrl1);
  165. if (sysinfo->dsize == 2) {
  166. correct_mpwldectr_result(&mmdc1->mpwldectrl0);
  167. correct_mpwldectr_result(&mmdc1->mpwldectrl1);
  168. }
  169. /*
  170. * User should issue MRS command to exit write leveling mode
  171. * through Load Mode Register command
  172. * Register setting:
  173. * Bits[31:16] MR1 value "ddr_mr1" value from initialization
  174. * Bit[9] clear WL_EN to disable MMDC DQS output
  175. * Bits[6:4] set CMD bits for Load Mode Register programming
  176. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  177. */
  178. writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
  179. /* re-enable auto refresh and zq cal */
  180. writel(esdmisc_val, &mmdc0->mdref);
  181. writel(zq_val, &mmdc0->mpzqhwctrl);
  182. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  183. readl(&mmdc0->mpwldectrl0));
  184. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  185. readl(&mmdc0->mpwldectrl1));
  186. if (sysinfo->dsize == 2) {
  187. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  188. readl(&mmdc1->mpwldectrl0));
  189. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  190. readl(&mmdc1->mpwldectrl1));
  191. }
  192. /* We must force a readback of these values, to get them to stick */
  193. readl(&mmdc0->mpwldectrl0);
  194. readl(&mmdc0->mpwldectrl1);
  195. if (sysinfo->dsize == 2) {
  196. readl(&mmdc1->mpwldectrl0);
  197. readl(&mmdc1->mpwldectrl1);
  198. }
  199. /* enable DDR logic power down timer: */
  200. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  201. /* Enable Adopt power down timer: */
  202. clrbits_le32(&mmdc0->mapsr, 0x1);
  203. /* Clear CON_REQ */
  204. writel(0, &mmdc0->mdscr);
  205. return errors;
  206. }
  207. static void mmdc_set_sdqs(bool set)
  208. {
  209. struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
  210. (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  211. struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
  212. (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  213. int i, sdqs_cnt;
  214. u32 sdqs;
  215. if (is_mx6sx()) {
  216. sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
  217. sdqs_cnt = 2;
  218. } else { /* MX6DQ */
  219. sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
  220. sdqs_cnt = 8;
  221. }
  222. for (i = 0; i < sdqs_cnt; i++) {
  223. if (set)
  224. setbits_le32(sdqs + (4 * i), 0x7000);
  225. else
  226. clrbits_le32(sdqs + (4 * i), 0x7000);
  227. }
  228. }
  229. int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  230. {
  231. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  232. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  233. bool cs0_enable;
  234. bool cs1_enable;
  235. bool cs0_enable_initial;
  236. bool cs1_enable_initial;
  237. u32 esdmisc_val;
  238. u32 temp_ref;
  239. u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
  240. u32 errors = 0;
  241. u32 initdelay = 0x40404040;
  242. /* check to see which chip selects are enabled */
  243. cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
  244. cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
  245. /* disable DDR logic power down timer: */
  246. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  247. /* disable Adopt power down timer: */
  248. setbits_le32(&mmdc0->mapsr, 0x1);
  249. /* set DQS pull ups */
  250. mmdc_set_sdqs(true);
  251. /* Save old RALAT and WALAT values */
  252. esdmisc_val = readl(&mmdc0->mdmisc);
  253. setbits_le32(&mmdc0->mdmisc,
  254. (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
  255. /* Disable auto refresh before proceeding with calibration */
  256. temp_ref = readl(&mmdc0->mdref);
  257. writel(0x0000c000, &mmdc0->mdref);
  258. /*
  259. * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
  260. * this also sets the CON_REQ bit.
  261. */
  262. if (cs0_enable_initial)
  263. writel(0x00008020, &mmdc0->mdscr);
  264. if (cs1_enable_initial)
  265. writel(0x00008028, &mmdc0->mdscr);
  266. /* poll to make sure the con_ack bit was asserted */
  267. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  268. /*
  269. * Check MDMISC register CALIB_PER_CS to see which CS calibration
  270. * is targeted to (under normal cases, it should be cleared
  271. * as this is the default value, indicating calibration is directed
  272. * to CS0).
  273. * Disable the other chip select not being target for calibration
  274. * to avoid any potential issues. This will get re-enabled at end
  275. * of calibration.
  276. */
  277. if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
  278. clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
  279. else
  280. clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
  281. /*
  282. * Check to see which chip selects are now enabled for
  283. * the remainder of the calibration.
  284. */
  285. cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
  286. cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
  287. precharge_all(cs0_enable, cs1_enable);
  288. /* Write the pre-defined value into MPPDCMPR1 */
  289. writel(pddword, &mmdc0->mppdcmpr1);
  290. /*
  291. * Issue a write access to the external DDR device by setting
  292. * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
  293. * this bit until it clears to indicate completion of the write access.
  294. */
  295. setbits_le32(&mmdc0->mpswdar0, 1);
  296. wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
  297. /* Set the RD_DL_ABS# bits to their default values
  298. * (will be calibrated later in the read delay-line calibration).
  299. * Both PHYs for x64 configuration, if x32, do only PHY0.
  300. */
  301. writel(initdelay, &mmdc0->mprddlctl);
  302. if (sysinfo->dsize == 0x2)
  303. writel(initdelay, &mmdc1->mprddlctl);
  304. /* Force a measurment, for previous delay setup to take effect. */
  305. force_delay_measurement(sysinfo->dsize);
  306. /*
  307. * ***************************
  308. * Read DQS Gating calibration
  309. * ***************************
  310. */
  311. debug("Starting Read DQS Gating calibration.\n");
  312. /*
  313. * Reset the read data FIFOs (two resets); only need to issue reset
  314. * to PHY0 since in x64 mode, the reset will also go to PHY1.
  315. */
  316. reset_read_data_fifos();
  317. /*
  318. * Start the automatic read DQS gating calibration process by
  319. * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
  320. * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
  321. * to indicate completion.
  322. * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
  323. * no errors were seen during calibration.
  324. */
  325. /*
  326. * Set bit 30: chooses option to wait 32 cycles instead of
  327. * 16 before comparing read data.
  328. */
  329. setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  330. if (sysinfo->dsize == 2)
  331. setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  332. /* Set bit 28 to start automatic read DQS gating calibration */
  333. setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
  334. /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
  335. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
  336. /*
  337. * Check to see if any errors were encountered during calibration
  338. * (check MPDGCTRL0[HW_DG_ERR]).
  339. * Check both PHYs for x64 configuration, if x32, check only PHY0.
  340. */
  341. if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
  342. errors |= 1;
  343. if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
  344. errors |= 2;
  345. /* now disable mpdgctrl0[DG_CMP_CYC] */
  346. clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  347. if (sysinfo->dsize == 2)
  348. clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  349. /*
  350. * DQS gating absolute offset should be modified from
  351. * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
  352. * reflecting (HW_DG_UPx - 0x80)
  353. */
  354. modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
  355. &mmdc0->mpdgctrl0);
  356. modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
  357. &mmdc0->mpdgctrl1);
  358. if (sysinfo->dsize == 0x2) {
  359. modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
  360. &mmdc1->mpdgctrl0);
  361. modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
  362. &mmdc1->mpdgctrl1);
  363. }
  364. debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
  365. /*
  366. * **********************
  367. * Read Delay calibration
  368. * **********************
  369. */
  370. debug("Starting Read Delay calibration.\n");
  371. reset_read_data_fifos();
  372. /*
  373. * 4. Issue the Precharge-All command to the DDR device for both
  374. * chip selects. If only using one chip select, then precharge
  375. * only the desired chip select.
  376. */
  377. precharge_all(cs0_enable, cs1_enable);
  378. /*
  379. * 9. Read delay-line calibration
  380. * Start the automatic read calibration process by asserting
  381. * MPRDDLHWCTL[HW_RD_DL_EN].
  382. */
  383. writel(0x00000030, &mmdc0->mprddlhwctl);
  384. /*
  385. * 10. poll for completion
  386. * MMDC indicates that the write data calibration had finished by
  387. * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
  388. * no error bits were set.
  389. */
  390. wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
  391. /* check both PHYs for x64 configuration, if x32, check only PHY0 */
  392. if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
  393. errors |= 4;
  394. if ((sysinfo->dsize == 0x2) &&
  395. (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
  396. errors |= 8;
  397. debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
  398. /*
  399. * ***********************
  400. * Write Delay Calibration
  401. * ***********************
  402. */
  403. debug("Starting Write Delay calibration.\n");
  404. reset_read_data_fifos();
  405. /*
  406. * 4. Issue the Precharge-All command to the DDR device for both
  407. * chip selects. If only using one chip select, then precharge
  408. * only the desired chip select.
  409. */
  410. precharge_all(cs0_enable, cs1_enable);
  411. /*
  412. * 8. Set the WR_DL_ABS# bits to their default values.
  413. * Both PHYs for x64 configuration, if x32, do only PHY0.
  414. */
  415. writel(initdelay, &mmdc0->mpwrdlctl);
  416. if (sysinfo->dsize == 0x2)
  417. writel(initdelay, &mmdc1->mpwrdlctl);
  418. /*
  419. * XXX This isn't in the manual. Force a measurement,
  420. * for previous delay setup to effect.
  421. */
  422. force_delay_measurement(sysinfo->dsize);
  423. /*
  424. * 9. 10. Start the automatic write calibration process
  425. * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
  426. */
  427. writel(0x00000030, &mmdc0->mpwrdlhwctl);
  428. /*
  429. * Poll for completion.
  430. * MMDC indicates that the write data calibration had finished
  431. * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
  432. * Also, ensure that no error bits were set.
  433. */
  434. wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
  435. /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
  436. if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
  437. errors |= 16;
  438. if ((sysinfo->dsize == 0x2) &&
  439. (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
  440. errors |= 32;
  441. debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
  442. reset_read_data_fifos();
  443. /* Enable DDR logic power down timer */
  444. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  445. /* Enable Adopt power down timer */
  446. clrbits_le32(&mmdc0->mapsr, 0x1);
  447. /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
  448. writel(esdmisc_val, &mmdc0->mdmisc);
  449. /* Clear DQS pull ups */
  450. mmdc_set_sdqs(false);
  451. /* Re-enable SDE (chip selects) if they were set initially */
  452. if (cs1_enable_initial)
  453. /* Set SDE_1 */
  454. setbits_le32(&mmdc0->mdctl, 1 << 30);
  455. if (cs0_enable_initial)
  456. /* Set SDE_0 */
  457. setbits_le32(&mmdc0->mdctl, 1 << 31);
  458. /* Re-enable to auto refresh */
  459. writel(temp_ref, &mmdc0->mdref);
  460. /* Clear the MDSCR (including the con_req bit) */
  461. writel(0x0, &mmdc0->mdscr); /* CS0 */
  462. /* Poll to make sure the con_ack bit is clear */
  463. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
  464. /*
  465. * Print out the registers that were updated as a result
  466. * of the calibration process.
  467. */
  468. debug("MMDC registers updated from calibration\n");
  469. debug("Read DQS gating calibration:\n");
  470. debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
  471. debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
  472. if (sysinfo->dsize == 2) {
  473. debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
  474. debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
  475. }
  476. debug("Read calibration:\n");
  477. debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
  478. if (sysinfo->dsize == 2)
  479. debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
  480. debug("Write calibration:\n");
  481. debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
  482. if (sysinfo->dsize == 2)
  483. debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
  484. /*
  485. * Registers below are for debugging purposes. These print out
  486. * the upper and lower boundaries captured during
  487. * read DQS gating calibration.
  488. */
  489. debug("Status registers bounds for read DQS gating:\n");
  490. debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
  491. debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
  492. debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
  493. debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
  494. if (sysinfo->dsize == 2) {
  495. debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
  496. debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
  497. debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
  498. debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
  499. }
  500. debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
  501. return errors;
  502. }
  503. #endif
  504. #if defined(CONFIG_MX6SX)
  505. /* Configure MX6SX mmdc iomux */
  506. void mx6sx_dram_iocfg(unsigned width,
  507. const struct mx6sx_iomux_ddr_regs *ddr,
  508. const struct mx6sx_iomux_grp_regs *grp)
  509. {
  510. struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
  511. struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
  512. mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  513. mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
  514. /* DDR IO TYPE */
  515. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  516. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  517. /* CLOCK */
  518. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  519. /* ADDRESS */
  520. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  521. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  522. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  523. /* Control */
  524. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  525. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  526. writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
  527. writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
  528. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  529. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  530. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  531. /* Data Strobes */
  532. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  533. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  534. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  535. if (width >= 32) {
  536. writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
  537. writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
  538. }
  539. /* Data */
  540. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  541. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  542. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  543. if (width >= 32) {
  544. writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
  545. writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
  546. }
  547. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  548. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  549. if (width >= 32) {
  550. writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
  551. writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
  552. }
  553. }
  554. #endif
  555. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  556. void mx6ul_dram_iocfg(unsigned width,
  557. const struct mx6ul_iomux_ddr_regs *ddr,
  558. const struct mx6ul_iomux_grp_regs *grp)
  559. {
  560. struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
  561. struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
  562. mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
  563. mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
  564. /* DDR IO TYPE */
  565. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  566. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  567. /* CLOCK */
  568. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  569. /* ADDRESS */
  570. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  571. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  572. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  573. /* Control */
  574. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  575. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  576. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  577. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  578. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  579. /* Data Strobes */
  580. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  581. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  582. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  583. /* Data */
  584. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  585. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  586. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  587. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  588. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  589. }
  590. #endif
  591. #if defined(CONFIG_MX6SL)
  592. void mx6sl_dram_iocfg(unsigned width,
  593. const struct mx6sl_iomux_ddr_regs *ddr,
  594. const struct mx6sl_iomux_grp_regs *grp)
  595. {
  596. struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
  597. struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
  598. mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
  599. mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
  600. /* DDR IO TYPE */
  601. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  602. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  603. /* CLOCK */
  604. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  605. /* ADDRESS */
  606. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  607. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  608. mx6_grp_iomux->grp_addds = grp->grp_addds;
  609. /* Control */
  610. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  611. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  612. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  613. /* Data Strobes */
  614. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  615. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  616. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  617. if (width >= 32) {
  618. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  619. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  620. }
  621. /* Data */
  622. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  623. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  624. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  625. if (width >= 32) {
  626. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  627. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  628. }
  629. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  630. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  631. if (width >= 32) {
  632. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  633. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  634. }
  635. }
  636. #endif
  637. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
  638. /* Configure MX6DQ mmdc iomux */
  639. void mx6dq_dram_iocfg(unsigned width,
  640. const struct mx6dq_iomux_ddr_regs *ddr,
  641. const struct mx6dq_iomux_grp_regs *grp)
  642. {
  643. volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
  644. volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
  645. mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  646. mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
  647. /* DDR IO Type */
  648. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  649. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  650. /* Clock */
  651. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  652. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  653. /* Address */
  654. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  655. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  656. mx6_grp_iomux->grp_addds = grp->grp_addds;
  657. /* Control */
  658. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  659. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  660. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  661. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  662. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  663. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  664. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  665. /* Data Strobes */
  666. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  667. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  668. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  669. if (width >= 32) {
  670. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  671. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  672. }
  673. if (width >= 64) {
  674. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  675. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  676. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  677. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  678. }
  679. /* Data */
  680. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  681. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  682. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  683. if (width >= 32) {
  684. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  685. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  686. }
  687. if (width >= 64) {
  688. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  689. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  690. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  691. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  692. }
  693. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  694. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  695. if (width >= 32) {
  696. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  697. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  698. }
  699. if (width >= 64) {
  700. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  701. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  702. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  703. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  704. }
  705. }
  706. #endif
  707. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  708. /* Configure MX6SDL mmdc iomux */
  709. void mx6sdl_dram_iocfg(unsigned width,
  710. const struct mx6sdl_iomux_ddr_regs *ddr,
  711. const struct mx6sdl_iomux_grp_regs *grp)
  712. {
  713. volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
  714. volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
  715. mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
  716. mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
  717. /* DDR IO Type */
  718. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  719. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  720. /* Clock */
  721. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  722. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  723. /* Address */
  724. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  725. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  726. mx6_grp_iomux->grp_addds = grp->grp_addds;
  727. /* Control */
  728. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  729. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  730. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  731. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  732. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  733. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  734. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  735. /* Data Strobes */
  736. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  737. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  738. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  739. if (width >= 32) {
  740. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  741. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  742. }
  743. if (width >= 64) {
  744. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  745. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  746. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  747. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  748. }
  749. /* Data */
  750. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  751. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  752. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  753. if (width >= 32) {
  754. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  755. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  756. }
  757. if (width >= 64) {
  758. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  759. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  760. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  761. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  762. }
  763. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  764. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  765. if (width >= 32) {
  766. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  767. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  768. }
  769. if (width >= 64) {
  770. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  771. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  772. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  773. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  774. }
  775. }
  776. #endif
  777. /*
  778. * Configure mx6 mmdc registers based on:
  779. * - board-specific memory configuration
  780. * - board-specific calibration data
  781. * - ddr3/lpddr2 chip details
  782. *
  783. * The various calculations here are derived from the Freescale
  784. * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
  785. * MMDC configuration registers based on memory system and memory chip
  786. * parameters.
  787. *
  788. * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
  789. * configuration registers based on memory system and memory chip
  790. * parameters.
  791. *
  792. * The defaults here are those which were specified in the spreadsheet.
  793. * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
  794. * and/or IMX6SLRM section titled MMDC initialization.
  795. */
  796. #define MR(val, ba, cmd, cs1) \
  797. ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
  798. #define MMDC1(entry, value) do { \
  799. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
  800. mmdc1->entry = value; \
  801. } while (0)
  802. /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
  803. #define BOOT_CFG3_DDR_MASK 0x30
  804. #define BOOT_CFG3_EXT_DDR_MASK 0x33
  805. #define DDR_MMAP_NOC_SINGLE 0
  806. #define DDR_MMAP_NOC_DUAL 0x31
  807. /* NoC ACTIVATE shifts */
  808. #define NOC_RD_SHIFT 0
  809. #define NOC_FAW_PERIOD_SHIFT 4
  810. #define NOC_FAW_BANKS_SHIFT 10
  811. /* NoC DdrTiming shifts */
  812. #define NOC_ACT_TO_ACT_SHIFT 0
  813. #define NOC_RD_TO_MISS_SHIFT 6
  814. #define NOC_WR_TO_MISS_SHIFT 12
  815. #define NOC_BURST_LEN_SHIFT 18
  816. #define NOC_RD_TO_WR_SHIFT 21
  817. #define NOC_WR_TO_RD_SHIFT 26
  818. #define NOC_BW_RATIO_SHIFT 31
  819. /*
  820. * According JESD209-2B-LPDDR2: Table 103
  821. * WL: write latency
  822. */
  823. static int lpddr2_wl(uint32_t mem_speed)
  824. {
  825. switch (mem_speed) {
  826. case 1066:
  827. case 933:
  828. return 4;
  829. case 800:
  830. return 3;
  831. case 677:
  832. case 533:
  833. return 2;
  834. case 400:
  835. case 333:
  836. return 1;
  837. default:
  838. puts("invalid memory speed\n");
  839. hang();
  840. }
  841. return 0;
  842. }
  843. /*
  844. * According JESD209-2B-LPDDR2: Table 103
  845. * RL: read latency
  846. */
  847. static int lpddr2_rl(uint32_t mem_speed)
  848. {
  849. switch (mem_speed) {
  850. case 1066:
  851. return 8;
  852. case 933:
  853. return 7;
  854. case 800:
  855. return 6;
  856. case 677:
  857. return 5;
  858. case 533:
  859. return 4;
  860. case 400:
  861. case 333:
  862. return 3;
  863. default:
  864. puts("invalid memory speed\n");
  865. hang();
  866. }
  867. return 0;
  868. }
  869. void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  870. const struct mx6_mmdc_calibration *calib,
  871. const struct mx6_lpddr2_cfg *lpddr2_cfg)
  872. {
  873. volatile struct mmdc_p_regs *mmdc0;
  874. u32 val;
  875. u8 tcke, tcksrx, tcksre, trrd;
  876. u8 twl, txp, tfaw, tcl;
  877. u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
  878. u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
  879. u16 cs0_end;
  880. u8 coladdr;
  881. int clkper; /* clock period in picoseconds */
  882. int clock; /* clock freq in mHz */
  883. int cs;
  884. /* only support 16/32 bits */
  885. if (sysinfo->dsize > 1)
  886. hang();
  887. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  888. clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
  889. clkper = (1000 * 1000) / clock; /* pico seconds */
  890. twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
  891. /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
  892. switch (lpddr2_cfg->density) {
  893. case 1:
  894. case 2:
  895. case 4:
  896. trfc = DIV_ROUND_UP(130000, clkper) - 1;
  897. txsr = DIV_ROUND_UP(140000, clkper) - 1;
  898. break;
  899. case 8:
  900. trfc = DIV_ROUND_UP(210000, clkper) - 1;
  901. txsr = DIV_ROUND_UP(220000, clkper) - 1;
  902. break;
  903. default:
  904. /*
  905. * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
  906. */
  907. hang();
  908. break;
  909. }
  910. /*
  911. * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
  912. * set them to 0. */
  913. txp = DIV_ROUND_UP(7500, clkper) - 1;
  914. tcke = 3;
  915. if (lpddr2_cfg->mem_speed == 333)
  916. tfaw = DIV_ROUND_UP(60000, clkper) - 1;
  917. else
  918. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  919. trrd = DIV_ROUND_UP(10000, clkper) - 1;
  920. /* tckesr for LPDDR2 */
  921. tcksre = DIV_ROUND_UP(15000, clkper);
  922. tcksrx = tcksre;
  923. twr = DIV_ROUND_UP(15000, clkper) - 1;
  924. /*
  925. * tMRR: 2, tMRW: 5
  926. * tMRD should be set to max(tMRR, tMRW)
  927. */
  928. tmrd = 5;
  929. tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
  930. /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
  931. trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
  932. trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
  933. clkper / 10) - 1;
  934. trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
  935. trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
  936. /* To LPDDR2, CL in MDCFG0 refers to RL */
  937. tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
  938. twtr = DIV_ROUND_UP(7500, clkper) - 1;
  939. trtp = DIV_ROUND_UP(7500, clkper) - 1;
  940. cs0_end = 4 * sysinfo->cs_density - 1;
  941. debug("density:%d Gb (%d Gb per chip)\n",
  942. sysinfo->cs_density, lpddr2_cfg->density);
  943. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  944. debug("memspd:%d\n", lpddr2_cfg->mem_speed);
  945. debug("trcd_lp=%d\n", trcd_lp);
  946. debug("trppb_lp=%d\n", trppb_lp);
  947. debug("trpab_lp=%d\n", trpab_lp);
  948. debug("trc_lp=%d\n", trc_lp);
  949. debug("tcke=%d\n", tcke);
  950. debug("tcksrx=%d\n", tcksrx);
  951. debug("tcksre=%d\n", tcksre);
  952. debug("trfc=%d\n", trfc);
  953. debug("txsr=%d\n", txsr);
  954. debug("txp=%d\n", txp);
  955. debug("tfaw=%d\n", tfaw);
  956. debug("tcl=%d\n", tcl);
  957. debug("tras=%d\n", tras);
  958. debug("twr=%d\n", twr);
  959. debug("tmrd=%d\n", tmrd);
  960. debug("twl=%d\n", twl);
  961. debug("trtp=%d\n", trtp);
  962. debug("twtr=%d\n", twtr);
  963. debug("trrd=%d\n", trrd);
  964. debug("cs0_end=%d\n", cs0_end);
  965. debug("ncs=%d\n", sysinfo->ncs);
  966. /*
  967. * board-specific configuration:
  968. * These values are determined empirically and vary per board layout
  969. */
  970. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  971. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  972. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  973. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  974. mmdc0->mprddlctl = calib->p0_mprddlctl;
  975. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  976. mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
  977. /* Read data DQ Byte0-3 delay */
  978. mmdc0->mprddqby0dl = 0x33333333;
  979. mmdc0->mprddqby1dl = 0x33333333;
  980. if (sysinfo->dsize > 0) {
  981. mmdc0->mprddqby2dl = 0x33333333;
  982. mmdc0->mprddqby3dl = 0x33333333;
  983. }
  984. /* Write data DQ Byte0-3 delay */
  985. mmdc0->mpwrdqby0dl = 0xf3333333;
  986. mmdc0->mpwrdqby1dl = 0xf3333333;
  987. if (sysinfo->dsize > 0) {
  988. mmdc0->mpwrdqby2dl = 0xf3333333;
  989. mmdc0->mpwrdqby3dl = 0xf3333333;
  990. }
  991. /*
  992. * In LPDDR2 mode this register should be cleared,
  993. * so no termination will be activated.
  994. */
  995. mmdc0->mpodtctrl = 0;
  996. /* complete calibration */
  997. val = (1 << 11); /* Force measurement on delay-lines */
  998. mmdc0->mpmur0 = val;
  999. /* Step 1: configuration request */
  1000. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1001. /* Step 2: Timing configuration */
  1002. mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
  1003. (tfaw << 4) | tcl;
  1004. mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
  1005. mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
  1006. mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
  1007. (trppb_lp << 4) | trpab_lp;
  1008. mmdc0->mdotc = 0;
  1009. mmdc0->mdasp = cs0_end; /* CS addressing */
  1010. /* Step 3: Configure DDR type */
  1011. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1012. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1013. (sysinfo->ralat << 6) | (1 << 3);
  1014. /* Step 4: Configure delay while leaving reset */
  1015. mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
  1016. (sysinfo->rst_to_cke << 0);
  1017. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1018. coladdr = lpddr2_cfg->coladdr;
  1019. if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1020. coladdr += 4;
  1021. else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1022. coladdr += 1;
  1023. mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
  1024. (coladdr - 9) << 20 | /* COL */
  1025. (0 << 19) | /* Burst Length = 4 for LPDDR2 */
  1026. (sysinfo->dsize << 16); /* DDR data bus size */
  1027. /* Step 6: Perform ZQ calibration */
  1028. val = 0xa1390003; /* one-time HW ZQ calib */
  1029. mmdc0->mpzqhwctrl = val;
  1030. /* Step 7: Enable MMDC with desired chip select */
  1031. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1032. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1033. /* Step 8: Write Mode Registers to Init LPDDR2 devices */
  1034. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1035. /* MR63: reset */
  1036. mmdc0->mdscr = MR(63, 0, 3, cs);
  1037. /* MR10: calibration,
  1038. * 0xff is calibration command after intilization.
  1039. */
  1040. val = 0xA | (0xff << 8);
  1041. mmdc0->mdscr = MR(val, 0, 3, cs);
  1042. /* MR1 */
  1043. val = 0x1 | (0x82 << 8);
  1044. mmdc0->mdscr = MR(val, 0, 3, cs);
  1045. /* MR2 */
  1046. val = 0x2 | (0x04 << 8);
  1047. mmdc0->mdscr = MR(val, 0, 3, cs);
  1048. /* MR3 */
  1049. val = 0x3 | (0x02 << 8);
  1050. mmdc0->mdscr = MR(val, 0, 3, cs);
  1051. }
  1052. /* Step 10: Power down control and self-refresh */
  1053. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1054. 5 << 12 | /* PWDT_1: 256 cycles */
  1055. 5 << 8 | /* PWDT_0: 256 cycles */
  1056. 1 << 6 | /* BOTH_CS_PD */
  1057. (tcksrx & 0x7) << 3 |
  1058. (tcksre & 0x7);
  1059. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1060. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1061. val = 0xa1310003;
  1062. mmdc0->mpzqhwctrl = val;
  1063. /* Step 12: Configure and activate periodic refresh */
  1064. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1065. /* Step 13: Deassert config request - init complete */
  1066. mmdc0->mdscr = 0x00000000;
  1067. /* wait for auto-ZQ calibration to complete */
  1068. mdelay(1);
  1069. }
  1070. void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1071. const struct mx6_mmdc_calibration *calib,
  1072. const struct mx6_ddr3_cfg *ddr3_cfg)
  1073. {
  1074. volatile struct mmdc_p_regs *mmdc0;
  1075. volatile struct mmdc_p_regs *mmdc1;
  1076. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  1077. u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
  1078. u32 val;
  1079. u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
  1080. u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
  1081. u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
  1082. u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
  1083. u16 cs0_end;
  1084. u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
  1085. u8 coladdr;
  1086. int clkper; /* clock period in picoseconds */
  1087. int clock; /* clock freq in MHz */
  1088. int cs;
  1089. u16 mem_speed = ddr3_cfg->mem_speed;
  1090. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1091. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
  1092. mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1093. /* Limit mem_speed for MX6D/MX6Q */
  1094. if (is_mx6dq() || is_mx6dqp()) {
  1095. if (mem_speed > 1066)
  1096. mem_speed = 1066; /* 1066 MT/s */
  1097. tcwl = 4;
  1098. }
  1099. /* Limit mem_speed for MX6S/MX6DL */
  1100. else {
  1101. if (mem_speed > 800)
  1102. mem_speed = 800; /* 800 MT/s */
  1103. tcwl = 3;
  1104. }
  1105. clock = mem_speed / 2;
  1106. /*
  1107. * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
  1108. * up to 528 MHz, so reduce the clock to fit chip specs
  1109. */
  1110. if (is_mx6dq() || is_mx6dqp()) {
  1111. if (clock > 528)
  1112. clock = 528; /* 528 MHz */
  1113. }
  1114. clkper = (1000 * 1000) / clock; /* pico seconds */
  1115. todtlon = tcwl;
  1116. taxpd = tcwl;
  1117. tanpd = tcwl;
  1118. switch (ddr3_cfg->density) {
  1119. case 1: /* 1Gb per chip */
  1120. trfc = DIV_ROUND_UP(110000, clkper) - 1;
  1121. txs = DIV_ROUND_UP(120000, clkper) - 1;
  1122. break;
  1123. case 2: /* 2Gb per chip */
  1124. trfc = DIV_ROUND_UP(160000, clkper) - 1;
  1125. txs = DIV_ROUND_UP(170000, clkper) - 1;
  1126. break;
  1127. case 4: /* 4Gb per chip */
  1128. trfc = DIV_ROUND_UP(260000, clkper) - 1;
  1129. txs = DIV_ROUND_UP(270000, clkper) - 1;
  1130. break;
  1131. case 8: /* 8Gb per chip */
  1132. trfc = DIV_ROUND_UP(350000, clkper) - 1;
  1133. txs = DIV_ROUND_UP(360000, clkper) - 1;
  1134. break;
  1135. default:
  1136. /* invalid density */
  1137. puts("invalid chip density\n");
  1138. hang();
  1139. break;
  1140. }
  1141. txpr = txs;
  1142. switch (mem_speed) {
  1143. case 800:
  1144. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1145. tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1146. if (ddr3_cfg->pagesz == 1) {
  1147. tfaw = DIV_ROUND_UP(40000, clkper) - 1;
  1148. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1149. } else {
  1150. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1151. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1152. }
  1153. break;
  1154. case 1066:
  1155. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1156. tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
  1157. if (ddr3_cfg->pagesz == 1) {
  1158. tfaw = DIV_ROUND_UP(37500, clkper) - 1;
  1159. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  1160. } else {
  1161. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1162. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1163. }
  1164. break;
  1165. default:
  1166. puts("invalid memory speed\n");
  1167. hang();
  1168. break;
  1169. }
  1170. txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
  1171. tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
  1172. taonpd = DIV_ROUND_UP(2000, clkper) - 1;
  1173. tcksrx = tcksre;
  1174. taofpd = taonpd;
  1175. twr = DIV_ROUND_UP(15000, clkper) - 1;
  1176. tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
  1177. trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
  1178. tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
  1179. tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
  1180. trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
  1181. twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
  1182. trcd = trp;
  1183. trtp = twtr;
  1184. cs0_end = 4 * sysinfo->cs_density - 1;
  1185. debug("density:%d Gb (%d Gb per chip)\n",
  1186. sysinfo->cs_density, ddr3_cfg->density);
  1187. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  1188. debug("memspd:%d\n", mem_speed);
  1189. debug("tcke=%d\n", tcke);
  1190. debug("tcksrx=%d\n", tcksrx);
  1191. debug("tcksre=%d\n", tcksre);
  1192. debug("taofpd=%d\n", taofpd);
  1193. debug("taonpd=%d\n", taonpd);
  1194. debug("todtlon=%d\n", todtlon);
  1195. debug("tanpd=%d\n", tanpd);
  1196. debug("taxpd=%d\n", taxpd);
  1197. debug("trfc=%d\n", trfc);
  1198. debug("txs=%d\n", txs);
  1199. debug("txp=%d\n", txp);
  1200. debug("txpdll=%d\n", txpdll);
  1201. debug("tfaw=%d\n", tfaw);
  1202. debug("tcl=%d\n", tcl);
  1203. debug("trcd=%d\n", trcd);
  1204. debug("trp=%d\n", trp);
  1205. debug("trc=%d\n", trc);
  1206. debug("tras=%d\n", tras);
  1207. debug("twr=%d\n", twr);
  1208. debug("tmrd=%d\n", tmrd);
  1209. debug("tcwl=%d\n", tcwl);
  1210. debug("tdllk=%d\n", tdllk);
  1211. debug("trtp=%d\n", trtp);
  1212. debug("twtr=%d\n", twtr);
  1213. debug("trrd=%d\n", trrd);
  1214. debug("txpr=%d\n", txpr);
  1215. debug("cs0_end=%d\n", cs0_end);
  1216. debug("ncs=%d\n", sysinfo->ncs);
  1217. debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
  1218. debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
  1219. debug("SRT=%d\n", ddr3_cfg->SRT);
  1220. debug("twr=%d\n", twr);
  1221. /*
  1222. * board-specific configuration:
  1223. * These values are determined empirically and vary per board layout
  1224. * see:
  1225. * appnote, ddr3 spreadsheet
  1226. */
  1227. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  1228. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  1229. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  1230. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  1231. mmdc0->mprddlctl = calib->p0_mprddlctl;
  1232. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  1233. if (sysinfo->dsize > 1) {
  1234. MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
  1235. MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
  1236. MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
  1237. MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
  1238. MMDC1(mprddlctl, calib->p1_mprddlctl);
  1239. MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
  1240. }
  1241. /* Read data DQ Byte0-3 delay */
  1242. mmdc0->mprddqby0dl = 0x33333333;
  1243. mmdc0->mprddqby1dl = 0x33333333;
  1244. if (sysinfo->dsize > 0) {
  1245. mmdc0->mprddqby2dl = 0x33333333;
  1246. mmdc0->mprddqby3dl = 0x33333333;
  1247. }
  1248. if (sysinfo->dsize > 1) {
  1249. MMDC1(mprddqby0dl, 0x33333333);
  1250. MMDC1(mprddqby1dl, 0x33333333);
  1251. MMDC1(mprddqby2dl, 0x33333333);
  1252. MMDC1(mprddqby3dl, 0x33333333);
  1253. }
  1254. /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
  1255. val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
  1256. mmdc0->mpodtctrl = val;
  1257. if (sysinfo->dsize > 1)
  1258. MMDC1(mpodtctrl, val);
  1259. /* complete calibration */
  1260. val = (1 << 11); /* Force measurement on delay-lines */
  1261. mmdc0->mpmur0 = val;
  1262. if (sysinfo->dsize > 1)
  1263. MMDC1(mpmur0, val);
  1264. /* Step 1: configuration request */
  1265. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1266. /* Step 2: Timing configuration */
  1267. mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
  1268. (txpdll << 9) | (tfaw << 4) | tcl;
  1269. mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
  1270. (tras << 16) | (1 << 15) /* trpa */ |
  1271. (twr << 9) | (tmrd << 5) | tcwl;
  1272. mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
  1273. mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
  1274. (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
  1275. mmdc0->mdasp = cs0_end; /* CS addressing */
  1276. /* Step 3: Configure DDR type */
  1277. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1278. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1279. (sysinfo->ralat << 6);
  1280. /* Step 4: Configure delay while leaving reset */
  1281. mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
  1282. (sysinfo->rst_to_cke << 0);
  1283. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1284. coladdr = ddr3_cfg->coladdr;
  1285. if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1286. coladdr += 4;
  1287. else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1288. coladdr += 1;
  1289. mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
  1290. (coladdr - 9) << 20 | /* COL */
  1291. (1 << 19) | /* Burst Length = 8 for DDR3 */
  1292. (sysinfo->dsize << 16); /* DDR data bus size */
  1293. /* Step 6: Perform ZQ calibration */
  1294. val = 0xa1390001; /* one-time HW ZQ calib */
  1295. mmdc0->mpzqhwctrl = val;
  1296. if (sysinfo->dsize > 1)
  1297. MMDC1(mpzqhwctrl, val);
  1298. /* Step 7: Enable MMDC with desired chip select */
  1299. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1300. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1301. /* Step 8: Write Mode Registers to Init DDR3 devices */
  1302. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1303. /* MR2 */
  1304. val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
  1305. ((tcwl - 3) & 3) << 3;
  1306. debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
  1307. mmdc0->mdscr = MR(val, 2, 3, cs);
  1308. /* MR3 */
  1309. debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
  1310. mmdc0->mdscr = MR(0, 3, 3, cs);
  1311. /* MR1 */
  1312. val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
  1313. ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
  1314. debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
  1315. mmdc0->mdscr = MR(val, 1, 3, cs);
  1316. /* MR0 */
  1317. val = ((tcl - 1) << 4) | /* CAS */
  1318. (1 << 8) | /* DLL Reset */
  1319. ((twr - 3) << 9) | /* Write Recovery */
  1320. (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
  1321. debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
  1322. mmdc0->mdscr = MR(val, 0, 3, cs);
  1323. /* ZQ calibration */
  1324. val = (1 << 10);
  1325. mmdc0->mdscr = MR(val, 0, 4, cs);
  1326. }
  1327. /* Step 10: Power down control and self-refresh */
  1328. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1329. 5 << 12 | /* PWDT_1: 256 cycles */
  1330. 5 << 8 | /* PWDT_0: 256 cycles */
  1331. 1 << 6 | /* BOTH_CS_PD */
  1332. (tcksrx & 0x7) << 3 |
  1333. (tcksre & 0x7);
  1334. if (!sysinfo->pd_fast_exit)
  1335. mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
  1336. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1337. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1338. val = 0xa1390003;
  1339. mmdc0->mpzqhwctrl = val;
  1340. if (sysinfo->dsize > 1)
  1341. MMDC1(mpzqhwctrl, val);
  1342. /* Step 12: Configure and activate periodic refresh */
  1343. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1344. /*
  1345. * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
  1346. * configure it and disable MMDC arbitration/reordering (see EB828)
  1347. */
  1348. if (is_mx6dqp() &&
  1349. ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
  1350. (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
  1351. struct mx6dqp_noc_sched_regs *noc_sched =
  1352. (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
  1353. /*
  1354. * These values are fixed based on integration parameters and
  1355. * should not be modified
  1356. */
  1357. noc_sched->rlat = 0x00000040;
  1358. noc_sched->ipu1 = 0x00000020;
  1359. noc_sched->ipu2 = 0x00000020;
  1360. noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
  1361. (tfaw << NOC_FAW_PERIOD_SHIFT) |
  1362. (trrd << NOC_RD_SHIFT);
  1363. noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
  1364. << NOC_BW_RATIO_SHIFT) |
  1365. ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
  1366. ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
  1367. (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
  1368. ((tcwl + twr + trp + trcd)
  1369. << NOC_WR_TO_MISS_SHIFT) |
  1370. ((trtp + trp + trcd - 4)
  1371. << NOC_RD_TO_MISS_SHIFT) |
  1372. (trc << NOC_ACT_TO_ACT_SHIFT);
  1373. if (sysinfo->dsize == 2) {
  1374. if (ddr3_cfg->coladdr == 10) {
  1375. if (ddr3_cfg->rowaddr == 15 &&
  1376. sysinfo->ncs == 2)
  1377. noc_sched->ddrconf = 4;
  1378. else
  1379. noc_sched->ddrconf = 0;
  1380. } else if (ddr3_cfg->coladdr == 11) {
  1381. noc_sched->ddrconf = 1;
  1382. }
  1383. } else {
  1384. if (ddr3_cfg->coladdr == 9) {
  1385. if (ddr3_cfg->rowaddr == 13)
  1386. noc_sched->ddrconf = 2;
  1387. else if (ddr3_cfg->rowaddr == 14)
  1388. noc_sched->ddrconf = 15;
  1389. } else if (ddr3_cfg->coladdr == 10) {
  1390. if (ddr3_cfg->rowaddr == 14 &&
  1391. sysinfo->ncs == 2)
  1392. noc_sched->ddrconf = 14;
  1393. else if (ddr3_cfg->rowaddr == 15 &&
  1394. sysinfo->ncs == 2)
  1395. noc_sched->ddrconf = 9;
  1396. else
  1397. noc_sched->ddrconf = 3;
  1398. } else if (ddr3_cfg->coladdr == 11) {
  1399. if (ddr3_cfg->rowaddr == 15 &&
  1400. sysinfo->ncs == 2)
  1401. noc_sched->ddrconf = 4;
  1402. else
  1403. noc_sched->ddrconf = 0;
  1404. } else if (ddr3_cfg->coladdr == 12) {
  1405. if (ddr3_cfg->rowaddr == 14)
  1406. noc_sched->ddrconf = 1;
  1407. }
  1408. }
  1409. /* Disable MMDC arbitration/reordering */
  1410. mmdc0->maarcr = 0x14420000;
  1411. }
  1412. /* Step 13: Deassert config request - init complete */
  1413. mmdc0->mdscr = 0x00000000;
  1414. /* wait for auto-ZQ calibration to complete */
  1415. mdelay(1);
  1416. }
  1417. void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
  1418. struct mx6_mmdc_calibration *calib)
  1419. {
  1420. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1421. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1422. calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
  1423. calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
  1424. calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
  1425. calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
  1426. calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
  1427. calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
  1428. if (sysinfo->dsize == 2) {
  1429. calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
  1430. calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
  1431. calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
  1432. calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
  1433. calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
  1434. calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
  1435. }
  1436. }
  1437. void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1438. const struct mx6_mmdc_calibration *calib,
  1439. const void *ddr_cfg)
  1440. {
  1441. if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
  1442. mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
  1443. } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
  1444. mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
  1445. } else {
  1446. puts("Unsupported ddr type\n");
  1447. hang();
  1448. }
  1449. }