clock.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <div64.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. enum pll_clocks {
  16. PLL_SYS, /* System PLL */
  17. PLL_BUS, /* System Bus PLL*/
  18. PLL_USBOTG, /* OTG USB PLL */
  19. PLL_ENET, /* ENET PLL */
  20. PLL_AUDIO, /* AUDIO PLL */
  21. PLL_VIDEO, /* VIDEO PLL */
  22. };
  23. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  24. #ifdef CONFIG_MXC_OCOTP
  25. void enable_ocotp_clk(unsigned char enable)
  26. {
  27. u32 reg;
  28. reg = __raw_readl(&imx_ccm->CCGR2);
  29. if (enable)
  30. reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  31. else
  32. reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  33. __raw_writel(reg, &imx_ccm->CCGR2);
  34. }
  35. #endif
  36. #ifdef CONFIG_NAND_MXS
  37. void setup_gpmi_io_clk(u32 cfg)
  38. {
  39. /* Disable clocks per ERR007177 from MX6 errata */
  40. clrbits_le32(&imx_ccm->CCGR4,
  41. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  42. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  43. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  44. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  45. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  46. #if defined(CONFIG_MX6SX)
  47. clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  48. clrsetbits_le32(&imx_ccm->cs2cdr,
  49. MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  50. MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  51. MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
  52. cfg);
  53. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
  54. #else
  55. clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  56. clrsetbits_le32(&imx_ccm->cs2cdr,
  57. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  58. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  59. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  60. cfg);
  61. setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  62. #endif
  63. setbits_le32(&imx_ccm->CCGR4,
  64. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  65. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  66. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  67. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  68. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  69. }
  70. #endif
  71. void enable_usboh3_clk(unsigned char enable)
  72. {
  73. u32 reg;
  74. reg = __raw_readl(&imx_ccm->CCGR6);
  75. if (enable)
  76. reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  77. else
  78. reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  79. __raw_writel(reg, &imx_ccm->CCGR6);
  80. }
  81. #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
  82. void enable_enet_clk(unsigned char enable)
  83. {
  84. u32 mask, *addr;
  85. if (is_mx6ull()) {
  86. mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
  87. addr = &imx_ccm->CCGR0;
  88. } else if (is_mx6ul()) {
  89. mask = MXC_CCM_CCGR3_ENET_MASK;
  90. addr = &imx_ccm->CCGR3;
  91. } else {
  92. mask = MXC_CCM_CCGR1_ENET_MASK;
  93. addr = &imx_ccm->CCGR1;
  94. }
  95. if (enable)
  96. setbits_le32(addr, mask);
  97. else
  98. clrbits_le32(addr, mask);
  99. }
  100. #endif
  101. #ifdef CONFIG_MXC_UART
  102. void enable_uart_clk(unsigned char enable)
  103. {
  104. u32 mask;
  105. if (is_mx6ul() || is_mx6ull())
  106. mask = MXC_CCM_CCGR5_UART_MASK;
  107. else
  108. mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
  109. if (enable)
  110. setbits_le32(&imx_ccm->CCGR5, mask);
  111. else
  112. clrbits_le32(&imx_ccm->CCGR5, mask);
  113. }
  114. #endif
  115. #ifdef CONFIG_MMC
  116. int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
  117. {
  118. u32 mask;
  119. if (bus_num > 3)
  120. return -EINVAL;
  121. mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
  122. if (enable)
  123. setbits_le32(&imx_ccm->CCGR6, mask);
  124. else
  125. clrbits_le32(&imx_ccm->CCGR6, mask);
  126. return 0;
  127. }
  128. #endif
  129. #ifdef CONFIG_SYS_I2C_MXC
  130. /* i2c_num can be from 0 - 3 */
  131. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  132. {
  133. u32 reg;
  134. u32 mask;
  135. u32 *addr;
  136. if (i2c_num > 3)
  137. return -EINVAL;
  138. if (i2c_num < 3) {
  139. mask = MXC_CCM_CCGR_CG_MASK
  140. << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
  141. + (i2c_num << 1));
  142. reg = __raw_readl(&imx_ccm->CCGR2);
  143. if (enable)
  144. reg |= mask;
  145. else
  146. reg &= ~mask;
  147. __raw_writel(reg, &imx_ccm->CCGR2);
  148. } else {
  149. if (is_mx6sll())
  150. return -EINVAL;
  151. if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
  152. mask = MXC_CCM_CCGR6_I2C4_MASK;
  153. addr = &imx_ccm->CCGR6;
  154. } else {
  155. mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
  156. addr = &imx_ccm->CCGR1;
  157. }
  158. reg = __raw_readl(addr);
  159. if (enable)
  160. reg |= mask;
  161. else
  162. reg &= ~mask;
  163. __raw_writel(reg, addr);
  164. }
  165. return 0;
  166. }
  167. #endif
  168. /* spi_num can be from 0 - SPI_MAX_NUM */
  169. int enable_spi_clk(unsigned char enable, unsigned spi_num)
  170. {
  171. u32 reg;
  172. u32 mask;
  173. if (spi_num > SPI_MAX_NUM)
  174. return -EINVAL;
  175. mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
  176. reg = __raw_readl(&imx_ccm->CCGR1);
  177. if (enable)
  178. reg |= mask;
  179. else
  180. reg &= ~mask;
  181. __raw_writel(reg, &imx_ccm->CCGR1);
  182. return 0;
  183. }
  184. static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  185. {
  186. u32 div, test_div, pll_num, pll_denom;
  187. switch (pll) {
  188. case PLL_SYS:
  189. div = __raw_readl(&imx_ccm->analog_pll_sys);
  190. div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
  191. return (infreq * div) >> 1;
  192. case PLL_BUS:
  193. div = __raw_readl(&imx_ccm->analog_pll_528);
  194. div &= BM_ANADIG_PLL_528_DIV_SELECT;
  195. return infreq * (20 + (div << 1));
  196. case PLL_USBOTG:
  197. div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
  198. div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
  199. return infreq * (20 + (div << 1));
  200. case PLL_ENET:
  201. div = __raw_readl(&imx_ccm->analog_pll_enet);
  202. div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
  203. return 25000000 * (div + (div >> 1) + 1);
  204. case PLL_AUDIO:
  205. div = __raw_readl(&imx_ccm->analog_pll_audio);
  206. if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
  207. return 0;
  208. /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
  209. if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
  210. return MXC_HCLK;
  211. pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
  212. pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
  213. test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
  214. BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
  215. div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
  216. if (test_div == 3) {
  217. debug("Error test_div\n");
  218. return 0;
  219. }
  220. test_div = 1 << (2 - test_div);
  221. return infreq * (div + pll_num / pll_denom) / test_div;
  222. case PLL_VIDEO:
  223. div = __raw_readl(&imx_ccm->analog_pll_video);
  224. if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
  225. return 0;
  226. /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
  227. if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
  228. return MXC_HCLK;
  229. pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
  230. pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
  231. test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
  232. BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  233. div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  234. if (test_div == 3) {
  235. debug("Error test_div\n");
  236. return 0;
  237. }
  238. test_div = 1 << (2 - test_div);
  239. return infreq * (div + pll_num / pll_denom) / test_div;
  240. default:
  241. return 0;
  242. }
  243. /* NOTREACHED */
  244. }
  245. static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
  246. {
  247. u32 div;
  248. u64 freq;
  249. switch (pll) {
  250. case PLL_BUS:
  251. if (!is_mx6ul() && !is_mx6ull()) {
  252. if (pfd_num == 3) {
  253. /* No PFD3 on PLL2 */
  254. return 0;
  255. }
  256. }
  257. div = __raw_readl(&imx_ccm->analog_pfd_528);
  258. freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
  259. break;
  260. case PLL_USBOTG:
  261. div = __raw_readl(&imx_ccm->analog_pfd_480);
  262. freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
  263. break;
  264. default:
  265. /* No PFD on other PLL */
  266. return 0;
  267. }
  268. return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
  269. ANATOP_PFD_FRAC_SHIFT(pfd_num));
  270. }
  271. static u32 get_mcu_main_clk(void)
  272. {
  273. u32 reg, freq;
  274. reg = __raw_readl(&imx_ccm->cacrr);
  275. reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
  276. reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
  277. freq = decode_pll(PLL_SYS, MXC_HCLK);
  278. return freq / (reg + 1);
  279. }
  280. u32 get_periph_clk(void)
  281. {
  282. u32 reg, div = 0, freq = 0;
  283. reg = __raw_readl(&imx_ccm->cbcdr);
  284. if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
  285. div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
  286. MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
  287. reg = __raw_readl(&imx_ccm->cbcmr);
  288. reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
  289. reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
  290. switch (reg) {
  291. case 0:
  292. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  293. break;
  294. case 1:
  295. case 2:
  296. freq = MXC_HCLK;
  297. break;
  298. default:
  299. break;
  300. }
  301. } else {
  302. reg = __raw_readl(&imx_ccm->cbcmr);
  303. reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
  304. reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
  305. switch (reg) {
  306. case 0:
  307. freq = decode_pll(PLL_BUS, MXC_HCLK);
  308. break;
  309. case 1:
  310. freq = mxc_get_pll_pfd(PLL_BUS, 2);
  311. break;
  312. case 2:
  313. freq = mxc_get_pll_pfd(PLL_BUS, 0);
  314. break;
  315. case 3:
  316. /* static / 2 divider */
  317. freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
  318. break;
  319. default:
  320. break;
  321. }
  322. }
  323. return freq / (div + 1);
  324. }
  325. static u32 get_ipg_clk(void)
  326. {
  327. u32 reg, ipg_podf;
  328. reg = __raw_readl(&imx_ccm->cbcdr);
  329. reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
  330. ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
  331. return get_ahb_clk() / (ipg_podf + 1);
  332. }
  333. static u32 get_ipg_per_clk(void)
  334. {
  335. u32 reg, perclk_podf;
  336. reg = __raw_readl(&imx_ccm->cscmr1);
  337. if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
  338. is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
  339. if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
  340. return MXC_HCLK; /* OSC 24Mhz */
  341. }
  342. perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
  343. return get_ipg_clk() / (perclk_podf + 1);
  344. }
  345. static u32 get_uart_clk(void)
  346. {
  347. u32 reg, uart_podf;
  348. u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
  349. reg = __raw_readl(&imx_ccm->cscdr1);
  350. if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
  351. is_mx6sll() || is_mx6ull()) {
  352. if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
  353. freq = MXC_HCLK;
  354. }
  355. reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
  356. uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
  357. return freq / (uart_podf + 1);
  358. }
  359. static u32 get_cspi_clk(void)
  360. {
  361. u32 reg, cspi_podf;
  362. reg = __raw_readl(&imx_ccm->cscdr2);
  363. cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
  364. MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
  365. if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
  366. is_mx6sll() || is_mx6ull()) {
  367. if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
  368. return MXC_HCLK / (cspi_podf + 1);
  369. }
  370. return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
  371. }
  372. static u32 get_axi_clk(void)
  373. {
  374. u32 root_freq, axi_podf;
  375. u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
  376. axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
  377. axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
  378. if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
  379. if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
  380. root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
  381. else
  382. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  383. } else
  384. root_freq = get_periph_clk();
  385. return root_freq / (axi_podf + 1);
  386. }
  387. static u32 get_emi_slow_clk(void)
  388. {
  389. u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
  390. cscmr1 = __raw_readl(&imx_ccm->cscmr1);
  391. emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
  392. emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
  393. emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
  394. emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
  395. switch (emi_clk_sel) {
  396. case 0:
  397. root_freq = get_axi_clk();
  398. break;
  399. case 1:
  400. root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  401. break;
  402. case 2:
  403. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  404. break;
  405. case 3:
  406. root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
  407. break;
  408. }
  409. return root_freq / (emi_slow_podf + 1);
  410. }
  411. static u32 get_mmdc_ch0_clk(void)
  412. {
  413. u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
  414. u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
  415. u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
  416. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
  417. is_mx6sll()) {
  418. podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
  419. MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
  420. if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
  421. per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
  422. MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
  423. if (is_mx6sl()) {
  424. if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
  425. freq = MXC_HCLK;
  426. else
  427. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  428. } else {
  429. if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
  430. freq = decode_pll(PLL_BUS, MXC_HCLK);
  431. else
  432. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  433. }
  434. } else {
  435. per2_clk2_podf = 0;
  436. switch ((cbcmr &
  437. MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
  438. MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
  439. case 0:
  440. freq = decode_pll(PLL_BUS, MXC_HCLK);
  441. break;
  442. case 1:
  443. freq = mxc_get_pll_pfd(PLL_BUS, 2);
  444. break;
  445. case 2:
  446. freq = mxc_get_pll_pfd(PLL_BUS, 0);
  447. break;
  448. case 3:
  449. if (is_mx6sl()) {
  450. freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
  451. break;
  452. }
  453. pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
  454. switch (pmu_misc2_audio_div) {
  455. case 0:
  456. case 2:
  457. pmu_misc2_audio_div = 1;
  458. break;
  459. case 1:
  460. pmu_misc2_audio_div = 2;
  461. break;
  462. case 3:
  463. pmu_misc2_audio_div = 4;
  464. break;
  465. }
  466. freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
  467. pmu_misc2_audio_div;
  468. break;
  469. }
  470. }
  471. return freq / (podf + 1) / (per2_clk2_podf + 1);
  472. } else {
  473. podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
  474. MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
  475. return get_periph_clk() / (podf + 1);
  476. }
  477. }
  478. #if defined(CONFIG_VIDEO_MXS)
  479. static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
  480. u32 post_div)
  481. {
  482. u32 reg = 0;
  483. ulong start;
  484. debug("pll5 div = %d, num = %d, denom = %d\n",
  485. pll_div, pll_num, pll_denom);
  486. /* Power up PLL5 video */
  487. writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
  488. BM_ANADIG_PLL_VIDEO_BYPASS |
  489. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  490. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  491. &imx_ccm->analog_pll_video_clr);
  492. /* Set div, num and denom */
  493. switch (post_div) {
  494. case 1:
  495. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  496. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
  497. &imx_ccm->analog_pll_video_set);
  498. break;
  499. case 2:
  500. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  501. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
  502. &imx_ccm->analog_pll_video_set);
  503. break;
  504. case 4:
  505. writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  506. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
  507. &imx_ccm->analog_pll_video_set);
  508. break;
  509. default:
  510. puts("Wrong test_div!\n");
  511. return -EINVAL;
  512. }
  513. writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
  514. &imx_ccm->analog_pll_video_num);
  515. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
  516. &imx_ccm->analog_pll_video_denom);
  517. /* Wait PLL5 lock */
  518. start = get_timer(0); /* Get current timestamp */
  519. do {
  520. reg = readl(&imx_ccm->analog_pll_video);
  521. if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
  522. /* Enable PLL out */
  523. writel(BM_ANADIG_PLL_VIDEO_ENABLE,
  524. &imx_ccm->analog_pll_video_set);
  525. return 0;
  526. }
  527. } while (get_timer(0) < (start + 10)); /* Wait 10ms */
  528. puts("Lock PLL5 timeout\n");
  529. return -ETIME;
  530. }
  531. /*
  532. * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
  533. *
  534. * 'freq' using KHz as unit, see driver/video/mxsfb.c.
  535. */
  536. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  537. {
  538. u32 reg = 0;
  539. u32 hck = MXC_HCLK / 1000;
  540. /* DIV_SELECT ranges from 27 to 54 */
  541. u32 min = hck * 27;
  542. u32 max = hck * 54;
  543. u32 temp, best = 0;
  544. u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
  545. u32 pll_div, pll_num, pll_denom, post_div = 1;
  546. debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
  547. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
  548. !is_mx6sll()) {
  549. debug("This chip not support lcd!\n");
  550. return;
  551. }
  552. if (!is_mx6sl()) {
  553. if (base_addr == LCDIF1_BASE_ADDR) {
  554. reg = readl(&imx_ccm->cscdr2);
  555. /* Can't change clocks when clock not from pre-mux */
  556. if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
  557. return;
  558. }
  559. }
  560. if (is_mx6sx()) {
  561. reg = readl(&imx_ccm->cscdr2);
  562. /* Can't change clocks when clock not from pre-mux */
  563. if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
  564. return;
  565. }
  566. temp = freq * max_pred * max_postd;
  567. if (temp < min) {
  568. /*
  569. * Register: PLL_VIDEO
  570. * Bit Field: POST_DIV_SELECT
  571. * 00 — Divide by 4.
  572. * 01 — Divide by 2.
  573. * 10 — Divide by 1.
  574. * 11 — Reserved
  575. * No need to check post_div(1)
  576. */
  577. for (post_div = 2; post_div <= 4; post_div <<= 1) {
  578. if ((temp * post_div) > min) {
  579. freq *= post_div;
  580. break;
  581. }
  582. }
  583. if (post_div > 4) {
  584. printf("Fail to set rate to %dkhz", freq);
  585. return;
  586. }
  587. }
  588. /* Choose the best pred and postd to match freq for lcd */
  589. for (i = 1; i <= max_pred; i++) {
  590. for (j = 1; j <= max_postd; j++) {
  591. temp = freq * i * j;
  592. if (temp > max || temp < min)
  593. continue;
  594. if (best == 0 || temp < best) {
  595. best = temp;
  596. pred = i;
  597. postd = j;
  598. }
  599. }
  600. }
  601. if (best == 0) {
  602. printf("Fail to set rate to %dKHz", freq);
  603. return;
  604. }
  605. debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
  606. pll_div = best / hck;
  607. pll_denom = 1000000;
  608. pll_num = (best - hck * pll_div) * pll_denom / hck;
  609. /*
  610. * pll_num
  611. * (24MHz * (pll_div + --------- ))
  612. * pll_denom
  613. *freq KHz = --------------------------------
  614. * post_div * pred * postd * 1000
  615. */
  616. if (base_addr == LCDIF1_BASE_ADDR) {
  617. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  618. return;
  619. enable_lcdif_clock(base_addr, 0);
  620. if (!is_mx6sl()) {
  621. /* Select pre-lcd clock to PLL5 and set pre divider */
  622. clrsetbits_le32(&imx_ccm->cscdr2,
  623. MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
  624. MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
  625. (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
  626. ((pred - 1) <<
  627. MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
  628. /* Set the post divider */
  629. clrsetbits_le32(&imx_ccm->cbcmr,
  630. MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
  631. ((postd - 1) <<
  632. MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
  633. } else {
  634. /* Select pre-lcd clock to PLL5 and set pre divider */
  635. clrsetbits_le32(&imx_ccm->cscdr2,
  636. MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
  637. MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
  638. (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
  639. ((pred - 1) <<
  640. MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
  641. /* Set the post divider */
  642. clrsetbits_le32(&imx_ccm->cscmr1,
  643. MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
  644. (((postd - 1)^0x6) <<
  645. MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
  646. }
  647. enable_lcdif_clock(base_addr, 1);
  648. } else if (is_mx6sx()) {
  649. /* Setting LCDIF2 for i.MX6SX */
  650. if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  651. return;
  652. enable_lcdif_clock(base_addr, 0);
  653. /* Select pre-lcd clock to PLL5 and set pre divider */
  654. clrsetbits_le32(&imx_ccm->cscdr2,
  655. MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
  656. MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
  657. (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
  658. ((pred - 1) <<
  659. MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
  660. /* Set the post divider */
  661. clrsetbits_le32(&imx_ccm->cscmr1,
  662. MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
  663. ((postd - 1) <<
  664. MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
  665. enable_lcdif_clock(base_addr, 1);
  666. }
  667. }
  668. int enable_lcdif_clock(u32 base_addr, bool enable)
  669. {
  670. u32 reg = 0;
  671. u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
  672. if (is_mx6sx()) {
  673. if ((base_addr != LCDIF1_BASE_ADDR) &&
  674. (base_addr != LCDIF2_BASE_ADDR)) {
  675. puts("Wrong LCD interface!\n");
  676. return -EINVAL;
  677. }
  678. /* Set to pre-mux clock at default */
  679. lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
  680. MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
  681. MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  682. lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
  683. (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
  684. MXC_CCM_CCGR3_DISP_AXI_MASK) :
  685. (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
  686. MXC_CCM_CCGR3_DISP_AXI_MASK);
  687. } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
  688. if (base_addr != LCDIF1_BASE_ADDR) {
  689. puts("Wrong LCD interface!\n");
  690. return -EINVAL;
  691. }
  692. /* Set to pre-mux clock at default */
  693. lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  694. lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
  695. } else if (is_mx6sl()) {
  696. if (base_addr != LCDIF1_BASE_ADDR) {
  697. puts("Wrong LCD interface!\n");
  698. return -EINVAL;
  699. }
  700. reg = readl(&imx_ccm->CCGR3);
  701. reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
  702. MXC_CCM_CCGR3_LCDIF_PIX_MASK);
  703. writel(reg, &imx_ccm->CCGR3);
  704. if (enable) {
  705. reg = readl(&imx_ccm->cscdr3);
  706. reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
  707. reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
  708. writel(reg, &imx_ccm->cscdr3);
  709. reg = readl(&imx_ccm->CCGR3);
  710. reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
  711. MXC_CCM_CCGR3_LCDIF_PIX_MASK;
  712. writel(reg, &imx_ccm->CCGR3);
  713. }
  714. return 0;
  715. } else {
  716. return 0;
  717. }
  718. /* Gate LCDIF clock first */
  719. reg = readl(&imx_ccm->CCGR3);
  720. reg &= ~lcdif_ccgr3_mask;
  721. writel(reg, &imx_ccm->CCGR3);
  722. reg = readl(&imx_ccm->CCGR2);
  723. reg &= ~MXC_CCM_CCGR2_LCD_MASK;
  724. writel(reg, &imx_ccm->CCGR2);
  725. if (enable) {
  726. /* Select pre-mux */
  727. reg = readl(&imx_ccm->cscdr2);
  728. reg &= ~lcdif_clk_sel_mask;
  729. writel(reg, &imx_ccm->cscdr2);
  730. /* Enable the LCDIF pix clock */
  731. reg = readl(&imx_ccm->CCGR3);
  732. reg |= lcdif_ccgr3_mask;
  733. writel(reg, &imx_ccm->CCGR3);
  734. reg = readl(&imx_ccm->CCGR2);
  735. reg |= MXC_CCM_CCGR2_LCD_MASK;
  736. writel(reg, &imx_ccm->CCGR2);
  737. }
  738. return 0;
  739. }
  740. #endif
  741. #ifdef CONFIG_FSL_QSPI
  742. /* qspi_num can be from 0 - 1 */
  743. void enable_qspi_clk(int qspi_num)
  744. {
  745. u32 reg = 0;
  746. /* Enable QuadSPI clock */
  747. switch (qspi_num) {
  748. case 0:
  749. /* disable the clock gate */
  750. clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
  751. /* set 50M : (50 = 396 / 2 / 4) */
  752. reg = readl(&imx_ccm->cscmr1);
  753. reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
  754. MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
  755. reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
  756. (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
  757. writel(reg, &imx_ccm->cscmr1);
  758. /* enable the clock gate */
  759. setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
  760. break;
  761. case 1:
  762. /*
  763. * disable the clock gate
  764. * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
  765. * disable both of them.
  766. */
  767. clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
  768. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  769. /* set 50M : (50 = 396 / 2 / 4) */
  770. reg = readl(&imx_ccm->cs2cdr);
  771. reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
  772. MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
  773. MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
  774. reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
  775. MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
  776. writel(reg, &imx_ccm->cs2cdr);
  777. /*enable the clock gate*/
  778. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
  779. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
  780. break;
  781. default:
  782. break;
  783. }
  784. }
  785. #endif
  786. #ifdef CONFIG_FEC_MXC
  787. int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
  788. {
  789. u32 reg = 0;
  790. s32 timeout = 100000;
  791. struct anatop_regs __iomem *anatop =
  792. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  793. if (freq < ENET_25MHZ || freq > ENET_125MHZ)
  794. return -EINVAL;
  795. reg = readl(&anatop->pll_enet);
  796. if (fec_id == 0) {
  797. reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
  798. reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
  799. } else if (fec_id == 1) {
  800. /* Only i.MX6SX/UL support ENET2 */
  801. if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
  802. return -EINVAL;
  803. reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
  804. reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
  805. } else {
  806. return -EINVAL;
  807. }
  808. if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
  809. (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
  810. reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
  811. writel(reg, &anatop->pll_enet);
  812. while (timeout--) {
  813. if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
  814. break;
  815. }
  816. if (timeout < 0)
  817. return -ETIMEDOUT;
  818. }
  819. /* Enable FEC clock */
  820. if (fec_id == 0)
  821. reg |= BM_ANADIG_PLL_ENET_ENABLE;
  822. else
  823. reg |= BM_ANADIG_PLL_ENET2_ENABLE;
  824. reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
  825. writel(reg, &anatop->pll_enet);
  826. #ifdef CONFIG_MX6SX
  827. /* Disable enet system clcok before switching clock parent */
  828. reg = readl(&imx_ccm->CCGR3);
  829. reg &= ~MXC_CCM_CCGR3_ENET_MASK;
  830. writel(reg, &imx_ccm->CCGR3);
  831. /*
  832. * Set enet ahb clock to 200MHz
  833. * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
  834. */
  835. reg = readl(&imx_ccm->chsccdr);
  836. reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
  837. | MXC_CCM_CHSCCDR_ENET_PODF_MASK
  838. | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
  839. /* PLL2 PFD2 */
  840. reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
  841. /* Div = 2*/
  842. reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
  843. reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
  844. writel(reg, &imx_ccm->chsccdr);
  845. /* Enable enet system clock */
  846. reg = readl(&imx_ccm->CCGR3);
  847. reg |= MXC_CCM_CCGR3_ENET_MASK;
  848. writel(reg, &imx_ccm->CCGR3);
  849. #endif
  850. return 0;
  851. }
  852. #endif
  853. static u32 get_usdhc_clk(u32 port)
  854. {
  855. u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
  856. u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
  857. u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
  858. if (is_mx6ul() || is_mx6ull()) {
  859. if (port > 1)
  860. return 0;
  861. }
  862. if (is_mx6sll()) {
  863. if (port > 2)
  864. return 0;
  865. }
  866. switch (port) {
  867. case 0:
  868. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
  869. MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
  870. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
  871. break;
  872. case 1:
  873. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
  874. MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
  875. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
  876. break;
  877. case 2:
  878. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
  879. MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
  880. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
  881. break;
  882. case 3:
  883. usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
  884. MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
  885. clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
  886. break;
  887. default:
  888. break;
  889. }
  890. if (clk_sel)
  891. root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
  892. else
  893. root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
  894. return root_freq / (usdhc_podf + 1);
  895. }
  896. u32 imx_get_uartclk(void)
  897. {
  898. return get_uart_clk();
  899. }
  900. u32 imx_get_fecclk(void)
  901. {
  902. return mxc_get_clock(MXC_IPG_CLK);
  903. }
  904. #if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
  905. static int enable_enet_pll(uint32_t en)
  906. {
  907. struct mxc_ccm_reg *const imx_ccm
  908. = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
  909. s32 timeout = 100000;
  910. u32 reg = 0;
  911. /* Enable PLLs */
  912. reg = readl(&imx_ccm->analog_pll_enet);
  913. reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
  914. writel(reg, &imx_ccm->analog_pll_enet);
  915. reg |= BM_ANADIG_PLL_SYS_ENABLE;
  916. while (timeout--) {
  917. if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
  918. break;
  919. }
  920. if (timeout <= 0)
  921. return -EIO;
  922. reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
  923. writel(reg, &imx_ccm->analog_pll_enet);
  924. reg |= en;
  925. writel(reg, &imx_ccm->analog_pll_enet);
  926. return 0;
  927. }
  928. #endif
  929. #ifdef CONFIG_SATA
  930. static void ungate_sata_clock(void)
  931. {
  932. struct mxc_ccm_reg *const imx_ccm =
  933. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  934. /* Enable SATA clock. */
  935. setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  936. }
  937. int enable_sata_clock(void)
  938. {
  939. ungate_sata_clock();
  940. return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
  941. }
  942. void disable_sata_clock(void)
  943. {
  944. struct mxc_ccm_reg *const imx_ccm =
  945. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  946. clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
  947. }
  948. #endif
  949. #ifdef CONFIG_PCIE_IMX
  950. static void ungate_pcie_clock(void)
  951. {
  952. struct mxc_ccm_reg *const imx_ccm =
  953. (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  954. /* Enable PCIe clock. */
  955. setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
  956. }
  957. int enable_pcie_clock(void)
  958. {
  959. struct anatop_regs *anatop_regs =
  960. (struct anatop_regs *)ANATOP_BASE_ADDR;
  961. struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  962. u32 lvds1_clk_sel;
  963. /*
  964. * Here be dragons!
  965. *
  966. * The register ANATOP_MISC1 is not documented in the Freescale
  967. * MX6RM. The register that is mapped in the ANATOP space and
  968. * marked as ANATOP_MISC1 is actually documented in the PMU section
  969. * of the datasheet as PMU_MISC1.
  970. *
  971. * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
  972. * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
  973. * for PCI express link that is clocked from the i.MX6.
  974. */
  975. #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
  976. #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
  977. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
  978. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
  979. #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
  980. if (is_mx6sx())
  981. lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
  982. else
  983. lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
  984. clrsetbits_le32(&anatop_regs->ana_misc1,
  985. ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
  986. ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
  987. ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
  988. /* PCIe reference clock sourced from AXI. */
  989. clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
  990. /* Party time! Ungate the clock to the PCIe. */
  991. #ifdef CONFIG_SATA
  992. ungate_sata_clock();
  993. #endif
  994. ungate_pcie_clock();
  995. return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
  996. BM_ANADIG_PLL_ENET_ENABLE_PCIE);
  997. }
  998. #endif
  999. #ifdef CONFIG_IMX_HAB
  1000. void hab_caam_clock_enable(unsigned char enable)
  1001. {
  1002. u32 reg;
  1003. if (is_mx6ull() || is_mx6sll()) {
  1004. /* CG5, DCP clock */
  1005. reg = __raw_readl(&imx_ccm->CCGR0);
  1006. if (enable)
  1007. reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
  1008. else
  1009. reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
  1010. __raw_writel(reg, &imx_ccm->CCGR0);
  1011. } else {
  1012. /* CG4 ~ CG6, CAAM clocks */
  1013. reg = __raw_readl(&imx_ccm->CCGR0);
  1014. if (enable)
  1015. reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  1016. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  1017. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
  1018. else
  1019. reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  1020. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  1021. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
  1022. __raw_writel(reg, &imx_ccm->CCGR0);
  1023. }
  1024. /* EMI slow clk */
  1025. reg = __raw_readl(&imx_ccm->CCGR6);
  1026. if (enable)
  1027. reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1028. else
  1029. reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1030. __raw_writel(reg, &imx_ccm->CCGR6);
  1031. }
  1032. #endif
  1033. static void enable_pll3(void)
  1034. {
  1035. struct anatop_regs __iomem *anatop =
  1036. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  1037. /* make sure pll3 is enabled */
  1038. if ((readl(&anatop->usb1_pll_480_ctrl) &
  1039. BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
  1040. /* enable pll's power */
  1041. writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
  1042. &anatop->usb1_pll_480_ctrl_set);
  1043. writel(0x80, &anatop->ana_misc2_clr);
  1044. /* wait for pll lock */
  1045. while ((readl(&anatop->usb1_pll_480_ctrl) &
  1046. BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
  1047. ;
  1048. /* disable bypass */
  1049. writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
  1050. &anatop->usb1_pll_480_ctrl_clr);
  1051. /* enable pll output */
  1052. writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
  1053. &anatop->usb1_pll_480_ctrl_set);
  1054. }
  1055. }
  1056. void enable_thermal_clk(void)
  1057. {
  1058. enable_pll3();
  1059. }
  1060. #ifdef CONFIG_MTD_NOR_FLASH
  1061. void enable_eim_clk(unsigned char enable)
  1062. {
  1063. u32 reg;
  1064. reg = __raw_readl(&imx_ccm->CCGR6);
  1065. if (enable)
  1066. reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1067. else
  1068. reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
  1069. __raw_writel(reg, &imx_ccm->CCGR6);
  1070. }
  1071. #endif
  1072. unsigned int mxc_get_clock(enum mxc_clock clk)
  1073. {
  1074. switch (clk) {
  1075. case MXC_ARM_CLK:
  1076. return get_mcu_main_clk();
  1077. case MXC_PER_CLK:
  1078. return get_periph_clk();
  1079. case MXC_AHB_CLK:
  1080. return get_ahb_clk();
  1081. case MXC_IPG_CLK:
  1082. return get_ipg_clk();
  1083. case MXC_IPG_PERCLK:
  1084. case MXC_I2C_CLK:
  1085. return get_ipg_per_clk();
  1086. case MXC_UART_CLK:
  1087. return get_uart_clk();
  1088. case MXC_CSPI_CLK:
  1089. return get_cspi_clk();
  1090. case MXC_AXI_CLK:
  1091. return get_axi_clk();
  1092. case MXC_EMI_SLOW_CLK:
  1093. return get_emi_slow_clk();
  1094. case MXC_DDR_CLK:
  1095. return get_mmdc_ch0_clk();
  1096. case MXC_ESDHC_CLK:
  1097. return get_usdhc_clk(0);
  1098. case MXC_ESDHC2_CLK:
  1099. return get_usdhc_clk(1);
  1100. case MXC_ESDHC3_CLK:
  1101. return get_usdhc_clk(2);
  1102. case MXC_ESDHC4_CLK:
  1103. return get_usdhc_clk(3);
  1104. case MXC_SATA_CLK:
  1105. return get_ahb_clk();
  1106. default:
  1107. printf("Unsupported MXC CLK: %d\n", clk);
  1108. break;
  1109. }
  1110. return 0;
  1111. }
  1112. #ifndef CONFIG_MX6SX
  1113. void enable_ipu_clock(void)
  1114. {
  1115. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1116. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
  1117. if (is_mx6dqp()) {
  1118. setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
  1119. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
  1120. }
  1121. }
  1122. void disable_ipu_clock(void)
  1123. {
  1124. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1125. clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK);
  1126. if (is_mx6dqp()) {
  1127. clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
  1128. clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
  1129. }
  1130. }
  1131. #endif
  1132. #ifndef CONFIG_SPL_BUILD
  1133. /*
  1134. * Dump some core clockes.
  1135. */
  1136. int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  1137. char *const argv[])
  1138. {
  1139. u32 freq;
  1140. freq = decode_pll(PLL_SYS, MXC_HCLK);
  1141. printf("PLL_SYS %8d MHz\n", freq / 1000000);
  1142. freq = decode_pll(PLL_BUS, MXC_HCLK);
  1143. printf("PLL_BUS %8d MHz\n", freq / 1000000);
  1144. freq = decode_pll(PLL_USBOTG, MXC_HCLK);
  1145. printf("PLL_OTG %8d MHz\n", freq / 1000000);
  1146. freq = decode_pll(PLL_ENET, MXC_HCLK);
  1147. printf("PLL_NET %8d MHz\n", freq / 1000000);
  1148. printf("\n");
  1149. printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
  1150. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  1151. printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
  1152. #ifdef CONFIG_MXC_SPI
  1153. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  1154. #endif
  1155. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  1156. printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
  1157. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  1158. printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
  1159. printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
  1160. printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
  1161. printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
  1162. printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
  1163. printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
  1164. return 0;
  1165. }
  1166. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
  1167. defined(CONFIG_MX6S)
  1168. static void disable_ldb_di_clock_sources(void)
  1169. {
  1170. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1171. int reg;
  1172. /* Make sure PFDs are disabled at boot. */
  1173. reg = readl(&mxc_ccm->analog_pfd_528);
  1174. /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
  1175. if (is_mx6sdl())
  1176. reg |= 0x80008080;
  1177. else
  1178. reg |= 0x80808080;
  1179. writel(reg, &mxc_ccm->analog_pfd_528);
  1180. /* Disable PLL3 PFDs */
  1181. reg = readl(&mxc_ccm->analog_pfd_480);
  1182. reg |= 0x80808080;
  1183. writel(reg, &mxc_ccm->analog_pfd_480);
  1184. /* Disable PLL5 */
  1185. reg = readl(&mxc_ccm->analog_pll_video);
  1186. reg &= ~(1 << 13);
  1187. writel(reg, &mxc_ccm->analog_pll_video);
  1188. }
  1189. static void enable_ldb_di_clock_sources(void)
  1190. {
  1191. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1192. int reg;
  1193. reg = readl(&mxc_ccm->analog_pfd_528);
  1194. if (is_mx6sdl())
  1195. reg &= ~(0x80008080);
  1196. else
  1197. reg &= ~(0x80808080);
  1198. writel(reg, &mxc_ccm->analog_pfd_528);
  1199. reg = readl(&mxc_ccm->analog_pfd_480);
  1200. reg &= ~(0x80808080);
  1201. writel(reg, &mxc_ccm->analog_pfd_480);
  1202. }
  1203. /*
  1204. * Try call this function as early in the boot process as possible since the
  1205. * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
  1206. */
  1207. void select_ldb_di_clock_source(enum ldb_di_clock clk)
  1208. {
  1209. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  1210. int reg;
  1211. /*
  1212. * Need to follow a strict procedure when changing the LDB
  1213. * clock, else we can introduce a glitch. Things to keep in
  1214. * mind:
  1215. * 1. The current and new parent clocks must be disabled.
  1216. * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
  1217. * no CG bit.
  1218. * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
  1219. * the top four options are in one mux and the PLL3 option along
  1220. * with another option is in the second mux. There is third mux
  1221. * used to decide between the first and second mux.
  1222. * The code below switches the parent to the bottom mux first
  1223. * and then manipulates the top mux. This ensures that no glitch
  1224. * will enter the divider.
  1225. *
  1226. * Need to disable MMDC_CH1 clock manually as there is no CG bit
  1227. * for this clock. The only way to disable this clock is to move
  1228. * it to pll3_sw_clk and then to disable pll3_sw_clk
  1229. * Make sure periph2_clk2_sel is set to pll3_sw_clk
  1230. */
  1231. /* Disable all ldb_di clock parents */
  1232. disable_ldb_di_clock_sources();
  1233. /* Set MMDC_CH1 mask bit */
  1234. reg = readl(&mxc_ccm->ccdr);
  1235. reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
  1236. writel(reg, &mxc_ccm->ccdr);
  1237. /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
  1238. reg = readl(&mxc_ccm->cbcmr);
  1239. reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
  1240. writel(reg, &mxc_ccm->cbcmr);
  1241. /*
  1242. * Set the periph2_clk_sel to the top mux so that
  1243. * mmdc_ch1 is from pll3_sw_clk.
  1244. */
  1245. reg = readl(&mxc_ccm->cbcdr);
  1246. reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
  1247. writel(reg, &mxc_ccm->cbcdr);
  1248. /* Wait for the clock switch */
  1249. while (readl(&mxc_ccm->cdhipr))
  1250. ;
  1251. /* Disable pll3_sw_clk by selecting bypass clock source */
  1252. reg = readl(&mxc_ccm->ccsr);
  1253. reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
  1254. writel(reg, &mxc_ccm->ccsr);
  1255. /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
  1256. reg = readl(&mxc_ccm->cs2cdr);
  1257. reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1258. | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1259. writel(reg, &mxc_ccm->cs2cdr);
  1260. /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
  1261. reg = readl(&mxc_ccm->cs2cdr);
  1262. reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
  1263. | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
  1264. reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1265. | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1266. writel(reg, &mxc_ccm->cs2cdr);
  1267. /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
  1268. reg = readl(&mxc_ccm->cs2cdr);
  1269. reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
  1270. | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
  1271. reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
  1272. | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  1273. writel(reg, &mxc_ccm->cs2cdr);
  1274. /* Unbypass pll3_sw_clk */
  1275. reg = readl(&mxc_ccm->ccsr);
  1276. reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
  1277. writel(reg, &mxc_ccm->ccsr);
  1278. /*
  1279. * Set the periph2_clk_sel back to the bottom mux so that
  1280. * mmdc_ch1 is from its original parent.
  1281. */
  1282. reg = readl(&mxc_ccm->cbcdr);
  1283. reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
  1284. writel(reg, &mxc_ccm->cbcdr);
  1285. /* Wait for the clock switch */
  1286. while (readl(&mxc_ccm->cdhipr))
  1287. ;
  1288. /* Clear MMDC_CH1 mask bit */
  1289. reg = readl(&mxc_ccm->ccdr);
  1290. reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
  1291. writel(reg, &mxc_ccm->ccdr);
  1292. enable_ldb_di_clock_sources();
  1293. }
  1294. #endif
  1295. /***************************************************/
  1296. U_BOOT_CMD(
  1297. clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
  1298. "display clocks",
  1299. ""
  1300. );
  1301. #endif