clock.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <div64.h>
  17. #include <asm/arch/sys_proto.h>
  18. enum pll_clocks {
  19. PLL1_CLOCK = 0,
  20. PLL2_CLOCK,
  21. PLL3_CLOCK,
  22. #ifdef CONFIG_MX53
  23. PLL4_CLOCK,
  24. #endif
  25. PLL_CLOCKS,
  26. };
  27. struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
  28. [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
  29. [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
  30. [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
  31. #ifdef CONFIG_MX53
  32. [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
  33. #endif
  34. };
  35. #define AHB_CLK_ROOT 133333333
  36. #define SZ_DEC_1M 1000000
  37. #define PLL_PD_MAX 16 /* Actual pd+1 */
  38. #define PLL_MFI_MAX 15
  39. #define PLL_MFI_MIN 5
  40. #define ARM_DIV_MAX 8
  41. #define IPG_DIV_MAX 4
  42. #define AHB_DIV_MAX 8
  43. #define EMI_DIV_MAX 8
  44. #define NFC_DIV_MAX 8
  45. #define MX5_CBCMR 0x00015154
  46. #define MX5_CBCDR 0x02888945
  47. struct fixed_pll_mfd {
  48. u32 ref_clk_hz;
  49. u32 mfd;
  50. };
  51. const struct fixed_pll_mfd fixed_mfd[] = {
  52. {MXC_HCLK, 24 * 16},
  53. };
  54. struct pll_param {
  55. u32 pd;
  56. u32 mfi;
  57. u32 mfn;
  58. u32 mfd;
  59. };
  60. #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
  61. #define PLL_FREQ_MIN(ref_clk) \
  62. ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
  63. #define MAX_DDR_CLK 420000000
  64. #define NFC_CLK_MAX 34000000
  65. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  66. void set_usboh3_clk(void)
  67. {
  68. clrsetbits_le32(&mxc_ccm->cscmr1,
  69. MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
  70. MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
  71. clrsetbits_le32(&mxc_ccm->cscdr1,
  72. MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
  73. MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
  74. MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
  75. MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
  76. }
  77. void enable_usboh3_clk(bool enable)
  78. {
  79. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  80. clrsetbits_le32(&mxc_ccm->CCGR2,
  81. MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
  82. MXC_CCM_CCGR2_USBOH3_60M(cg));
  83. }
  84. #ifdef CONFIG_SYS_I2C_MXC
  85. /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
  86. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  87. {
  88. u32 mask;
  89. #if defined(CONFIG_MX51)
  90. if (i2c_num > 1)
  91. #elif defined(CONFIG_MX53)
  92. if (i2c_num > 2)
  93. #endif
  94. return -EINVAL;
  95. mask = MXC_CCM_CCGR_CG_MASK <<
  96. (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
  97. if (enable)
  98. setbits_le32(&mxc_ccm->CCGR1, mask);
  99. else
  100. clrbits_le32(&mxc_ccm->CCGR1, mask);
  101. return 0;
  102. }
  103. #endif
  104. void set_usb_phy_clk(void)
  105. {
  106. clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
  107. }
  108. #if defined(CONFIG_MX51)
  109. void enable_usb_phy1_clk(bool enable)
  110. {
  111. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  112. clrsetbits_le32(&mxc_ccm->CCGR2,
  113. MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
  114. MXC_CCM_CCGR2_USB_PHY(cg));
  115. }
  116. void enable_usb_phy2_clk(bool enable)
  117. {
  118. /* i.MX51 has a single USB PHY clock, so do nothing here. */
  119. }
  120. #elif defined(CONFIG_MX53)
  121. void enable_usb_phy1_clk(bool enable)
  122. {
  123. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  124. clrsetbits_le32(&mxc_ccm->CCGR4,
  125. MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
  126. MXC_CCM_CCGR4_USB_PHY1(cg));
  127. }
  128. void enable_usb_phy2_clk(bool enable)
  129. {
  130. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  131. clrsetbits_le32(&mxc_ccm->CCGR4,
  132. MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
  133. MXC_CCM_CCGR4_USB_PHY2(cg));
  134. }
  135. #endif
  136. /*
  137. * Calculate the frequency of PLLn.
  138. */
  139. static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
  140. {
  141. uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
  142. uint64_t refclk, temp;
  143. int32_t mfn_abs;
  144. ctrl = readl(&pll->ctrl);
  145. if (ctrl & MXC_DPLLC_CTL_HFSM) {
  146. mfn = readl(&pll->hfs_mfn);
  147. mfd = readl(&pll->hfs_mfd);
  148. op = readl(&pll->hfs_op);
  149. } else {
  150. mfn = readl(&pll->mfn);
  151. mfd = readl(&pll->mfd);
  152. op = readl(&pll->op);
  153. }
  154. mfd &= MXC_DPLLC_MFD_MFD_MASK;
  155. mfn &= MXC_DPLLC_MFN_MFN_MASK;
  156. pdf = op & MXC_DPLLC_OP_PDF_MASK;
  157. mfi = MXC_DPLLC_OP_MFI_RD(op);
  158. /* 21.2.3 */
  159. if (mfi < 5)
  160. mfi = 5;
  161. /* Sign extend */
  162. if (mfn >= 0x04000000) {
  163. mfn |= 0xfc000000;
  164. mfn_abs = -mfn;
  165. } else
  166. mfn_abs = mfn;
  167. refclk = infreq * 2;
  168. if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
  169. refclk *= 2;
  170. do_div(refclk, pdf + 1);
  171. temp = refclk * mfn_abs;
  172. do_div(temp, mfd + 1);
  173. ret = refclk * mfi;
  174. if ((int)mfn < 0)
  175. ret -= temp;
  176. else
  177. ret += temp;
  178. return ret;
  179. }
  180. #ifdef CONFIG_MX51
  181. /*
  182. * This function returns the Frequency Pre-Multiplier clock.
  183. */
  184. static u32 get_fpm(void)
  185. {
  186. u32 mult;
  187. u32 ccr = readl(&mxc_ccm->ccr);
  188. if (ccr & MXC_CCM_CCR_FPM_MULT)
  189. mult = 1024;
  190. else
  191. mult = 512;
  192. return MXC_CLK32 * mult;
  193. }
  194. #endif
  195. /*
  196. * This function returns the low power audio clock.
  197. */
  198. static u32 get_lp_apm(void)
  199. {
  200. u32 ret_val = 0;
  201. u32 ccsr = readl(&mxc_ccm->ccsr);
  202. if (ccsr & MXC_CCM_CCSR_LP_APM)
  203. #if defined(CONFIG_MX51)
  204. ret_val = get_fpm();
  205. #elif defined(CONFIG_MX53)
  206. ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
  207. #endif
  208. else
  209. ret_val = MXC_HCLK;
  210. return ret_val;
  211. }
  212. /*
  213. * Get mcu main rate
  214. */
  215. u32 get_mcu_main_clk(void)
  216. {
  217. u32 reg, freq;
  218. reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
  219. freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  220. return freq / (reg + 1);
  221. }
  222. /*
  223. * Get the rate of peripheral's root clock.
  224. */
  225. u32 get_periph_clk(void)
  226. {
  227. u32 reg;
  228. reg = readl(&mxc_ccm->cbcdr);
  229. if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
  230. return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
  231. reg = readl(&mxc_ccm->cbcmr);
  232. switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
  233. case 0:
  234. return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  235. case 1:
  236. return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
  237. case 2:
  238. return get_lp_apm();
  239. default:
  240. return 0;
  241. }
  242. /* NOTREACHED */
  243. }
  244. /*
  245. * Get the rate of ipg clock.
  246. */
  247. static u32 get_ipg_clk(void)
  248. {
  249. uint32_t freq, reg, div;
  250. freq = get_ahb_clk();
  251. reg = readl(&mxc_ccm->cbcdr);
  252. div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
  253. return freq / div;
  254. }
  255. /*
  256. * Get the rate of ipg_per clock.
  257. */
  258. static u32 get_ipg_per_clk(void)
  259. {
  260. u32 freq, pred1, pred2, podf;
  261. if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
  262. return get_ipg_clk();
  263. if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
  264. freq = get_lp_apm();
  265. else
  266. freq = get_periph_clk();
  267. podf = readl(&mxc_ccm->cbcdr);
  268. pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
  269. pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
  270. podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
  271. return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
  272. }
  273. /* Get the output clock rate of a standard PLL MUX for peripherals. */
  274. static u32 get_standard_pll_sel_clk(u32 clk_sel)
  275. {
  276. u32 freq = 0;
  277. switch (clk_sel & 0x3) {
  278. case 0:
  279. freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  280. break;
  281. case 1:
  282. freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
  283. break;
  284. case 2:
  285. freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
  286. break;
  287. case 3:
  288. freq = get_lp_apm();
  289. break;
  290. }
  291. return freq;
  292. }
  293. /*
  294. * Get the rate of uart clk.
  295. */
  296. static u32 get_uart_clk(void)
  297. {
  298. unsigned int clk_sel, freq, reg, pred, podf;
  299. reg = readl(&mxc_ccm->cscmr1);
  300. clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
  301. freq = get_standard_pll_sel_clk(clk_sel);
  302. reg = readl(&mxc_ccm->cscdr1);
  303. pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
  304. podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
  305. freq /= (pred + 1) * (podf + 1);
  306. return freq;
  307. }
  308. /*
  309. * get cspi clock rate.
  310. */
  311. static u32 imx_get_cspiclk(void)
  312. {
  313. u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
  314. u32 cscmr1 = readl(&mxc_ccm->cscmr1);
  315. u32 cscdr2 = readl(&mxc_ccm->cscdr2);
  316. pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
  317. pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
  318. clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
  319. freq = get_standard_pll_sel_clk(clk_sel);
  320. ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
  321. return ret_val;
  322. }
  323. /*
  324. * get esdhc clock rate.
  325. */
  326. static u32 get_esdhc_clk(u32 port)
  327. {
  328. u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
  329. u32 cscmr1 = readl(&mxc_ccm->cscmr1);
  330. u32 cscdr1 = readl(&mxc_ccm->cscdr1);
  331. switch (port) {
  332. case 0:
  333. clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
  334. pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
  335. podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
  336. break;
  337. case 1:
  338. clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
  339. pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
  340. podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
  341. break;
  342. case 2:
  343. if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
  344. return get_esdhc_clk(1);
  345. else
  346. return get_esdhc_clk(0);
  347. case 3:
  348. if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
  349. return get_esdhc_clk(1);
  350. else
  351. return get_esdhc_clk(0);
  352. default:
  353. break;
  354. }
  355. freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
  356. return freq;
  357. }
  358. static u32 get_axi_a_clk(void)
  359. {
  360. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  361. u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
  362. return get_periph_clk() / (pdf + 1);
  363. }
  364. static u32 get_axi_b_clk(void)
  365. {
  366. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  367. u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
  368. return get_periph_clk() / (pdf + 1);
  369. }
  370. static u32 get_emi_slow_clk(void)
  371. {
  372. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  373. u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
  374. u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
  375. if (emi_clk_sel)
  376. return get_ahb_clk() / (pdf + 1);
  377. return get_periph_clk() / (pdf + 1);
  378. }
  379. static u32 get_ddr_clk(void)
  380. {
  381. u32 ret_val = 0;
  382. u32 cbcmr = readl(&mxc_ccm->cbcmr);
  383. u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
  384. #ifdef CONFIG_MX51
  385. u32 cbcdr = readl(&mxc_ccm->cbcdr);
  386. if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
  387. u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
  388. ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  389. ret_val /= ddr_clk_podf + 1;
  390. return ret_val;
  391. }
  392. #endif
  393. switch (ddr_clk_sel) {
  394. case 0:
  395. ret_val = get_axi_a_clk();
  396. break;
  397. case 1:
  398. ret_val = get_axi_b_clk();
  399. break;
  400. case 2:
  401. ret_val = get_emi_slow_clk();
  402. break;
  403. case 3:
  404. ret_val = get_ahb_clk();
  405. break;
  406. default:
  407. break;
  408. }
  409. return ret_val;
  410. }
  411. /*
  412. * The API of get mxc clocks.
  413. */
  414. unsigned int mxc_get_clock(enum mxc_clock clk)
  415. {
  416. switch (clk) {
  417. case MXC_ARM_CLK:
  418. return get_mcu_main_clk();
  419. case MXC_AHB_CLK:
  420. return get_ahb_clk();
  421. case MXC_IPG_CLK:
  422. return get_ipg_clk();
  423. case MXC_IPG_PERCLK:
  424. case MXC_I2C_CLK:
  425. return get_ipg_per_clk();
  426. case MXC_UART_CLK:
  427. return get_uart_clk();
  428. case MXC_CSPI_CLK:
  429. return imx_get_cspiclk();
  430. case MXC_ESDHC_CLK:
  431. return get_esdhc_clk(0);
  432. case MXC_ESDHC2_CLK:
  433. return get_esdhc_clk(1);
  434. case MXC_ESDHC3_CLK:
  435. return get_esdhc_clk(2);
  436. case MXC_ESDHC4_CLK:
  437. return get_esdhc_clk(3);
  438. case MXC_FEC_CLK:
  439. return get_ipg_clk();
  440. case MXC_SATA_CLK:
  441. return get_ahb_clk();
  442. case MXC_DDR_CLK:
  443. return get_ddr_clk();
  444. default:
  445. break;
  446. }
  447. return -EINVAL;
  448. }
  449. u32 imx_get_uartclk(void)
  450. {
  451. return get_uart_clk();
  452. }
  453. u32 imx_get_fecclk(void)
  454. {
  455. return get_ipg_clk();
  456. }
  457. static int gcd(int m, int n)
  458. {
  459. int t;
  460. while (m > 0) {
  461. if (n > m) {
  462. t = m;
  463. m = n;
  464. n = t;
  465. } /* swap */
  466. m -= n;
  467. }
  468. return n;
  469. }
  470. /*
  471. * This is to calculate various parameters based on reference clock and
  472. * targeted clock based on the equation:
  473. * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
  474. * This calculation is based on a fixed MFD value for simplicity.
  475. */
  476. static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
  477. {
  478. u64 pd, mfi = 1, mfn, mfd, t1;
  479. u32 n_target = target;
  480. u32 n_ref = ref, i;
  481. /*
  482. * Make sure targeted freq is in the valid range.
  483. * Otherwise the following calculation might be wrong!!!
  484. */
  485. if (n_target < PLL_FREQ_MIN(ref) ||
  486. n_target > PLL_FREQ_MAX(ref)) {
  487. printf("Targeted peripheral clock should be"
  488. "within [%d - %d]\n",
  489. PLL_FREQ_MIN(ref) / SZ_DEC_1M,
  490. PLL_FREQ_MAX(ref) / SZ_DEC_1M);
  491. return -EINVAL;
  492. }
  493. for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
  494. if (fixed_mfd[i].ref_clk_hz == ref) {
  495. mfd = fixed_mfd[i].mfd;
  496. break;
  497. }
  498. }
  499. if (i == ARRAY_SIZE(fixed_mfd))
  500. return -EINVAL;
  501. /* Use n_target and n_ref to avoid overflow */
  502. for (pd = 1; pd <= PLL_PD_MAX; pd++) {
  503. t1 = n_target * pd;
  504. do_div(t1, (4 * n_ref));
  505. mfi = t1;
  506. if (mfi > PLL_MFI_MAX)
  507. return -EINVAL;
  508. else if (mfi < 5)
  509. continue;
  510. break;
  511. }
  512. /*
  513. * Now got pd and mfi already
  514. *
  515. * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
  516. */
  517. t1 = n_target * pd;
  518. do_div(t1, 4);
  519. t1 -= n_ref * mfi;
  520. t1 *= mfd;
  521. do_div(t1, n_ref);
  522. mfn = t1;
  523. debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
  524. ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
  525. i = 1;
  526. if (mfn != 0)
  527. i = gcd(mfd, mfn);
  528. pll->pd = (u32)pd;
  529. pll->mfi = (u32)mfi;
  530. do_div(mfn, i);
  531. pll->mfn = (u32)mfn;
  532. do_div(mfd, i);
  533. pll->mfd = (u32)mfd;
  534. return 0;
  535. }
  536. #define calc_div(tgt_clk, src_clk, limit) ({ \
  537. u32 v = 0; \
  538. if (((src_clk) % (tgt_clk)) <= 100) \
  539. v = (src_clk) / (tgt_clk); \
  540. else \
  541. v = ((src_clk) / (tgt_clk)) + 1;\
  542. if (v > limit) \
  543. v = limit; \
  544. (v - 1); \
  545. })
  546. #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
  547. { \
  548. writel(0x1232, &pll->ctrl); \
  549. writel(0x2, &pll->config); \
  550. writel((((pd) - 1) << 0) | ((fi) << 4), \
  551. &pll->op); \
  552. writel(fn, &(pll->mfn)); \
  553. writel((fd) - 1, &pll->mfd); \
  554. writel((((pd) - 1) << 0) | ((fi) << 4), \
  555. &pll->hfs_op); \
  556. writel(fn, &pll->hfs_mfn); \
  557. writel((fd) - 1, &pll->hfs_mfd); \
  558. writel(0x1232, &pll->ctrl); \
  559. while (!readl(&pll->ctrl) & 0x1) \
  560. ;\
  561. }
  562. static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
  563. {
  564. u32 ccsr = readl(&mxc_ccm->ccsr);
  565. struct mxc_pll_reg *pll = mxc_plls[index];
  566. switch (index) {
  567. case PLL1_CLOCK:
  568. /* Switch ARM to PLL2 clock */
  569. writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
  570. &mxc_ccm->ccsr);
  571. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  572. pll_param->mfi, pll_param->mfn,
  573. pll_param->mfd);
  574. /* Switch back */
  575. writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
  576. &mxc_ccm->ccsr);
  577. break;
  578. case PLL2_CLOCK:
  579. /* Switch to pll2 bypass clock */
  580. writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
  581. &mxc_ccm->ccsr);
  582. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  583. pll_param->mfi, pll_param->mfn,
  584. pll_param->mfd);
  585. /* Switch back */
  586. writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
  587. &mxc_ccm->ccsr);
  588. break;
  589. case PLL3_CLOCK:
  590. /* Switch to pll3 bypass clock */
  591. writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
  592. &mxc_ccm->ccsr);
  593. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  594. pll_param->mfi, pll_param->mfn,
  595. pll_param->mfd);
  596. /* Switch back */
  597. writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
  598. &mxc_ccm->ccsr);
  599. break;
  600. #ifdef CONFIG_MX53
  601. case PLL4_CLOCK:
  602. /* Switch to pll4 bypass clock */
  603. writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
  604. &mxc_ccm->ccsr);
  605. CHANGE_PLL_SETTINGS(pll, pll_param->pd,
  606. pll_param->mfi, pll_param->mfn,
  607. pll_param->mfd);
  608. /* Switch back */
  609. writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
  610. &mxc_ccm->ccsr);
  611. break;
  612. #endif
  613. default:
  614. return -EINVAL;
  615. }
  616. return 0;
  617. }
  618. /* Config CPU clock */
  619. static int config_core_clk(u32 ref, u32 freq)
  620. {
  621. int ret = 0;
  622. struct pll_param pll_param;
  623. memset(&pll_param, 0, sizeof(struct pll_param));
  624. /* The case that periph uses PLL1 is not considered here */
  625. ret = calc_pll_params(ref, freq, &pll_param);
  626. if (ret != 0) {
  627. printf("Error:Can't find pll parameters: %d\n", ret);
  628. return ret;
  629. }
  630. return config_pll_clk(PLL1_CLOCK, &pll_param);
  631. }
  632. static int config_nfc_clk(u32 nfc_clk)
  633. {
  634. u32 parent_rate = get_emi_slow_clk();
  635. u32 div;
  636. if (nfc_clk == 0)
  637. return -EINVAL;
  638. div = parent_rate / nfc_clk;
  639. if (div == 0)
  640. div++;
  641. if (parent_rate / div > NFC_CLK_MAX)
  642. div++;
  643. clrsetbits_le32(&mxc_ccm->cbcdr,
  644. MXC_CCM_CBCDR_NFC_PODF_MASK,
  645. MXC_CCM_CBCDR_NFC_PODF(div - 1));
  646. while (readl(&mxc_ccm->cdhipr) != 0)
  647. ;
  648. return 0;
  649. }
  650. void enable_nfc_clk(unsigned char enable)
  651. {
  652. unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
  653. clrsetbits_le32(&mxc_ccm->CCGR5,
  654. MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
  655. MXC_CCM_CCGR5_EMI_ENFC(cg));
  656. }
  657. #ifdef CONFIG_FSL_IIM
  658. void enable_efuse_prog_supply(bool enable)
  659. {
  660. if (enable)
  661. setbits_le32(&mxc_ccm->cgpr,
  662. MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
  663. else
  664. clrbits_le32(&mxc_ccm->cgpr,
  665. MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
  666. }
  667. #endif
  668. /* Config main_bus_clock for periphs */
  669. static int config_periph_clk(u32 ref, u32 freq)
  670. {
  671. int ret = 0;
  672. struct pll_param pll_param;
  673. memset(&pll_param, 0, sizeof(struct pll_param));
  674. if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
  675. ret = calc_pll_params(ref, freq, &pll_param);
  676. if (ret != 0) {
  677. printf("Error:Can't find pll parameters: %d\n",
  678. ret);
  679. return ret;
  680. }
  681. switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
  682. readl(&mxc_ccm->cbcmr))) {
  683. case 0:
  684. return config_pll_clk(PLL1_CLOCK, &pll_param);
  685. break;
  686. case 1:
  687. return config_pll_clk(PLL3_CLOCK, &pll_param);
  688. break;
  689. default:
  690. return -EINVAL;
  691. }
  692. }
  693. return 0;
  694. }
  695. static int config_ddr_clk(u32 emi_clk)
  696. {
  697. u32 clk_src;
  698. s32 shift = 0, clk_sel, div = 1;
  699. u32 cbcmr = readl(&mxc_ccm->cbcmr);
  700. if (emi_clk > MAX_DDR_CLK) {
  701. printf("Warning:DDR clock should not exceed %d MHz\n",
  702. MAX_DDR_CLK / SZ_DEC_1M);
  703. emi_clk = MAX_DDR_CLK;
  704. }
  705. clk_src = get_periph_clk();
  706. /* Find DDR clock input */
  707. clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
  708. switch (clk_sel) {
  709. case 0:
  710. shift = 16;
  711. break;
  712. case 1:
  713. shift = 19;
  714. break;
  715. case 2:
  716. shift = 22;
  717. break;
  718. case 3:
  719. shift = 10;
  720. break;
  721. default:
  722. return -EINVAL;
  723. }
  724. if ((clk_src % emi_clk) < 10000000)
  725. div = clk_src / emi_clk;
  726. else
  727. div = (clk_src / emi_clk) + 1;
  728. if (div > 8)
  729. div = 8;
  730. clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
  731. while (readl(&mxc_ccm->cdhipr) != 0)
  732. ;
  733. writel(0x0, &mxc_ccm->ccdr);
  734. return 0;
  735. }
  736. #ifdef CONFIG_MX53
  737. static int config_ldb_clk(u32 ref, u32 freq)
  738. {
  739. int ret = 0;
  740. struct pll_param pll_param;
  741. memset(&pll_param, 0, sizeof(struct pll_param));
  742. ret = calc_pll_params(ref, freq, &pll_param);
  743. if (ret != 0) {
  744. printf("Error:Can't find pll parameters: %d\n",
  745. ret);
  746. return ret;
  747. }
  748. return config_pll_clk(PLL4_CLOCK, &pll_param);
  749. }
  750. #else
  751. static int config_ldb_clk(u32 ref, u32 freq)
  752. {
  753. /* Platform not supported */
  754. return -EINVAL;
  755. }
  756. #endif
  757. /*
  758. * This function assumes the expected core clock has to be changed by
  759. * modifying the PLL. This is NOT true always but for most of the times,
  760. * it is. So it assumes the PLL output freq is the same as the expected
  761. * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
  762. * In the latter case, it will try to increase the presc value until
  763. * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
  764. * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
  765. * on the targeted PLL and reference input clock to the PLL. Lastly,
  766. * it sets the register based on these values along with the dividers.
  767. * Note 1) There is no value checking for the passed-in divider values
  768. * so the caller has to make sure those values are sensible.
  769. * 2) Also adjust the NFC divider such that the NFC clock doesn't
  770. * exceed NFC_CLK_MAX.
  771. * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
  772. * 177MHz for higher voltage, this function fixes the max to 133MHz.
  773. * 4) This function should not have allowed diag_printf() calls since
  774. * the serial driver has been stoped. But leave then here to allow
  775. * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
  776. */
  777. int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
  778. {
  779. freq *= SZ_DEC_1M;
  780. switch (clk) {
  781. case MXC_ARM_CLK:
  782. if (config_core_clk(ref, freq))
  783. return -EINVAL;
  784. break;
  785. case MXC_PERIPH_CLK:
  786. if (config_periph_clk(ref, freq))
  787. return -EINVAL;
  788. break;
  789. case MXC_DDR_CLK:
  790. if (config_ddr_clk(freq))
  791. return -EINVAL;
  792. break;
  793. case MXC_NFC_CLK:
  794. if (config_nfc_clk(freq))
  795. return -EINVAL;
  796. break;
  797. case MXC_LDB_CLK:
  798. if (config_ldb_clk(ref, freq))
  799. return -EINVAL;
  800. break;
  801. default:
  802. printf("Warning:Unsupported or invalid clock type\n");
  803. }
  804. return 0;
  805. }
  806. #ifdef CONFIG_MX53
  807. /*
  808. * The clock for the external interface can be set to use internal clock
  809. * if fuse bank 4, row 3, bit 2 is set.
  810. * This is an undocumented feature and it was confirmed by Freescale's support:
  811. * Fuses (but not pins) may be used to configure SATA clocks.
  812. * Particularly the i.MX53 Fuse_Map contains the next information
  813. * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
  814. * '00' - 100MHz (External)
  815. * '01' - 50MHz (External)
  816. * '10' - 120MHz, internal (USB PHY)
  817. * '11' - Reserved
  818. */
  819. void mxc_set_sata_internal_clock(void)
  820. {
  821. u32 *tmp_base =
  822. (u32 *)(IIM_BASE_ADDR + 0x180c);
  823. set_usb_phy_clk();
  824. clrsetbits_le32(tmp_base, 0x6, 0x4);
  825. }
  826. #endif
  827. #ifndef CONFIG_SPL_BUILD
  828. /*
  829. * Dump some core clockes.
  830. */
  831. static int do_mx5_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  832. char *const argv[])
  833. {
  834. u32 freq;
  835. freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
  836. printf("PLL1 %8d MHz\n", freq / 1000000);
  837. freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
  838. printf("PLL2 %8d MHz\n", freq / 1000000);
  839. freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
  840. printf("PLL3 %8d MHz\n", freq / 1000000);
  841. #ifdef CONFIG_MX53
  842. freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
  843. printf("PLL4 %8d MHz\n", freq / 1000000);
  844. #endif
  845. printf("\n");
  846. printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
  847. printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
  848. printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
  849. printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
  850. #ifdef CONFIG_MXC_SPI
  851. printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
  852. #endif
  853. return 0;
  854. }
  855. /***************************************************/
  856. U_BOOT_CMD(
  857. clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
  858. "display clocks",
  859. ""
  860. );
  861. #endif