imx_bootaux.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <asm/mach-imx/sys_proto.h>
  9. #include <command.h>
  10. #include <elf.h>
  11. #include <imx_sip.h>
  12. #include <linux/compiler.h>
  13. #include <cpu_func.h>
  14. int arch_auxiliary_core_up(u32 core_id, ulong addr)
  15. {
  16. ulong stack, pc;
  17. if (!addr)
  18. return -EINVAL;
  19. #ifdef CONFIG_IMX8M
  20. stack = *(u32 *)addr;
  21. pc = *(u32 *)(addr + 4);
  22. #else
  23. /*
  24. * handling ELF64 binaries
  25. * isn't supported yet.
  26. */
  27. if (valid_elf_image(addr)) {
  28. stack = 0x0;
  29. pc = load_elf_image_phdr(addr);
  30. if (!pc)
  31. return CMD_RET_FAILURE;
  32. } else {
  33. /*
  34. * Assume binary file with vector table at the beginning.
  35. * Cortex-M4 vector tables start with the stack pointer (SP)
  36. * and reset vector (initial PC).
  37. */
  38. stack = *(u32 *)addr;
  39. pc = *(u32 *)(addr + 4);
  40. }
  41. #endif
  42. printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
  43. stack, pc);
  44. /* Set the stack and pc to M4 bootROM */
  45. writel(stack, M4_BOOTROM_BASE_ADDR);
  46. writel(pc, M4_BOOTROM_BASE_ADDR + 4);
  47. flush_dcache_all();
  48. /* Enable M4 */
  49. #ifdef CONFIG_IMX8M
  50. call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);
  51. #else
  52. clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
  53. SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
  54. #endif
  55. return 0;
  56. }
  57. int arch_auxiliary_core_check_up(u32 core_id)
  58. {
  59. #ifdef CONFIG_IMX8M
  60. return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0);
  61. #else
  62. unsigned int val;
  63. val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
  64. if (val & SRC_M4C_NON_SCLR_RST_MASK)
  65. return 0; /* assert in reset */
  66. return 1;
  67. #endif
  68. }
  69. /*
  70. * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  71. * the reset vector at the head for the image, with SP and PC
  72. * as the first two words.
  73. *
  74. * Per the cortex-M reference manual, the reset vector of M4 needs
  75. * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
  76. * of that vector. So to boot M4, the A core must build the M4's reset
  77. * vector with getting the PC and SP from image and filling them to
  78. * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
  79. * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
  80. * accessing the M4 TCMUL.
  81. */
  82. static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
  83. char *const argv[])
  84. {
  85. ulong addr;
  86. int ret, up;
  87. if (argc < 2)
  88. return CMD_RET_USAGE;
  89. up = arch_auxiliary_core_check_up(0);
  90. if (up) {
  91. printf("## Auxiliary core is already up\n");
  92. return CMD_RET_SUCCESS;
  93. }
  94. addr = simple_strtoul(argv[1], NULL, 16);
  95. if (!addr)
  96. return CMD_RET_FAILURE;
  97. ret = arch_auxiliary_core_up(0, addr);
  98. if (ret)
  99. return CMD_RET_FAILURE;
  100. return CMD_RET_SUCCESS;
  101. }
  102. U_BOOT_CMD(
  103. bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
  104. "Start auxiliary core",
  105. ""
  106. );