soc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/mach-imx/hab.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/syscounter.h>
  18. #include <asm/armv8/mmu.h>
  19. #include <dm/uclass.h>
  20. #include <errno.h>
  21. #include <fdt_support.h>
  22. #include <fsl_wdog.h>
  23. #include <imx_sip.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #if defined(CONFIG_IMX_HAB)
  26. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  27. .bank = 1,
  28. .word = 3,
  29. };
  30. #endif
  31. int timer_init(void)
  32. {
  33. #ifdef CONFIG_SPL_BUILD
  34. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  35. unsigned long freq = readl(&sctr->cntfid0);
  36. /* Update with accurate clock frequency */
  37. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  38. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  39. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  40. #endif
  41. gd->arch.tbl = 0;
  42. gd->arch.tbu = 0;
  43. return 0;
  44. }
  45. void enable_tzc380(void)
  46. {
  47. struct iomuxc_gpr_base_regs *gpr =
  48. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  49. /* Enable TZASC and lock setting */
  50. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  51. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  52. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  53. setbits_le32(&gpr->gpr[10], BIT(1));
  54. /*
  55. * set Region 0 attribute to allow secure and non-secure
  56. * read/write permission. Found some masters like usb dwc3
  57. * controllers can't work with secure memory.
  58. */
  59. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  60. }
  61. void set_wdog_reset(struct wdog_regs *wdog)
  62. {
  63. /*
  64. * Output WDOG_B signal to reset external pmic or POR_B decided by
  65. * the board design. Without external reset, the peripherals/DDR/
  66. * PMIC are not reset, that may cause system working abnormal.
  67. * WDZST bit is write-once only bit. Align this bit in kernel,
  68. * otherwise kernel code will have no chance to set this bit.
  69. */
  70. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  71. }
  72. static struct mm_region imx8m_mem_map[] = {
  73. {
  74. /* ROM */
  75. .virt = 0x0UL,
  76. .phys = 0x0UL,
  77. .size = 0x100000UL,
  78. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  79. PTE_BLOCK_OUTER_SHARE
  80. }, {
  81. /* CAAM */
  82. .virt = 0x100000UL,
  83. .phys = 0x100000UL,
  84. .size = 0x8000UL,
  85. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  86. PTE_BLOCK_NON_SHARE |
  87. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  88. }, {
  89. /* TCM */
  90. .virt = 0x7C0000UL,
  91. .phys = 0x7C0000UL,
  92. .size = 0x80000UL,
  93. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  94. PTE_BLOCK_NON_SHARE |
  95. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  96. }, {
  97. /* OCRAM */
  98. .virt = 0x900000UL,
  99. .phys = 0x900000UL,
  100. .size = 0x200000UL,
  101. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  102. PTE_BLOCK_OUTER_SHARE
  103. }, {
  104. /* AIPS */
  105. .virt = 0xB00000UL,
  106. .phys = 0xB00000UL,
  107. .size = 0x3f500000UL,
  108. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  109. PTE_BLOCK_NON_SHARE |
  110. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  111. }, {
  112. /* DRAM1 */
  113. .virt = 0x40000000UL,
  114. .phys = 0x40000000UL,
  115. .size = PHYS_SDRAM_SIZE,
  116. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  117. PTE_BLOCK_OUTER_SHARE
  118. #ifdef PHYS_SDRAM_2_SIZE
  119. }, {
  120. /* DRAM2 */
  121. .virt = 0x100000000UL,
  122. .phys = 0x100000000UL,
  123. .size = PHYS_SDRAM_2_SIZE,
  124. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  125. PTE_BLOCK_OUTER_SHARE
  126. #endif
  127. }, {
  128. /* List terminator */
  129. 0,
  130. }
  131. };
  132. struct mm_region *mem_map = imx8m_mem_map;
  133. void enable_caches(void)
  134. {
  135. /*
  136. * If OPTEE runs, remove OPTEE memory from MMU table to
  137. * avoid speculative prefetch. OPTEE runs at the top of
  138. * the first memory bank
  139. */
  140. if (rom_pointer[1])
  141. imx8m_mem_map[5].size -= rom_pointer[1];
  142. icache_enable();
  143. dcache_enable();
  144. }
  145. static u32 get_cpu_variant_type(u32 type)
  146. {
  147. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  148. struct fuse_bank *bank = &ocotp->bank[1];
  149. struct fuse_bank1_regs *fuse =
  150. (struct fuse_bank1_regs *)bank->fuse_regs;
  151. u32 value = readl(&fuse->tester4);
  152. if (type == MXC_CPU_IMX8MQ) {
  153. if ((value & 0x3) == 0x2)
  154. return MXC_CPU_IMX8MD;
  155. else if (value & 0x200000)
  156. return MXC_CPU_IMX8MQL;
  157. } else if (type == MXC_CPU_IMX8MM) {
  158. switch (value & 0x3) {
  159. case 2:
  160. if (value & 0x1c0000)
  161. return MXC_CPU_IMX8MMDL;
  162. else
  163. return MXC_CPU_IMX8MMD;
  164. case 3:
  165. if (value & 0x1c0000)
  166. return MXC_CPU_IMX8MMSL;
  167. else
  168. return MXC_CPU_IMX8MMS;
  169. default:
  170. if (value & 0x1c0000)
  171. return MXC_CPU_IMX8MML;
  172. break;
  173. }
  174. } else if (type == MXC_CPU_IMX8MN) {
  175. switch (value & 0x3) {
  176. case 2:
  177. if (value & 0x1000000)
  178. return MXC_CPU_IMX8MNDL;
  179. else
  180. return MXC_CPU_IMX8MND;
  181. case 3:
  182. if (value & 0x1000000)
  183. return MXC_CPU_IMX8MNSL;
  184. else
  185. return MXC_CPU_IMX8MNS;
  186. default:
  187. if (value & 0x1000000)
  188. return MXC_CPU_IMX8MNL;
  189. break;
  190. }
  191. }
  192. return type;
  193. }
  194. u32 get_cpu_rev(void)
  195. {
  196. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  197. u32 reg = readl(&ana_pll->digprog);
  198. u32 type = (reg >> 16) & 0xff;
  199. u32 major_low = (reg >> 8) & 0xff;
  200. u32 rom_version;
  201. reg &= 0xff;
  202. /* iMX8MP */
  203. if (major_low == 0x43) {
  204. return (MXC_CPU_IMX8MP << 12) | reg;
  205. } else if (major_low == 0x42) {
  206. /* iMX8MN */
  207. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  208. } else if (major_low == 0x41) {
  209. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  210. } else {
  211. if (reg == CHIP_REV_1_0) {
  212. /*
  213. * For B0 chip, the DIGPROG is not updated,
  214. * it is still TO1.0. we have to check ROM
  215. * version or OCOTP_READ_FUSE_DATA.
  216. * 0xff0055aa is magic number for B1.
  217. */
  218. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  219. reg = CHIP_REV_2_1;
  220. } else {
  221. rom_version =
  222. readl((void __iomem *)ROM_VERSION_A0);
  223. if (rom_version != CHIP_REV_1_0) {
  224. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  225. rom_version &= 0xff;
  226. if (rom_version == CHIP_REV_2_0)
  227. reg = CHIP_REV_2_0;
  228. }
  229. }
  230. }
  231. type = get_cpu_variant_type(type);
  232. }
  233. return (type << 12) | reg;
  234. }
  235. static void imx_set_wdog_powerdown(bool enable)
  236. {
  237. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  238. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  239. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  240. /* Write to the PDE (Power Down Enable) bit */
  241. writew(enable, &wdog1->wmcr);
  242. writew(enable, &wdog2->wmcr);
  243. writew(enable, &wdog3->wmcr);
  244. }
  245. int arch_cpu_init_dm(void)
  246. {
  247. struct udevice *dev;
  248. int ret;
  249. if (CONFIG_IS_ENABLED(CLK)) {
  250. ret = uclass_get_device_by_name(UCLASS_CLK,
  251. "clock-controller@30380000",
  252. &dev);
  253. if (ret < 0) {
  254. printf("Failed to find clock node. Check device tree\n");
  255. return ret;
  256. }
  257. }
  258. return 0;
  259. }
  260. int arch_cpu_init(void)
  261. {
  262. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  263. /*
  264. * ROM might disable clock for SCTR,
  265. * enable the clock before timer_init.
  266. */
  267. if (IS_ENABLED(CONFIG_SPL_BUILD))
  268. clock_enable(CCGR_SCTR, 1);
  269. /*
  270. * Init timer at very early state, because sscg pll setting
  271. * will use it
  272. */
  273. timer_init();
  274. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  275. clock_init();
  276. imx_set_wdog_powerdown(false);
  277. }
  278. if (is_imx8mq()) {
  279. clock_enable(CCGR_OCOTP, 1);
  280. if (readl(&ocotp->ctrl) & 0x200)
  281. writel(0x200, &ocotp->ctrl_clr);
  282. }
  283. return 0;
  284. }
  285. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  286. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  287. enum boot_device get_boot_device(void)
  288. {
  289. volatile gd_t *pgd = gd;
  290. int ret;
  291. u32 boot;
  292. u16 boot_type;
  293. u8 boot_instance;
  294. enum boot_device boot_dev = SD1_BOOT;
  295. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  296. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  297. gd = pgd;
  298. if (ret != ROM_API_OKAY) {
  299. puts("ROMAPI: failure at query_boot_info\n");
  300. return -1;
  301. }
  302. boot_type = boot >> 16;
  303. boot_instance = (boot >> 8) & 0xff;
  304. switch (boot_type) {
  305. case BT_DEV_TYPE_SD:
  306. boot_dev = boot_instance + SD1_BOOT;
  307. break;
  308. case BT_DEV_TYPE_MMC:
  309. boot_dev = boot_instance + MMC1_BOOT;
  310. break;
  311. case BT_DEV_TYPE_NAND:
  312. boot_dev = NAND_BOOT;
  313. break;
  314. case BT_DEV_TYPE_FLEXSPINOR:
  315. boot_dev = QSPI_BOOT;
  316. break;
  317. case BT_DEV_TYPE_USB:
  318. boot_dev = USB_BOOT;
  319. break;
  320. default:
  321. break;
  322. }
  323. return boot_dev;
  324. }
  325. #endif
  326. bool is_usb_boot(void)
  327. {
  328. return get_boot_device() == USB_BOOT;
  329. }
  330. #ifdef CONFIG_OF_SYSTEM_SETUP
  331. int ft_system_setup(void *blob, bd_t *bd)
  332. {
  333. int i = 0;
  334. int rc;
  335. int nodeoff;
  336. /* Disable the CPU idle for A0 chip since the HW does not support it */
  337. if (is_soc_rev(CHIP_REV_1_0)) {
  338. static const char * const nodes_path[] = {
  339. "/cpus/cpu@0",
  340. "/cpus/cpu@1",
  341. "/cpus/cpu@2",
  342. "/cpus/cpu@3",
  343. };
  344. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  345. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  346. if (nodeoff < 0)
  347. continue; /* Not found, skip it */
  348. debug("Found %s node\n", nodes_path[i]);
  349. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  350. if (rc == -FDT_ERR_NOTFOUND)
  351. continue;
  352. if (rc) {
  353. printf("Unable to update property %s:%s, err=%s\n",
  354. nodes_path[i], "status", fdt_strerror(rc));
  355. return rc;
  356. }
  357. debug("Remove %s:%s\n", nodes_path[i],
  358. "cpu-idle-states");
  359. }
  360. }
  361. return 0;
  362. }
  363. #endif
  364. #if !CONFIG_IS_ENABLED(SYSRESET)
  365. void reset_cpu(ulong addr)
  366. {
  367. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  368. /* Clear WDA to trigger WDOG_B immediately */
  369. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  370. while (1) {
  371. /*
  372. * spin for .5 seconds before reset
  373. */
  374. }
  375. }
  376. #endif
  377. #if defined(CONFIG_ARCH_MISC_INIT)
  378. static void acquire_buildinfo(void)
  379. {
  380. u64 atf_commit = 0;
  381. /* Get ARM Trusted Firmware commit id */
  382. atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
  383. IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
  384. if (atf_commit == 0xffffffff) {
  385. debug("ATF does not support build info\n");
  386. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  387. }
  388. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  389. }
  390. int arch_misc_init(void)
  391. {
  392. acquire_buildinfo();
  393. return 0;
  394. }
  395. #endif
  396. void imx_tmu_arch_init(void *reg_base)
  397. {
  398. if (is_imx8mm() || is_imx8mn()) {
  399. /* Load TCALIV and TASR from fuses */
  400. struct ocotp_regs *ocotp =
  401. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  402. struct fuse_bank *bank = &ocotp->bank[3];
  403. struct fuse_bank3_regs *fuse =
  404. (struct fuse_bank3_regs *)bank->fuse_regs;
  405. u32 tca_rt, tca_hr, tca_en;
  406. u32 buf_vref, buf_slope;
  407. tca_rt = fuse->ana0 & 0xFF;
  408. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  409. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  410. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  411. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  412. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  413. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  414. (ulong)reg_base + 0x30);
  415. }
  416. #ifdef CONFIG_IMX8MP
  417. /* Load TCALIV0/1/m40 and TRIM from fuses */
  418. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  419. struct fuse_bank *bank = &ocotp->bank[38];
  420. struct fuse_bank38_regs *fuse =
  421. (struct fuse_bank38_regs *)bank->fuse_regs;
  422. struct fuse_bank *bank2 = &ocotp->bank[39];
  423. struct fuse_bank39_regs *fuse2 =
  424. (struct fuse_bank39_regs *)bank2->fuse_regs;
  425. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  426. u32 reg;
  427. u32 tca40[2], tca25[2], tca105[2];
  428. /* For blank sample */
  429. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  430. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  431. /* Use a default 25C binary codes */
  432. tca25[0] = 1596;
  433. tca25[1] = 1596;
  434. writel(tca25[0], (ulong)reg_base + 0x30);
  435. writel(tca25[1], (ulong)reg_base + 0x34);
  436. return;
  437. }
  438. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  439. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  440. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  441. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  442. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  443. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  444. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  445. writel(reg, (ulong)reg_base + 0x3c);
  446. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  447. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  448. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  449. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  450. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  451. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  452. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  453. /* use 25c for 1p calibration */
  454. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  455. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  456. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  457. #endif
  458. }