ddrmc-vf610-calibration.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ddrmc DDR3 calibration code for NXP's VF610
  4. *
  5. * Copyright (C) 2018 DENX Software Engineering
  6. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  7. *
  8. */
  9. /* #define DEBUG */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <linux/bitmap.h>
  15. #include "ddrmc-vf610-calibration.h"
  16. /*
  17. * Documents:
  18. *
  19. * [1] "Vybrid: About DDR leveling feature on DDRMC."
  20. * https://community.nxp.com/thread/395323
  21. *
  22. * [2] VFxxx Controller Reference Manual, Rev. 0, 10/2016
  23. *
  24. *
  25. * NOTE
  26. * ====
  27. *
  28. * NXP recommends setting 'fixed' parameters instead of performing the
  29. * training at each boot.
  30. *
  31. * Use those functions to determine those values on new HW, read the
  32. * calculated value from registers and add them to the board specific
  33. * struct ddrmc_cr_setting.
  34. *
  35. * SW leveling supported operations - CR93[SW_LVL_MODE]:
  36. *
  37. * - 0x0 (b'00) - No leveling
  38. *
  39. * - 0x1 (b'01) - WRLVL_DL_X - It is not recommended to perform this tuning
  40. * on HW designs utilizing non-flyback topology
  41. * (Single DDR3 with x16).
  42. * Instead the WRLVL_DL_0/1 fields shall be set
  43. * based on trace length differences from their
  44. * layout.
  45. * Mismatches up to 25% or tCK (clock period) are
  46. * allowed, so the value in the filed doesn’t have
  47. * to be very accurate.
  48. *
  49. * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
  50. * to the DQ signals so that the strobe edge is
  51. * centered in the window of valid read data.
  52. *
  53. * - 0x3 (b'11) - RDLVL_GTDL_0/1 - refers to the delay the PHY uses to un-gate
  54. * the Read DQS strobe pad from the time that the
  55. * PHY enables the pad to input the strobe signal.
  56. *
  57. */
  58. static int ddr_cal_get_first_edge_index(unsigned long *bmap, enum edge e,
  59. int samples, int start, int max)
  60. {
  61. int i, ret = -1;
  62. /*
  63. * We look only for the first value (and filter out
  64. * some wrong data)
  65. */
  66. switch (e) {
  67. case RISING_EDGE:
  68. for (i = start; i <= max - samples; i++) {
  69. if (test_bit(i, bmap)) {
  70. if (!test_bit(i - 1, bmap) &&
  71. test_bit(i + 1, bmap) &&
  72. test_bit(i + 2, bmap) &&
  73. test_bit(i + 3, bmap)) {
  74. return i;
  75. }
  76. }
  77. }
  78. break;
  79. case FALLING_EDGE:
  80. for (i = start; i <= max - samples; i++) {
  81. if (!test_bit(i, bmap)) {
  82. if (test_bit(i - 1, bmap) &&
  83. test_bit(i - 2, bmap) &&
  84. test_bit(i - 3, bmap)) {
  85. return i;
  86. }
  87. }
  88. }
  89. }
  90. return ret;
  91. }
  92. static void bitmap_print(unsigned long *bmap, int max)
  93. {
  94. int i;
  95. debug("BITMAP [0x%p]:\n", bmap);
  96. for (i = 0; i <= max; i++) {
  97. debug("%d ", test_bit(i, bmap) ? 1 : 0);
  98. if (i && (i % 32) == (32 - 1))
  99. debug("\n");
  100. }
  101. debug("\n");
  102. }
  103. #define sw_leveling_op_done \
  104. while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
  105. #define sw_leveling_load_value \
  106. do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
  107. DDRMC_CR93_SWLVL_LOAD); } while (0)
  108. #define sw_leveling_start \
  109. do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
  110. DDRMC_CR93_SWLVL_START); } while (0)
  111. #define sw_leveling_exit \
  112. do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
  113. DDRMC_CR94_SWLVL_EXIT); } while (0)
  114. /*
  115. * RDLVL_DL calibration:
  116. *
  117. * NXP is _NOT_ recommending performing the leveling at each
  118. * boot. Instead - one shall run this procedure on new boards
  119. * and then use hardcoded values.
  120. *
  121. */
  122. static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
  123. {
  124. DECLARE_BITMAP(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
  125. int rdlvl_dl_0_min = -1, rdlvl_dl_0_max = -1;
  126. int rdlvl_dl_1_min = -1, rdlvl_dl_1_max = -1;
  127. int rdlvl_dl_0, rdlvl_dl_1;
  128. u8 swlvl_rsp;
  129. u32 tmp;
  130. int i;
  131. /* Read defaults */
  132. u16 rdlvl_dl_0_def =
  133. (readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF;
  134. u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF;
  135. debug("\nRDLVL: ======================\n");
  136. debug("RDLVL: DQS to DQ (RDLVL)\n");
  137. debug("RDLVL: RDLVL_DL_0_DFL:\t 0x%x\n", rdlvl_dl_0_def);
  138. debug("RDLVL: RDLVL_DL_1_DFL:\t 0x%x\n", rdlvl_dl_1_def);
  139. /*
  140. * Set/Read setup for calibration
  141. *
  142. * Values necessary for leveling from Vybrid RM [2] - page 1600
  143. */
  144. writel(0x40703030, &ddrmr->cr[144]);
  145. writel(0x40, &ddrmr->cr[145]);
  146. writel(0x40, &ddrmr->cr[146]);
  147. tmp = readl(&ddrmr->cr[144]);
  148. debug("RDLVL: PHY_RDLVL_RES:\t 0x%x\n", (tmp >> 24) & 0xFF);// set 0x40
  149. debug("RDLVL: PHY_RDLV_LOAD:\t 0x%x\n", (tmp >> 16) & 0xFF);// set 0x70
  150. debug("RDLVL: PHY_RDLV_DLL:\t 0x%x\n", (tmp >> 8) & 0xFF); // set 0x30
  151. debug("RDLVL: PHY_RDLV_EN:\t 0x%x\n", tmp & 0xFF); //set 0x30
  152. tmp = readl(&ddrmr->cr[145]);
  153. debug("RDLVL: PHY_RDLV_RR:\t 0x%x\n", tmp & 0x3FF); //set 0x40
  154. tmp = readl(&ddrmr->cr[146]);
  155. debug("RDLVL: PHY_RDLV_RESP:\t 0x%x\n", tmp); //set 0x40
  156. /*
  157. * Program/read the leveling edge RDLVL_EDGE = 0
  158. *
  159. * 0x00 is the correct output on SWLVL_RSP_X
  160. * If by any chance 1s are visible -> wrong number read
  161. */
  162. clrbits_le32(&ddrmr->cr[101], DDRMC_CR101_PHY_RDLVL_EDGE);
  163. tmp = readl(&ddrmr->cr[101]);
  164. debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
  165. (tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
  166. /* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
  167. clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
  168. DDRMC_CR93_SW_LVL_MODE(0x2));
  169. tmp = readl(&ddrmr->cr[93]);
  170. debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
  171. (tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
  172. /* Start procedure - CR93[SWLVL_START] to ’b1 */
  173. sw_leveling_start;
  174. /* Poll CR94[SWLVL_OP_DONE] */
  175. sw_leveling_op_done;
  176. /*
  177. * Program delays for RDLVL_DL_0
  178. *
  179. * The procedure is to increase the delay values from 0 to 0xFF
  180. * and read the response from the DDRMC
  181. */
  182. debug("\nRDLVL: ---> RDLVL_DL_0\n");
  183. bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
  184. for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
  185. clrsetbits_le32(&ddrmr->cr[105],
  186. 0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
  187. i << DDRMC_CR105_RDLVL_DL_0_OFF);
  188. /* Load values CR93[SWLVL_LOAD] to ’b1 */
  189. sw_leveling_load_value;
  190. /* Poll CR94[SWLVL_OP_DONE] */
  191. sw_leveling_op_done;
  192. /*
  193. * Read Responses - SWLVL_RESP_0
  194. *
  195. * The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
  196. * -> 1 in the bit vector
  197. */
  198. swlvl_rsp = (readl(&ddrmr->cr[94]) >>
  199. DDRMC_CR94_SWLVL_RESP_0_OFF) & 0xF;
  200. if (swlvl_rsp == 0)
  201. generic_set_bit(i, rdlvl_rsp);
  202. }
  203. bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
  204. /*
  205. * First test for rising edge 0x0 -> 0x1 in bitmap
  206. */
  207. rdlvl_dl_0_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
  208. N_SAMPLES, N_SAMPLES,
  209. DDRMC_DQS_DQ_MAX_DELAY);
  210. /*
  211. * Secondly test for falling edge 0x1 -> 0x0 in bitmap
  212. */
  213. rdlvl_dl_0_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
  214. N_SAMPLES, rdlvl_dl_0_min,
  215. DDRMC_DQS_DQ_MAX_DELAY);
  216. debug("RDLVL: DL_0 min: %d [0x%x] DL_0 max: %d [0x%x]\n",
  217. rdlvl_dl_0_min, rdlvl_dl_0_min, rdlvl_dl_0_max, rdlvl_dl_0_max);
  218. rdlvl_dl_0 = (rdlvl_dl_0_max - rdlvl_dl_0_min) / 2;
  219. if (rdlvl_dl_0_max == -1 || rdlvl_dl_0_min == -1 || rdlvl_dl_0 <= 0) {
  220. debug("RDLVL: The DQS to DQ delay cannot be found!\n");
  221. debug("RDLVL: Using default - slice 0: %d!\n", rdlvl_dl_0_def);
  222. rdlvl_dl_0 = rdlvl_dl_0_def;
  223. }
  224. debug("\nRDLVL: ---> RDLVL_DL_1\n");
  225. bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
  226. for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
  227. clrsetbits_le32(&ddrmr->cr[110],
  228. 0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
  229. i << DDRMC_CR110_RDLVL_DL_1_OFF);
  230. /* Load values CR93[SWLVL_LOAD] to ’b1 */
  231. sw_leveling_load_value;
  232. /* Poll CR94[SWLVL_OP_DONE] */
  233. sw_leveling_op_done;
  234. /*
  235. * Read Responses - SWLVL_RESP_1
  236. *
  237. * The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
  238. * -> 1 in the bit vector
  239. */
  240. swlvl_rsp = (readl(&ddrmr->cr[95]) >>
  241. DDRMC_CR95_SWLVL_RESP_1_OFF) & 0xF;
  242. if (swlvl_rsp == 0)
  243. generic_set_bit(i, rdlvl_rsp);
  244. }
  245. bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
  246. /*
  247. * First test for rising edge 0x0 -> 0x1 in bitmap
  248. */
  249. rdlvl_dl_1_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
  250. N_SAMPLES, N_SAMPLES,
  251. DDRMC_DQS_DQ_MAX_DELAY);
  252. /*
  253. * Secondly test for falling edge 0x1 -> 0x0 in bitmap
  254. */
  255. rdlvl_dl_1_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
  256. N_SAMPLES, rdlvl_dl_1_min,
  257. DDRMC_DQS_DQ_MAX_DELAY);
  258. debug("RDLVL: DL_1 min: %d [0x%x] DL_1 max: %d [0x%x]\n",
  259. rdlvl_dl_1_min, rdlvl_dl_1_min, rdlvl_dl_1_max, rdlvl_dl_1_max);
  260. rdlvl_dl_1 = (rdlvl_dl_1_max - rdlvl_dl_1_min) / 2;
  261. if (rdlvl_dl_1_max == -1 || rdlvl_dl_1_min == -1 || rdlvl_dl_1 <= 0) {
  262. debug("RDLVL: The DQS to DQ delay cannot be found!\n");
  263. debug("RDLVL: Using default - slice 1: %d!\n", rdlvl_dl_1_def);
  264. rdlvl_dl_1 = rdlvl_dl_1_def;
  265. }
  266. debug("RDLVL: CALIBRATED: rdlvl_dl_0: 0x%x\t rdlvl_dl_1: 0x%x\n",
  267. rdlvl_dl_0, rdlvl_dl_1);
  268. /* Write new delay values */
  269. writel(DDRMC_CR105_RDLVL_DL_0(rdlvl_dl_0), &ddrmr->cr[105]);
  270. writel(DDRMC_CR110_RDLVL_DL_1(rdlvl_dl_1), &ddrmr->cr[110]);
  271. sw_leveling_load_value;
  272. sw_leveling_op_done;
  273. /* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
  274. sw_leveling_exit;
  275. /* Poll CR94[SWLVL_OP_DONE] */
  276. sw_leveling_op_done;
  277. return 0;
  278. }
  279. /*
  280. * WRLVL_DL calibration:
  281. *
  282. * For non-flyback memory architecture - where one have a single DDR3 x16
  283. * memory - it is NOT necessary to perform "Write Leveling"
  284. * [3] 'Vybrid DDR3 write leveling' https://community.nxp.com/thread/429362
  285. *
  286. */
  287. int ddrmc_calibration(struct ddrmr_regs *ddrmr)
  288. {
  289. ddrmc_cal_dqs_to_dq(ddrmr);
  290. return 0;
  291. }