spl_boot.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/cache.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/clk.h>
  12. #include <asm/arch/dmc.h>
  13. #include <asm/arch/periph.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <asm/arch/power.h>
  16. #include <asm/arch/spl.h>
  17. #include <asm/arch/spi.h>
  18. #include "common_setup.h"
  19. #include "clock_init.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /* Index into irom ptr table */
  22. enum index {
  23. MMC_INDEX,
  24. EMMC44_INDEX,
  25. EMMC44_END_INDEX,
  26. SPI_INDEX,
  27. USB_INDEX,
  28. };
  29. /* IROM Function Pointers Table */
  30. u32 irom_ptr_table[] = {
  31. [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
  32. [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
  33. [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
  34. -EMMC4.4 end boot operation */
  35. [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
  36. [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
  37. };
  38. void *get_irom_func(int index)
  39. {
  40. return (void *)*(u32 *)irom_ptr_table[index];
  41. }
  42. #ifdef CONFIG_USB_BOOTING
  43. /*
  44. * Set/clear program flow prediction and return the previous state.
  45. */
  46. static int config_branch_prediction(int set_cr_z)
  47. {
  48. unsigned int cr;
  49. /* System Control Register: 11th bit Z Branch prediction enable */
  50. cr = get_cr();
  51. set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
  52. return cr & CR_Z;
  53. }
  54. #endif
  55. #ifdef CONFIG_SPI_BOOTING
  56. static void spi_rx_tx(struct exynos_spi *regs, int todo,
  57. void *dinp, void const *doutp, int i)
  58. {
  59. uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
  60. int rx_lvl, tx_lvl;
  61. uint out_bytes, in_bytes;
  62. out_bytes = todo;
  63. in_bytes = todo;
  64. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  65. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  66. writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  67. while (in_bytes) {
  68. uint32_t spi_sts;
  69. int temp;
  70. spi_sts = readl(&regs->spi_sts);
  71. rx_lvl = ((spi_sts >> 15) & 0x7f);
  72. tx_lvl = ((spi_sts >> 6) & 0x7f);
  73. while (tx_lvl < 32 && out_bytes) {
  74. temp = 0xffffffff;
  75. writel(temp, &regs->tx_data);
  76. out_bytes -= 4;
  77. tx_lvl += 4;
  78. }
  79. while (rx_lvl >= 4 && in_bytes) {
  80. temp = readl(&regs->rx_data);
  81. if (rxp)
  82. *rxp++ = temp;
  83. in_bytes -= 4;
  84. rx_lvl -= 4;
  85. }
  86. }
  87. }
  88. /*
  89. * Copy uboot from spi flash to RAM
  90. *
  91. * @parma uboot_size size of u-boot to copy
  92. * @param uboot_addr address in u-boot to copy
  93. */
  94. static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
  95. {
  96. int upto, todo;
  97. int i, timeout = 100;
  98. struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
  99. set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
  100. /* set the spi1 GPIO */
  101. exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
  102. /* set pktcnt and enable it */
  103. writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  104. /* set FB_CLK_SEL */
  105. writel(SPI_FB_DELAY_180, &regs->fb_clk);
  106. /* set CH_WIDTH and BUS_WIDTH as word */
  107. setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  108. SPI_MODE_BUS_WIDTH_WORD);
  109. clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
  110. /* clear rx and tx channel if set priveously */
  111. clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  112. setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
  113. SPI_RX_BYTE_SWAP |
  114. SPI_RX_HWORD_SWAP);
  115. /* do a soft reset */
  116. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  117. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  118. /* now set rx and tx channel ON */
  119. setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
  120. clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
  121. /* Send read instruction (0x3h) followed by a 24 bit addr */
  122. writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
  123. /* waiting for TX done */
  124. while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
  125. if (!timeout) {
  126. debug("SPI TIMEOUT\n");
  127. break;
  128. }
  129. timeout--;
  130. }
  131. for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
  132. todo = min(uboot_size - upto, (unsigned int)(1 << 15));
  133. spi_rx_tx(regs, todo, (void *)(uboot_addr),
  134. (void *)(SPI_FLASH_UBOOT_POS), i);
  135. }
  136. setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
  137. /*
  138. * Let put controller mode to BYTE as
  139. * SPI driver does not support WORD mode yet
  140. */
  141. clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  142. SPI_MODE_BUS_WIDTH_WORD);
  143. writel(0, &regs->swap_cfg);
  144. /*
  145. * Flush spi tx, rx fifos and reset the SPI controller
  146. * and clear rx/tx channel
  147. */
  148. clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  149. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  150. clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  151. }
  152. #endif
  153. /*
  154. * Copy U-Boot from mmc to RAM:
  155. * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
  156. * Pointer to API (Data transfer from mmc to ram)
  157. */
  158. void copy_uboot_to_ram(void)
  159. {
  160. unsigned int bootmode = BOOT_MODE_OM;
  161. u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
  162. u32 offset = 0, size = 0;
  163. #ifdef CONFIG_SPI_BOOTING
  164. struct spl_machine_param *param = spl_get_machine_params();
  165. #endif
  166. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  167. u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
  168. void (*end_bootop_from_emmc)(void);
  169. #endif
  170. #ifdef CONFIG_USB_BOOTING
  171. int is_cr_z_set;
  172. unsigned int sec_boot_check;
  173. /*
  174. * Note that older hardware (before Exynos5800) does not expect any
  175. * arguments, but it does not hurt to pass them, so a common function
  176. * prototype is used.
  177. */
  178. u32 (*usb_copy)(u32 num_of_block, u32 *dst);
  179. /* Read iRAM location to check for secondary USB boot mode */
  180. sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
  181. if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
  182. bootmode = BOOT_MODE_USB;
  183. #endif
  184. if (bootmode == BOOT_MODE_OM)
  185. bootmode = get_boot_mode();
  186. switch (bootmode) {
  187. #ifdef CONFIG_SPI_BOOTING
  188. case BOOT_MODE_SERIAL:
  189. /* Customised function to copy u-boot from SF */
  190. exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
  191. break;
  192. #endif
  193. case BOOT_MODE_SD:
  194. offset = BL2_START_OFFSET;
  195. size = BL2_SIZE_BLOC_COUNT;
  196. copy_bl2 = get_irom_func(MMC_INDEX);
  197. break;
  198. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  199. case BOOT_MODE_EMMC:
  200. /* Set the FSYS1 clock divisor value for EMMC boot */
  201. emmc_boot_clk_div_set();
  202. copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
  203. end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
  204. copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
  205. end_bootop_from_emmc();
  206. break;
  207. #endif
  208. #ifdef CONFIG_USB_BOOTING
  209. case BOOT_MODE_USB:
  210. /*
  211. * iROM needs program flow prediction to be disabled
  212. * before copy from USB device to RAM
  213. */
  214. is_cr_z_set = config_branch_prediction(0);
  215. usb_copy = get_irom_func(USB_INDEX);
  216. usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
  217. config_branch_prediction(is_cr_z_set);
  218. break;
  219. #endif
  220. default:
  221. break;
  222. }
  223. if (copy_bl2)
  224. copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
  225. }
  226. void memzero(void *s, size_t n)
  227. {
  228. char *ptr = s;
  229. size_t i;
  230. for (i = 0; i < n; i++)
  231. *ptr++ = '\0';
  232. }
  233. /**
  234. * Set up the U-Boot global_data pointer
  235. *
  236. * This sets the address of the global data, and sets up basic values.
  237. *
  238. * @param gdp Value to give to gd
  239. */
  240. static void setup_global_data(gd_t *gdp)
  241. {
  242. gd = gdp;
  243. memzero((void *)gd, sizeof(gd_t));
  244. gd->flags |= GD_FLG_RELOC;
  245. gd->baudrate = CONFIG_BAUDRATE;
  246. gd->have_console = 1;
  247. }
  248. void board_init_f(unsigned long bootflag)
  249. {
  250. __aligned(8) gd_t local_gd;
  251. __attribute__((noreturn)) void (*uboot)(void);
  252. setup_global_data(&local_gd);
  253. if (do_lowlevel_init())
  254. power_exit_wakeup();
  255. copy_uboot_to_ram();
  256. /* Jump to U-Boot image */
  257. uboot = (void *)CONFIG_SYS_TEXT_BASE;
  258. (*uboot)();
  259. /* Never returns Here */
  260. }
  261. /* Place Holders */
  262. void board_init_r(gd_t *id, ulong dest_addr)
  263. {
  264. /* Function attribute is no-return */
  265. /* This Function never executes */
  266. while (1)
  267. ;
  268. }