power.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. * Donghwa Lee <dh09.lee@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/power.h>
  9. static void exynos4_mipi_phy_control(unsigned int dev_index,
  10. unsigned int enable)
  11. {
  12. struct exynos4_power *pmu =
  13. (struct exynos4_power *)samsung_get_base_power();
  14. unsigned int addr, cfg = 0;
  15. if (dev_index == 0)
  16. addr = (unsigned int)&pmu->mipi_phy0_control;
  17. else
  18. addr = (unsigned int)&pmu->mipi_phy1_control;
  19. cfg = readl(addr);
  20. if (enable)
  21. cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
  22. else
  23. cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
  24. writel(cfg, addr);
  25. }
  26. void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
  27. {
  28. if (cpu_is_exynos4())
  29. exynos4_mipi_phy_control(dev_index, enable);
  30. }
  31. void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
  32. {
  33. struct exynos5_power *power =
  34. (struct exynos5_power *)samsung_get_base_power();
  35. if (enable) {
  36. /* Enabling USBHOST_PHY */
  37. setbits_le32(&power->usbhost_phy_control,
  38. POWER_USB_HOST_PHY_CTRL_EN);
  39. } else {
  40. /* Disabling USBHOST_PHY */
  41. clrbits_le32(&power->usbhost_phy_control,
  42. POWER_USB_HOST_PHY_CTRL_EN);
  43. }
  44. }
  45. void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
  46. {
  47. struct exynos4412_power *power =
  48. (struct exynos4412_power *)samsung_get_base_power();
  49. if (enable) {
  50. /* Enabling USBHOST_PHY */
  51. setbits_le32(&power->usbhost_phy_control,
  52. POWER_USB_HOST_PHY_CTRL_EN);
  53. setbits_le32(&power->hsic1_phy_control,
  54. POWER_USB_HOST_PHY_CTRL_EN);
  55. setbits_le32(&power->hsic2_phy_control,
  56. POWER_USB_HOST_PHY_CTRL_EN);
  57. } else {
  58. /* Disabling USBHOST_PHY */
  59. clrbits_le32(&power->usbhost_phy_control,
  60. POWER_USB_HOST_PHY_CTRL_EN);
  61. clrbits_le32(&power->hsic1_phy_control,
  62. POWER_USB_HOST_PHY_CTRL_EN);
  63. clrbits_le32(&power->hsic2_phy_control,
  64. POWER_USB_HOST_PHY_CTRL_EN);
  65. }
  66. }
  67. void set_usbhost_phy_ctrl(unsigned int enable)
  68. {
  69. if (cpu_is_exynos5())
  70. exynos5_set_usbhost_phy_ctrl(enable);
  71. else if (cpu_is_exynos4())
  72. if (proid_is_exynos4412())
  73. exynos4412_set_usbhost_phy_ctrl(enable);
  74. }
  75. static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
  76. {
  77. struct exynos5_power *power =
  78. (struct exynos5_power *)samsung_get_base_power();
  79. if (enable) {
  80. /* Enabling USBDRD_PHY */
  81. setbits_le32(&power->usbdrd_phy_control,
  82. POWER_USB_DRD_PHY_CTRL_EN);
  83. } else {
  84. /* Disabling USBDRD_PHY */
  85. clrbits_le32(&power->usbdrd_phy_control,
  86. POWER_USB_DRD_PHY_CTRL_EN);
  87. }
  88. }
  89. static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
  90. {
  91. struct exynos5420_power *power =
  92. (struct exynos5420_power *)samsung_get_base_power();
  93. if (enable) {
  94. /* Enabling USBDEV_PHY */
  95. setbits_le32(&power->usbdev_phy_control,
  96. POWER_USB_DRD_PHY_CTRL_EN);
  97. setbits_le32(&power->usbdev1_phy_control,
  98. POWER_USB_DRD_PHY_CTRL_EN);
  99. } else {
  100. /* Disabling USBDEV_PHY */
  101. clrbits_le32(&power->usbdev_phy_control,
  102. POWER_USB_DRD_PHY_CTRL_EN);
  103. clrbits_le32(&power->usbdev1_phy_control,
  104. POWER_USB_DRD_PHY_CTRL_EN);
  105. }
  106. }
  107. void set_usbdrd_phy_ctrl(unsigned int enable)
  108. {
  109. if (cpu_is_exynos5()) {
  110. if (proid_is_exynos542x())
  111. exynos5420_set_usbdev_phy_ctrl(enable);
  112. else
  113. exynos5_set_usbdrd_phy_ctrl(enable);
  114. }
  115. }
  116. static void exynos5_dp_phy_control(unsigned int enable)
  117. {
  118. unsigned int cfg;
  119. struct exynos5_power *power =
  120. (struct exynos5_power *)samsung_get_base_power();
  121. cfg = readl(&power->dptx_phy_control);
  122. if (enable)
  123. cfg |= EXYNOS_DP_PHY_ENABLE;
  124. else
  125. cfg &= ~EXYNOS_DP_PHY_ENABLE;
  126. writel(cfg, &power->dptx_phy_control);
  127. }
  128. void exynos_dp_phy_ctrl(unsigned int enable)
  129. {
  130. if (cpu_is_exynos5())
  131. exynos5_dp_phy_control(enable);
  132. }
  133. static void exynos5_set_ps_hold_ctrl(void)
  134. {
  135. struct exynos5_power *power =
  136. (struct exynos5_power *)samsung_get_base_power();
  137. /* Set PS-Hold high */
  138. setbits_le32(&power->ps_hold_control,
  139. EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
  140. }
  141. /*
  142. * Set ps_hold data driving value high
  143. * This enables the machine to stay powered on
  144. * after the initial power-on condition goes away
  145. * (e.g. power button).
  146. */
  147. void set_ps_hold_ctrl(void)
  148. {
  149. if (cpu_is_exynos5())
  150. exynos5_set_ps_hold_ctrl();
  151. }
  152. static void exynos5_set_xclkout(void)
  153. {
  154. struct exynos5_power *power =
  155. (struct exynos5_power *)samsung_get_base_power();
  156. /* use xxti for xclk out */
  157. clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
  158. PMU_DEBUG_XXTI);
  159. }
  160. void set_xclkout(void)
  161. {
  162. if (cpu_is_exynos5())
  163. exynos5_set_xclkout();
  164. }
  165. /* Enables hardware tripping to power off the system when TMU fails */
  166. void set_hw_thermal_trip(void)
  167. {
  168. if (cpu_is_exynos5()) {
  169. struct exynos5_power *power =
  170. (struct exynos5_power *)samsung_get_base_power();
  171. /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
  172. setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
  173. }
  174. }
  175. static uint32_t exynos5_get_reset_status(void)
  176. {
  177. struct exynos5_power *power =
  178. (struct exynos5_power *)samsung_get_base_power();
  179. return power->inform1;
  180. }
  181. static uint32_t exynos4_get_reset_status(void)
  182. {
  183. struct exynos4_power *power =
  184. (struct exynos4_power *)samsung_get_base_power();
  185. return power->inform1;
  186. }
  187. uint32_t get_reset_status(void)
  188. {
  189. if (cpu_is_exynos5())
  190. return exynos5_get_reset_status();
  191. else
  192. return exynos4_get_reset_status();
  193. }
  194. static void exynos5_power_exit_wakeup(void)
  195. {
  196. struct exynos5_power *power =
  197. (struct exynos5_power *)samsung_get_base_power();
  198. typedef void (*resume_func)(void);
  199. ((resume_func)power->inform0)();
  200. }
  201. static void exynos4_power_exit_wakeup(void)
  202. {
  203. struct exynos4_power *power =
  204. (struct exynos4_power *)samsung_get_base_power();
  205. typedef void (*resume_func)(void);
  206. ((resume_func)power->inform0)();
  207. }
  208. void power_exit_wakeup(void)
  209. {
  210. if (cpu_is_exynos5())
  211. exynos5_power_exit_wakeup();
  212. else
  213. exynos4_power_exit_wakeup();
  214. }
  215. unsigned int get_boot_mode(void)
  216. {
  217. unsigned int om_pin = samsung_get_base_power();
  218. return readl(om_pin) & OM_PIN_MASK;
  219. }