pinmux.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 Samsung Electronics.
  4. * Abhilash Kesavan <a.kesavan@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <fdtdec.h>
  8. #include <log.h>
  9. #include <asm/gpio.h>
  10. #include <asm/arch/pinmux.h>
  11. #include <asm/arch/sromc.h>
  12. static void exynos5_uart_config(int peripheral)
  13. {
  14. int i, start, count;
  15. switch (peripheral) {
  16. case PERIPH_ID_UART0:
  17. start = EXYNOS5_GPIO_A00;
  18. count = 4;
  19. break;
  20. case PERIPH_ID_UART1:
  21. start = EXYNOS5_GPIO_D00;
  22. count = 4;
  23. break;
  24. case PERIPH_ID_UART2:
  25. start = EXYNOS5_GPIO_A10;
  26. count = 4;
  27. break;
  28. case PERIPH_ID_UART3:
  29. start = EXYNOS5_GPIO_A14;
  30. count = 2;
  31. break;
  32. default:
  33. debug("%s: invalid peripheral %d", __func__, peripheral);
  34. return;
  35. }
  36. for (i = start; i < start + count; i++) {
  37. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  38. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  39. }
  40. }
  41. static void exynos5420_uart_config(int peripheral)
  42. {
  43. int i, start, count;
  44. switch (peripheral) {
  45. case PERIPH_ID_UART0:
  46. start = EXYNOS5420_GPIO_A00;
  47. count = 4;
  48. break;
  49. case PERIPH_ID_UART1:
  50. start = EXYNOS5420_GPIO_A04;
  51. count = 4;
  52. break;
  53. case PERIPH_ID_UART2:
  54. start = EXYNOS5420_GPIO_A10;
  55. count = 4;
  56. break;
  57. case PERIPH_ID_UART3:
  58. start = EXYNOS5420_GPIO_A14;
  59. count = 2;
  60. break;
  61. default:
  62. debug("%s: invalid peripheral %d", __func__, peripheral);
  63. return;
  64. }
  65. for (i = start; i < start + count; i++) {
  66. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  67. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  68. }
  69. }
  70. static int exynos5_mmc_config(int peripheral, int flags)
  71. {
  72. int i, start, start_ext, gpio_func = 0;
  73. switch (peripheral) {
  74. case PERIPH_ID_SDMMC0:
  75. start = EXYNOS5_GPIO_C00;
  76. start_ext = EXYNOS5_GPIO_C10;
  77. gpio_func = S5P_GPIO_FUNC(0x2);
  78. break;
  79. case PERIPH_ID_SDMMC1:
  80. start = EXYNOS5_GPIO_C20;
  81. start_ext = 0;
  82. break;
  83. case PERIPH_ID_SDMMC2:
  84. start = EXYNOS5_GPIO_C30;
  85. start_ext = EXYNOS5_GPIO_C43;
  86. gpio_func = S5P_GPIO_FUNC(0x3);
  87. break;
  88. case PERIPH_ID_SDMMC3:
  89. start = EXYNOS5_GPIO_C40;
  90. start_ext = 0;
  91. break;
  92. default:
  93. debug("%s: invalid peripheral %d", __func__, peripheral);
  94. return -1;
  95. }
  96. if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
  97. debug("SDMMC device %d does not support 8bit mode",
  98. peripheral);
  99. return -1;
  100. }
  101. if (flags & PINMUX_FLAG_8BIT_MODE) {
  102. for (i = start_ext; i <= (start_ext + 3); i++) {
  103. gpio_cfg_pin(i, gpio_func);
  104. gpio_set_pull(i, S5P_GPIO_PULL_UP);
  105. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  106. }
  107. }
  108. for (i = start; i < (start + 2); i++) {
  109. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  110. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  111. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  112. }
  113. for (i = (start + 3); i <= (start + 6); i++) {
  114. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  115. gpio_set_pull(i, S5P_GPIO_PULL_UP);
  116. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  117. }
  118. return 0;
  119. }
  120. static int exynos5420_mmc_config(int peripheral, int flags)
  121. {
  122. int i, start = 0, start_ext = 0;
  123. switch (peripheral) {
  124. case PERIPH_ID_SDMMC0:
  125. start = EXYNOS5420_GPIO_C00;
  126. start_ext = EXYNOS5420_GPIO_C30;
  127. break;
  128. case PERIPH_ID_SDMMC1:
  129. start = EXYNOS5420_GPIO_C10;
  130. start_ext = EXYNOS5420_GPIO_D14;
  131. break;
  132. case PERIPH_ID_SDMMC2:
  133. start = EXYNOS5420_GPIO_C20;
  134. start_ext = 0;
  135. break;
  136. default:
  137. start = 0;
  138. debug("%s: invalid peripheral %d", __func__, peripheral);
  139. return -1;
  140. }
  141. if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
  142. debug("SDMMC device %d does not support 8bit mode",
  143. peripheral);
  144. return -1;
  145. }
  146. if (flags & PINMUX_FLAG_8BIT_MODE) {
  147. for (i = start_ext; i <= (start_ext + 3); i++) {
  148. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  149. gpio_set_pull(i, S5P_GPIO_PULL_UP);
  150. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  151. }
  152. }
  153. for (i = start; i < (start + 3); i++) {
  154. /*
  155. * MMC0 is intended to be used for eMMC. The
  156. * card detect pin is used as a VDDEN signal to
  157. * power on the eMMC. The 5420 iROM makes
  158. * this same assumption.
  159. */
  160. if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
  161. #ifndef CONFIG_SPL_BUILD
  162. gpio_request(i, "sdmmc0_vdden");
  163. #endif
  164. gpio_set_value(i, 1);
  165. gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
  166. } else {
  167. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  168. }
  169. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  170. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  171. }
  172. for (i = (start + 3); i <= (start + 6); i++) {
  173. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  174. gpio_set_pull(i, S5P_GPIO_PULL_UP);
  175. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  176. }
  177. return 0;
  178. }
  179. static void exynos5_sromc_config(int flags)
  180. {
  181. int i;
  182. /*
  183. * SROM:CS1 and EBI
  184. *
  185. * GPY0[0] SROM_CSn[0]
  186. * GPY0[1] SROM_CSn[1](2)
  187. * GPY0[2] SROM_CSn[2]
  188. * GPY0[3] SROM_CSn[3]
  189. * GPY0[4] EBI_OEn(2)
  190. * GPY0[5] EBI_EEn(2)
  191. *
  192. * GPY1[0] EBI_BEn[0](2)
  193. * GPY1[1] EBI_BEn[1](2)
  194. * GPY1[2] SROM_WAIT(2)
  195. * GPY1[3] EBI_DATA_RDn(2)
  196. */
  197. gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
  198. S5P_GPIO_FUNC(2));
  199. gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
  200. gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
  201. for (i = 0; i < 4; i++)
  202. gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
  203. /*
  204. * EBI: 8 Addrss Lines
  205. *
  206. * GPY3[0] EBI_ADDR[0](2)
  207. * GPY3[1] EBI_ADDR[1](2)
  208. * GPY3[2] EBI_ADDR[2](2)
  209. * GPY3[3] EBI_ADDR[3](2)
  210. * GPY3[4] EBI_ADDR[4](2)
  211. * GPY3[5] EBI_ADDR[5](2)
  212. * GPY3[6] EBI_ADDR[6](2)
  213. * GPY3[7] EBI_ADDR[7](2)
  214. *
  215. * EBI: 16 Data Lines
  216. *
  217. * GPY5[0] EBI_DATA[0](2)
  218. * GPY5[1] EBI_DATA[1](2)
  219. * GPY5[2] EBI_DATA[2](2)
  220. * GPY5[3] EBI_DATA[3](2)
  221. * GPY5[4] EBI_DATA[4](2)
  222. * GPY5[5] EBI_DATA[5](2)
  223. * GPY5[6] EBI_DATA[6](2)
  224. * GPY5[7] EBI_DATA[7](2)
  225. *
  226. * GPY6[0] EBI_DATA[8](2)
  227. * GPY6[1] EBI_DATA[9](2)
  228. * GPY6[2] EBI_DATA[10](2)
  229. * GPY6[3] EBI_DATA[11](2)
  230. * GPY6[4] EBI_DATA[12](2)
  231. * GPY6[5] EBI_DATA[13](2)
  232. * GPY6[6] EBI_DATA[14](2)
  233. * GPY6[7] EBI_DATA[15](2)
  234. */
  235. for (i = 0; i < 8; i++) {
  236. gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
  237. gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
  238. gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
  239. gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
  240. gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
  241. gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
  242. }
  243. }
  244. static void exynos5_i2c_config(int peripheral, int flags)
  245. {
  246. int func01, func23;
  247. /* High-Speed I2C */
  248. if (flags & PINMUX_FLAG_HS_MODE) {
  249. func01 = 4;
  250. func23 = 4;
  251. } else {
  252. func01 = 2;
  253. func23 = 3;
  254. }
  255. switch (peripheral) {
  256. case PERIPH_ID_I2C0:
  257. gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
  258. gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
  259. break;
  260. case PERIPH_ID_I2C1:
  261. gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
  262. gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
  263. break;
  264. case PERIPH_ID_I2C2:
  265. gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
  266. gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
  267. break;
  268. case PERIPH_ID_I2C3:
  269. gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
  270. gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
  271. break;
  272. case PERIPH_ID_I2C4:
  273. gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
  274. gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
  275. break;
  276. case PERIPH_ID_I2C5:
  277. gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
  278. gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
  279. break;
  280. case PERIPH_ID_I2C6:
  281. gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
  282. gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
  283. break;
  284. case PERIPH_ID_I2C7:
  285. gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
  286. gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
  287. break;
  288. }
  289. }
  290. static void exynos5420_i2c_config(int peripheral)
  291. {
  292. switch (peripheral) {
  293. case PERIPH_ID_I2C0:
  294. gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
  295. gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
  296. break;
  297. case PERIPH_ID_I2C1:
  298. gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
  299. gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
  300. break;
  301. case PERIPH_ID_I2C2:
  302. gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
  303. gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
  304. break;
  305. case PERIPH_ID_I2C3:
  306. gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
  307. gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
  308. break;
  309. case PERIPH_ID_I2C4:
  310. gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
  311. gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
  312. break;
  313. case PERIPH_ID_I2C5:
  314. gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
  315. gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
  316. break;
  317. case PERIPH_ID_I2C6:
  318. gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
  319. gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
  320. break;
  321. case PERIPH_ID_I2C7:
  322. gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
  323. gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
  324. break;
  325. case PERIPH_ID_I2C8:
  326. gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
  327. gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
  328. break;
  329. case PERIPH_ID_I2C9:
  330. gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
  331. gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
  332. break;
  333. case PERIPH_ID_I2C10:
  334. gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
  335. gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
  336. break;
  337. }
  338. }
  339. static void exynos5_i2s_config(int peripheral)
  340. {
  341. int i;
  342. switch (peripheral) {
  343. case PERIPH_ID_I2S0:
  344. for (i = 0; i < 5; i++)
  345. gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
  346. break;
  347. case PERIPH_ID_I2S1:
  348. for (i = 0; i < 5; i++)
  349. gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
  350. break;
  351. }
  352. }
  353. static void exynos5420_i2s_config(int peripheral)
  354. {
  355. int i;
  356. switch (peripheral) {
  357. case PERIPH_ID_I2S0:
  358. for (i = 0; i < 5; i++)
  359. gpio_cfg_pin(EXYNOS5420_GPIO_Z0 + i,
  360. S5P_GPIO_FUNC(0x02));
  361. break;
  362. }
  363. }
  364. void exynos5_spi_config(int peripheral)
  365. {
  366. int cfg = 0, pin = 0, i;
  367. switch (peripheral) {
  368. case PERIPH_ID_SPI0:
  369. cfg = S5P_GPIO_FUNC(0x2);
  370. pin = EXYNOS5_GPIO_A20;
  371. break;
  372. case PERIPH_ID_SPI1:
  373. cfg = S5P_GPIO_FUNC(0x2);
  374. pin = EXYNOS5_GPIO_A24;
  375. break;
  376. case PERIPH_ID_SPI2:
  377. cfg = S5P_GPIO_FUNC(0x5);
  378. pin = EXYNOS5_GPIO_B11;
  379. break;
  380. case PERIPH_ID_SPI3:
  381. cfg = S5P_GPIO_FUNC(0x2);
  382. pin = EXYNOS5_GPIO_F10;
  383. break;
  384. case PERIPH_ID_SPI4:
  385. for (i = 0; i < 2; i++) {
  386. gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
  387. gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
  388. }
  389. break;
  390. }
  391. if (peripheral != PERIPH_ID_SPI4) {
  392. for (i = pin; i < pin + 4; i++)
  393. gpio_cfg_pin(i, cfg);
  394. }
  395. }
  396. void exynos5420_spi_config(int peripheral)
  397. {
  398. int cfg, pin, i;
  399. switch (peripheral) {
  400. case PERIPH_ID_SPI0:
  401. pin = EXYNOS5420_GPIO_A20;
  402. cfg = S5P_GPIO_FUNC(0x2);
  403. break;
  404. case PERIPH_ID_SPI1:
  405. pin = EXYNOS5420_GPIO_A24;
  406. cfg = S5P_GPIO_FUNC(0x2);
  407. break;
  408. case PERIPH_ID_SPI2:
  409. pin = EXYNOS5420_GPIO_B11;
  410. cfg = S5P_GPIO_FUNC(0x5);
  411. break;
  412. case PERIPH_ID_SPI3:
  413. pin = EXYNOS5420_GPIO_F10;
  414. cfg = S5P_GPIO_FUNC(0x2);
  415. break;
  416. case PERIPH_ID_SPI4:
  417. cfg = 0;
  418. pin = 0;
  419. break;
  420. default:
  421. cfg = 0;
  422. pin = 0;
  423. debug("%s: invalid peripheral %d", __func__, peripheral);
  424. return;
  425. }
  426. if (peripheral != PERIPH_ID_SPI4) {
  427. for (i = pin; i < pin + 4; i++)
  428. gpio_cfg_pin(i, cfg);
  429. } else {
  430. for (i = 0; i < 2; i++) {
  431. gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
  432. S5P_GPIO_FUNC(0x4));
  433. gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
  434. S5P_GPIO_FUNC(0x4));
  435. }
  436. }
  437. }
  438. static int exynos5_pinmux_config(int peripheral, int flags)
  439. {
  440. switch (peripheral) {
  441. case PERIPH_ID_UART0:
  442. case PERIPH_ID_UART1:
  443. case PERIPH_ID_UART2:
  444. case PERIPH_ID_UART3:
  445. exynos5_uart_config(peripheral);
  446. break;
  447. case PERIPH_ID_SDMMC0:
  448. case PERIPH_ID_SDMMC1:
  449. case PERIPH_ID_SDMMC2:
  450. case PERIPH_ID_SDMMC3:
  451. return exynos5_mmc_config(peripheral, flags);
  452. case PERIPH_ID_SROMC:
  453. exynos5_sromc_config(flags);
  454. break;
  455. case PERIPH_ID_I2C0:
  456. case PERIPH_ID_I2C1:
  457. case PERIPH_ID_I2C2:
  458. case PERIPH_ID_I2C3:
  459. case PERIPH_ID_I2C4:
  460. case PERIPH_ID_I2C5:
  461. case PERIPH_ID_I2C6:
  462. case PERIPH_ID_I2C7:
  463. exynos5_i2c_config(peripheral, flags);
  464. break;
  465. case PERIPH_ID_I2S0:
  466. case PERIPH_ID_I2S1:
  467. exynos5_i2s_config(peripheral);
  468. break;
  469. case PERIPH_ID_SPI0:
  470. case PERIPH_ID_SPI1:
  471. case PERIPH_ID_SPI2:
  472. case PERIPH_ID_SPI3:
  473. case PERIPH_ID_SPI4:
  474. exynos5_spi_config(peripheral);
  475. break;
  476. case PERIPH_ID_DPHPD:
  477. /* Set Hotplug detect for DP */
  478. gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
  479. /*
  480. * Hotplug detect should have an external pullup; disable the
  481. * internal pulldown so they don't fight.
  482. */
  483. gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
  484. break;
  485. case PERIPH_ID_PWM0:
  486. gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2));
  487. break;
  488. default:
  489. debug("%s: invalid peripheral %d", __func__, peripheral);
  490. return -1;
  491. }
  492. return 0;
  493. }
  494. static int exynos5420_pinmux_config(int peripheral, int flags)
  495. {
  496. switch (peripheral) {
  497. case PERIPH_ID_UART0:
  498. case PERIPH_ID_UART1:
  499. case PERIPH_ID_UART2:
  500. case PERIPH_ID_UART3:
  501. exynos5420_uart_config(peripheral);
  502. break;
  503. case PERIPH_ID_SDMMC0:
  504. case PERIPH_ID_SDMMC1:
  505. case PERIPH_ID_SDMMC2:
  506. case PERIPH_ID_SDMMC3:
  507. return exynos5420_mmc_config(peripheral, flags);
  508. case PERIPH_ID_SPI0:
  509. case PERIPH_ID_SPI1:
  510. case PERIPH_ID_SPI2:
  511. case PERIPH_ID_SPI3:
  512. case PERIPH_ID_SPI4:
  513. exynos5420_spi_config(peripheral);
  514. break;
  515. case PERIPH_ID_I2C0:
  516. case PERIPH_ID_I2C1:
  517. case PERIPH_ID_I2C2:
  518. case PERIPH_ID_I2C3:
  519. case PERIPH_ID_I2C4:
  520. case PERIPH_ID_I2C5:
  521. case PERIPH_ID_I2C6:
  522. case PERIPH_ID_I2C7:
  523. case PERIPH_ID_I2C8:
  524. case PERIPH_ID_I2C9:
  525. case PERIPH_ID_I2C10:
  526. exynos5420_i2c_config(peripheral);
  527. break;
  528. case PERIPH_ID_I2S0:
  529. exynos5420_i2s_config(peripheral);
  530. break;
  531. case PERIPH_ID_PWM0:
  532. gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2));
  533. break;
  534. default:
  535. debug("%s: invalid peripheral %d", __func__, peripheral);
  536. return -1;
  537. }
  538. return 0;
  539. }
  540. static void exynos4_i2c_config(int peripheral, int flags)
  541. {
  542. switch (peripheral) {
  543. case PERIPH_ID_I2C0:
  544. gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
  545. gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
  546. break;
  547. case PERIPH_ID_I2C1:
  548. gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
  549. gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
  550. break;
  551. case PERIPH_ID_I2C2:
  552. gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
  553. gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
  554. break;
  555. case PERIPH_ID_I2C3:
  556. gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
  557. gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
  558. break;
  559. case PERIPH_ID_I2C4:
  560. gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
  561. gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
  562. break;
  563. case PERIPH_ID_I2C5:
  564. gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
  565. gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
  566. break;
  567. case PERIPH_ID_I2C6:
  568. gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
  569. gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
  570. break;
  571. case PERIPH_ID_I2C7:
  572. gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
  573. gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
  574. break;
  575. }
  576. }
  577. static int exynos4_mmc_config(int peripheral, int flags)
  578. {
  579. int i, start = 0, start_ext = 0;
  580. unsigned int func, ext_func;
  581. switch (peripheral) {
  582. case PERIPH_ID_SDMMC0:
  583. start = EXYNOS4_GPIO_K00;
  584. start_ext = EXYNOS4_GPIO_K13;
  585. func = S5P_GPIO_FUNC(0x2);
  586. ext_func = S5P_GPIO_FUNC(0x3);
  587. break;
  588. case PERIPH_ID_SDMMC2:
  589. start = EXYNOS4_GPIO_K20;
  590. start_ext = EXYNOS4_GPIO_K33;
  591. func = S5P_GPIO_FUNC(0x2);
  592. ext_func = S5P_GPIO_FUNC(0x3);
  593. break;
  594. case PERIPH_ID_SDMMC4:
  595. start = EXYNOS4_GPIO_K00;
  596. start_ext = EXYNOS4_GPIO_K13;
  597. func = S5P_GPIO_FUNC(0x3);
  598. ext_func = S5P_GPIO_FUNC(0x4);
  599. break;
  600. default:
  601. return -1;
  602. }
  603. for (i = start; i < (start + 7); i++) {
  604. if (i == (start + 2))
  605. continue;
  606. gpio_cfg_pin(i, func);
  607. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  608. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  609. }
  610. /* SDMMC2 do not use 8bit mode at exynos4 */
  611. if (flags & PINMUX_FLAG_8BIT_MODE) {
  612. for (i = start_ext; i < (start_ext + 4); i++) {
  613. gpio_cfg_pin(i, ext_func);
  614. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  615. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  616. }
  617. }
  618. return 0;
  619. }
  620. static void exynos4_uart_config(int peripheral)
  621. {
  622. int i, start, count;
  623. switch (peripheral) {
  624. case PERIPH_ID_UART0:
  625. start = EXYNOS4_GPIO_A00;
  626. count = 4;
  627. break;
  628. case PERIPH_ID_UART1:
  629. start = EXYNOS4_GPIO_A04;
  630. count = 4;
  631. break;
  632. case PERIPH_ID_UART2:
  633. start = EXYNOS4_GPIO_A10;
  634. count = 4;
  635. break;
  636. case PERIPH_ID_UART3:
  637. start = EXYNOS4_GPIO_A14;
  638. count = 2;
  639. break;
  640. default:
  641. debug("%s: invalid peripheral %d", __func__, peripheral);
  642. return;
  643. }
  644. for (i = start; i < (start + count); i++) {
  645. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  646. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  647. }
  648. }
  649. static void exynos4x12_i2c_config(int peripheral, int flags)
  650. {
  651. switch (peripheral) {
  652. case PERIPH_ID_I2C0:
  653. gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
  654. gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
  655. break;
  656. case PERIPH_ID_I2C1:
  657. gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
  658. gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
  659. break;
  660. case PERIPH_ID_I2C2:
  661. gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
  662. gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
  663. break;
  664. case PERIPH_ID_I2C3:
  665. gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
  666. gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
  667. break;
  668. case PERIPH_ID_I2C4:
  669. gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
  670. gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
  671. break;
  672. case PERIPH_ID_I2C5:
  673. gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
  674. gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
  675. break;
  676. case PERIPH_ID_I2C6:
  677. gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
  678. gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
  679. break;
  680. case PERIPH_ID_I2C7:
  681. gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
  682. gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
  683. break;
  684. }
  685. }
  686. static int exynos4x12_mmc_config(int peripheral, int flags)
  687. {
  688. int i, start = 0, start_ext = 0;
  689. unsigned int func, ext_func;
  690. switch (peripheral) {
  691. case PERIPH_ID_SDMMC0:
  692. start = EXYNOS4X12_GPIO_K00;
  693. start_ext = EXYNOS4X12_GPIO_K13;
  694. func = S5P_GPIO_FUNC(0x2);
  695. ext_func = S5P_GPIO_FUNC(0x3);
  696. break;
  697. case PERIPH_ID_SDMMC2:
  698. start = EXYNOS4X12_GPIO_K20;
  699. start_ext = EXYNOS4X12_GPIO_K33;
  700. func = S5P_GPIO_FUNC(0x2);
  701. ext_func = S5P_GPIO_FUNC(0x3);
  702. break;
  703. case PERIPH_ID_SDMMC4:
  704. start = EXYNOS4X12_GPIO_K00;
  705. start_ext = EXYNOS4X12_GPIO_K13;
  706. func = S5P_GPIO_FUNC(0x3);
  707. ext_func = S5P_GPIO_FUNC(0x4);
  708. break;
  709. default:
  710. return -1;
  711. }
  712. for (i = start; i < (start + 7); i++) {
  713. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  714. if (i == (start + 2))
  715. continue;
  716. gpio_cfg_pin(i, func);
  717. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  718. }
  719. if (flags & PINMUX_FLAG_8BIT_MODE) {
  720. for (i = start_ext; i < (start_ext + 4); i++) {
  721. gpio_cfg_pin(i, ext_func);
  722. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  723. gpio_set_drv(i, S5P_GPIO_DRV_4X);
  724. }
  725. }
  726. return 0;
  727. }
  728. static void exynos4x12_uart_config(int peripheral)
  729. {
  730. int i, start, count;
  731. switch (peripheral) {
  732. case PERIPH_ID_UART0:
  733. start = EXYNOS4X12_GPIO_A00;
  734. count = 4;
  735. break;
  736. case PERIPH_ID_UART1:
  737. start = EXYNOS4X12_GPIO_A04;
  738. count = 4;
  739. break;
  740. case PERIPH_ID_UART2:
  741. start = EXYNOS4X12_GPIO_A10;
  742. count = 4;
  743. break;
  744. case PERIPH_ID_UART3:
  745. start = EXYNOS4X12_GPIO_A14;
  746. count = 2;
  747. break;
  748. default:
  749. debug("%s: invalid peripheral %d", __func__, peripheral);
  750. return;
  751. }
  752. for (i = start; i < (start + count); i++) {
  753. gpio_set_pull(i, S5P_GPIO_PULL_NONE);
  754. gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
  755. }
  756. }
  757. static int exynos4_pinmux_config(int peripheral, int flags)
  758. {
  759. switch (peripheral) {
  760. case PERIPH_ID_UART0:
  761. case PERIPH_ID_UART1:
  762. case PERIPH_ID_UART2:
  763. case PERIPH_ID_UART3:
  764. exynos4_uart_config(peripheral);
  765. break;
  766. case PERIPH_ID_I2C0:
  767. case PERIPH_ID_I2C1:
  768. case PERIPH_ID_I2C2:
  769. case PERIPH_ID_I2C3:
  770. case PERIPH_ID_I2C4:
  771. case PERIPH_ID_I2C5:
  772. case PERIPH_ID_I2C6:
  773. case PERIPH_ID_I2C7:
  774. exynos4_i2c_config(peripheral, flags);
  775. break;
  776. case PERIPH_ID_SDMMC0:
  777. case PERIPH_ID_SDMMC2:
  778. case PERIPH_ID_SDMMC4:
  779. return exynos4_mmc_config(peripheral, flags);
  780. case PERIPH_ID_SDMMC1:
  781. case PERIPH_ID_SDMMC3:
  782. debug("SDMMC device %d not implemented\n", peripheral);
  783. return -1;
  784. default:
  785. debug("%s: invalid peripheral %d", __func__, peripheral);
  786. return -1;
  787. }
  788. return 0;
  789. }
  790. static int exynos4x12_pinmux_config(int peripheral, int flags)
  791. {
  792. switch (peripheral) {
  793. case PERIPH_ID_UART0:
  794. case PERIPH_ID_UART1:
  795. case PERIPH_ID_UART2:
  796. case PERIPH_ID_UART3:
  797. exynos4x12_uart_config(peripheral);
  798. break;
  799. case PERIPH_ID_I2C0:
  800. case PERIPH_ID_I2C1:
  801. case PERIPH_ID_I2C2:
  802. case PERIPH_ID_I2C3:
  803. case PERIPH_ID_I2C4:
  804. case PERIPH_ID_I2C5:
  805. case PERIPH_ID_I2C6:
  806. case PERIPH_ID_I2C7:
  807. exynos4x12_i2c_config(peripheral, flags);
  808. break;
  809. case PERIPH_ID_SDMMC0:
  810. case PERIPH_ID_SDMMC2:
  811. case PERIPH_ID_SDMMC4:
  812. return exynos4x12_mmc_config(peripheral, flags);
  813. case PERIPH_ID_SDMMC1:
  814. case PERIPH_ID_SDMMC3:
  815. debug("SDMMC device %d not implemented\n", peripheral);
  816. return -1;
  817. default:
  818. debug("%s: invalid peripheral %d", __func__, peripheral);
  819. return -1;
  820. }
  821. return 0;
  822. }
  823. int exynos_pinmux_config(int peripheral, int flags)
  824. {
  825. if (cpu_is_exynos5()) {
  826. if (proid_is_exynos542x())
  827. return exynos5420_pinmux_config(peripheral, flags);
  828. else if (proid_is_exynos5250())
  829. return exynos5_pinmux_config(peripheral, flags);
  830. } else if (cpu_is_exynos4()) {
  831. if (proid_is_exynos4412())
  832. return exynos4x12_pinmux_config(peripheral, flags);
  833. else
  834. return exynos4_pinmux_config(peripheral, flags);
  835. }
  836. debug("pinmux functionality not supported\n");
  837. return -1;
  838. }
  839. #if CONFIG_IS_ENABLED(OF_CONTROL)
  840. static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
  841. {
  842. int err;
  843. u32 cell[3];
  844. err = fdtdec_get_int_array(blob, node, "interrupts", cell,
  845. ARRAY_SIZE(cell));
  846. if (err) {
  847. debug(" invalid peripheral id\n");
  848. return PERIPH_ID_NONE;
  849. }
  850. return cell[1];
  851. }
  852. static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
  853. {
  854. int err;
  855. u32 cell[3];
  856. err = fdtdec_get_int_array(blob, node, "interrupts", cell,
  857. ARRAY_SIZE(cell));
  858. if (err)
  859. return PERIPH_ID_NONE;
  860. return cell[1];
  861. }
  862. int pinmux_decode_periph_id(const void *blob, int node)
  863. {
  864. if (cpu_is_exynos5())
  865. return exynos5_pinmux_decode_periph_id(blob, node);
  866. else if (cpu_is_exynos4())
  867. return exynos4_pinmux_decode_periph_id(blob, node);
  868. return PERIPH_ID_NONE;
  869. }
  870. #endif