exynos5_setup.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Machine Specific Values for SMDK5250 board based on EXYNOS5
  4. *
  5. * Copyright (C) 2012 Samsung Electronics
  6. */
  7. #ifndef _SMDK5250_SETUP_H
  8. #define _SMDK5250_SETUP_H
  9. #include <config.h>
  10. #include <asm/arch/dmc.h>
  11. #define NOT_AVAILABLE 0
  12. #define DATA_MASK 0xFFFFF
  13. #define ENABLE_BIT 0x1
  14. #define DISABLE_BIT 0x0
  15. #define CA_SWAP_EN (1 << 0)
  16. /* Set PLL */
  17. #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
  18. /* MEMCONTROL register bit fields */
  19. #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
  20. #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
  21. #define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
  22. #define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
  23. #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
  24. #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
  25. #define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
  26. #define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
  27. #define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
  28. #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
  29. #define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
  30. #define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
  31. #define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
  32. #define DMC_MEMCONTROL_BL_8 (3 << 20)
  33. #define DMC_MEMCONTROL_BL_4 (2 << 20)
  34. #define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
  35. #define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
  36. #define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
  37. #define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
  38. #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
  39. /* MEMCONFIG0 register bit fields */
  40. #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
  41. #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
  42. #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
  43. #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
  44. #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
  45. #define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
  46. #define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
  47. #define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
  48. #define DMC_MEMBASECONFIG_VAL(x) ( \
  49. DMC_MEMBASECONFIGX_CHIP_BASE(x) | \
  50. DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
  51. )
  52. /*
  53. * As we use channel interleaving, therefore value of the base address
  54. * register must be set as half of the bus base address
  55. * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
  56. * we need to set half 0x10 to the membaseconfigx registers
  57. * see exynos5420 UM section 17.17.3.21 for more.
  58. */
  59. #define DMC_CHIP_BASE_0 0x10
  60. #define DMC_CHIP_BASE_1 0x50
  61. #define DMC_CHIP_MASK 0x7C0
  62. #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
  63. #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
  64. #define DMC_PRECHCONFIG_VAL 0xFF000000
  65. #define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
  66. #define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
  67. #define DFI_INIT_START (1 << 28)
  68. #define EMPTY (1 << 8)
  69. #define AREF_EN (1 << 5)
  70. #define DFI_INIT_COMPLETE_CHO (1 << 2)
  71. #define DFI_INIT_COMPLETE_CH1 (1 << 3)
  72. #define RDLVL_COMPLETE_CHO (1 << 14)
  73. #define RDLVL_COMPLETE_CH1 (1 << 15)
  74. #define CLK_STOP_EN (1 << 0)
  75. #define DPWRDN_EN (1 << 1)
  76. #define DSREF_EN (1 << 5)
  77. /* COJCONTROL register bit fields */
  78. #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
  79. #define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
  80. #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
  81. #define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
  82. #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
  83. #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
  84. #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
  85. #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
  86. #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
  87. #define DMC_CONCONTROL_VAL 0x1FFF2101
  88. #define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
  89. | DMC_CONCONTROL_AREF_EN_ENABLE \
  90. | DMC_CONCONTROL_IO_PD_CON_ENABLE
  91. #define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
  92. /* CLK_DIV_CPU1 */
  93. #define HPM_RATIO 0x2
  94. #define COPY_RATIO 0x0
  95. /* CLK_DIV_CPU1 = 0x00000003 */
  96. #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
  97. | (COPY_RATIO))
  98. /* CLK_SRC_CORE0 */
  99. #define CLK_SRC_CORE0_VAL 0x00000000
  100. /* CLK_SRC_CORE1 */
  101. #define CLK_SRC_CORE1_VAL 0x100
  102. /* CLK_DIV_CORE0 */
  103. #define CLK_DIV_CORE0_VAL 0x00120000
  104. /* CLK_DIV_CORE1 */
  105. #define CLK_DIV_CORE1_VAL 0x07070700
  106. /* CLK_DIV_SYSRGT */
  107. #define CLK_DIV_SYSRGT_VAL 0x00000111
  108. /* CLK_DIV_ACP */
  109. #define CLK_DIV_ACP_VAL 0x12
  110. /* CLK_DIV_SYSLFT */
  111. #define CLK_DIV_SYSLFT_VAL 0x00000311
  112. #define MUX_APLL_SEL_MASK (1 << 0)
  113. #define MUX_MPLL_SEL_MASK (1 << 8)
  114. #define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
  115. #define MUX_CPLL_SEL_MASK (1 << 8)
  116. #define MUX_EPLL_SEL_MASK (1 << 12)
  117. #define MUX_VPLL_SEL_MASK (1 << 16)
  118. #define MUX_GPLL_SEL_MASK (1 << 28)
  119. #define MUX_BPLL_SEL_MASK (1 << 0)
  120. #define MUX_HPM_SEL_MASK (1 << 20)
  121. #define HPM_SEL_SCLK_MPLL (1 << 21)
  122. #define PLL_LOCKED (1 << 29)
  123. #define APLL_CON0_LOCKED (1 << 29)
  124. #define MPLL_CON0_LOCKED (1 << 29)
  125. #define BPLL_CON0_LOCKED (1 << 29)
  126. #define CPLL_CON0_LOCKED (1 << 29)
  127. #define EPLL_CON0_LOCKED (1 << 29)
  128. #define GPLL_CON0_LOCKED (1 << 29)
  129. #define VPLL_CON0_LOCKED (1 << 29)
  130. #define CLK_REG_DISABLE 0x0
  131. #define TOP2_VAL 0x0110000
  132. /* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
  133. #define SPI0_ISP_SEL 6
  134. #define SPI1_ISP_SEL 6
  135. #define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
  136. | (SPI0_ISP_SEL << 0)
  137. /* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
  138. #define SPI0_ISP_RATIO 0xf
  139. #define SPI1_ISP_RATIO 0xf
  140. #define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
  141. | (SPI0_ISP_RATIO << 0)
  142. /* CLK_DIV_FSYS2 */
  143. #define MMC2_RATIO_MASK 0xf
  144. #define MMC2_RATIO_VAL 0x3
  145. #define MMC2_RATIO_OFFSET 0
  146. #define MMC2_PRE_RATIO_MASK 0xff
  147. #define MMC2_PRE_RATIO_VAL 0x9
  148. #define MMC2_PRE_RATIO_OFFSET 8
  149. #define MMC3_RATIO_MASK 0xf
  150. #define MMC3_RATIO_VAL 0x1
  151. #define MMC3_RATIO_OFFSET 16
  152. #define MMC3_PRE_RATIO_MASK 0xff
  153. #define MMC3_PRE_RATIO_VAL 0x0
  154. #define MMC3_PRE_RATIO_OFFSET 24
  155. /* CLK_SRC_LEX */
  156. #define CLK_SRC_LEX_VAL 0x0
  157. /* CLK_DIV_LEX */
  158. #define CLK_DIV_LEX_VAL 0x10
  159. /* CLK_DIV_R0X */
  160. #define CLK_DIV_R0X_VAL 0x10
  161. /* CLK_DIV_L0X */
  162. #define CLK_DIV_R1X_VAL 0x10
  163. /* CLK_DIV_ISP2 */
  164. #define CLK_DIV_ISP2_VAL 0x1
  165. /* CLK_SRC_KFC */
  166. #define SRC_KFC_HPM_SEL (1 << 15)
  167. /* CLK_SRC_KFC */
  168. #define CLK_SRC_KFC_VAL 0x00008001
  169. /* CLK_DIV_KFC */
  170. #define CLK_DIV_KFC_VAL 0x03300110
  171. /* CLK_DIV2_RATIO */
  172. #define CLK_DIV2_RATIO 0x10111150
  173. /* CLK_DIV4_RATIO */
  174. #define CLK_DIV4_RATIO 0x00000003
  175. /* CLK_DIV_G2D */
  176. #define CLK_DIV_G2D 0x00000010
  177. /*
  178. * DIV_DISP1_0
  179. * For DP, divisor should be 2
  180. */
  181. #define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
  182. /* CLK_GATE_IP_DISP1 */
  183. #define CLK_GATE_DP1_ALLOW (1 << 4)
  184. /* AUDIO CLK SEL */
  185. #define AUDIO0_SEL_EPLL (0x6 << 28)
  186. #define AUDIO0_RATIO 0x5
  187. #define PCM0_RATIO 0x3
  188. #define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
  189. /* CLK_SRC_CDREX */
  190. #define MUX_MCLK_CDR_MSPLL (1 << 4)
  191. #define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
  192. #define BPLL_SEL_MASK 0x7
  193. #define FOUTBPLL 2
  194. #define DDR3PHY_CTRL_PHY_RESET (1 << 0)
  195. #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
  196. #define PHY_CON0_RESET_VAL 0x17020a40
  197. #define P0_CMD_EN (1 << 14)
  198. #define BYTE_RDLVL_EN (1 << 13)
  199. #define CTRL_SHGATE (1 << 8)
  200. #define PHY_CON1_RESET_VAL 0x09210100
  201. #define RDLVL_PASS_ADJ_VAL 0x6
  202. #define RDLVL_PASS_ADJ_OFFSET 16
  203. #define CTRL_GATEDURADJ_MASK (0xf << 20)
  204. #define READ_LEVELLING_DDR3 0x0100
  205. #define PHY_CON2_RESET_VAL 0x00010004
  206. #define INIT_DESKEW_EN (1 << 6)
  207. #define DLL_DESKEW_EN (1 << 12)
  208. #define RDLVL_GATE_EN (1 << 24)
  209. #define RDLVL_EN (1 << 25)
  210. #define RDLVL_INCR_ADJ (0x1 << 16)
  211. /* DREX_PAUSE */
  212. #define DREX_PAUSE_EN (1 << 0)
  213. #define BYPASS_EN (1 << 22)
  214. /* MEMMORY VAL */
  215. #define PHY_CON0_VAL 0x17021A00
  216. #define PHY_CON12_RESET_VAL 0x10100070
  217. #define PHY_CON12_VAL 0x10107F50
  218. #define CTRL_START (1 << 6)
  219. #define CTRL_DLL_ON (1 << 5)
  220. #define CTRL_LOCK_COARSE_OFFSET 10
  221. #define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
  222. #define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
  223. CTRL_LOCK_COARSE_OFFSET)
  224. #define CTRL_FORCE_MASK (0x7F << 8)
  225. #define CTRL_FINE_LOCKED 0x7
  226. #define CTRL_OFFSETD_RESET_VAL 0x8
  227. #define CTRL_OFFSETD_VAL 0x7F
  228. #define CTRL_OFFSETR0 0x7F
  229. #define CTRL_OFFSETR1 0x7F
  230. #define CTRL_OFFSETR2 0x7F
  231. #define CTRL_OFFSETR3 0x7F
  232. #define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
  233. CTRL_OFFSETR1 << 8 | \
  234. CTRL_OFFSETR2 << 16 | \
  235. CTRL_OFFSETR3 << 24)
  236. #define PHY_CON4_RESET_VAL 0x08080808
  237. #define CTRL_OFFSETW0 0x7F
  238. #define CTRL_OFFSETW1 0x7F
  239. #define CTRL_OFFSETW2 0x7F
  240. #define CTRL_OFFSETW3 0x7F
  241. #define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
  242. CTRL_OFFSETW1 << 8 | \
  243. CTRL_OFFSETW2 << 16 | \
  244. CTRL_OFFSETW3 << 24)
  245. #define PHY_CON6_RESET_VAL 0x08080808
  246. #define PHY_CON14_RESET_VAL 0x001F0000
  247. #define CTRL_PULLD_DQS 0xF
  248. #define CTRL_PULLD_DQS_OFFSET 0
  249. /* ZQ Configurations */
  250. #define PHY_CON16_RESET_VAL 0x08000304
  251. #define ZQ_CLK_EN (1 << 27)
  252. #define ZQ_CLK_DIV_EN (1 << 18)
  253. #define ZQ_MANUAL_STR (1 << 1)
  254. #define ZQ_DONE (1 << 0)
  255. #define ZQ_MODE_DDS_OFFSET 24
  256. #define CTRL_RDLVL_GATE_ENABLE 1
  257. #define CTRL_RDLVL_GATE_DISABLE 0
  258. #define CTRL_RDLVL_DATA_ENABLE 2
  259. /* Direct Command */
  260. #define DIRECT_CMD_NOP 0x07000000
  261. #define DIRECT_CMD_PALL 0x01000000
  262. #define DIRECT_CMD_ZQINIT 0x0a000000
  263. #define DIRECT_CMD_CHANNEL_SHIFT 28
  264. #define DIRECT_CMD_CHIP_SHIFT 20
  265. #define DIRECT_CMD_BANK_SHIFT 16
  266. #define DIRECT_CMD_REFA (5 << 24)
  267. #define DIRECT_CMD_MRS1 0x71C00
  268. #define DIRECT_CMD_MRS2 0x10BFC
  269. #define DIRECT_CMD_MRS3 0x0050C
  270. #define DIRECT_CMD_MRS4 0x00868
  271. #define DIRECT_CMD_MRS5 0x00C04
  272. /* Drive Strength */
  273. #define IMPEDANCE_48_OHM 4
  274. #define IMPEDANCE_40_OHM 5
  275. #define IMPEDANCE_34_OHM 6
  276. #define IMPEDANCE_30_OHM 7
  277. #define PHY_CON39_VAL_48_OHM 0x09240924
  278. #define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
  279. #define PHY_CON39_VAL_34_OHM 0x0DB60DB6
  280. #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
  281. #define CTRL_BSTLEN_OFFSET 8
  282. #define CTRL_RDLAT_OFFSET 0
  283. #define CMD_DEFAULT_LPDDR3 0xF
  284. #define CMD_DEFUALT_OFFSET 0
  285. #define T_WRDATA_EN 0x7
  286. #define T_WRDATA_EN_DDR3 0x8
  287. #define T_WRDATA_EN_OFFSET 16
  288. #define T_WRDATA_EN_MASK 0x1f
  289. #define PHY_CON31_VAL 0x0C183060
  290. #define PHY_CON32_VAL 0x60C18306
  291. #define PHY_CON33_VAL 0x00000030
  292. #define PHY_CON31_RESET_VAL 0x0
  293. #define PHY_CON32_RESET_VAL 0x0
  294. #define PHY_CON33_RESET_VAL 0x0
  295. #define SL_DLL_DYN_CON_EN (1 << 1)
  296. #define FP_RESYNC (1 << 3)
  297. #define CTRL_START (1 << 6)
  298. #define DMC_AREF_EN (1 << 5)
  299. #define DMC_CONCONTROL_EMPTY (1 << 8)
  300. #define DFI_INIT_START (1 << 28)
  301. #define DMC_MEMCONTROL_VAL 0x00312700
  302. #define CLK_STOP_EN (1 << 0)
  303. #define DPWRDN_EN (1 << 1)
  304. #define DSREF_EN (1 << 5)
  305. #define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
  306. #define MEMBASECONFIG_CHIP_MASK_OFFSET 0
  307. #define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
  308. #define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
  309. #define CHIP_BASE_OFFSET 16
  310. #define MEMCONFIG_VAL 0x1323
  311. #define PRECHCONFIG_DEFAULT_VAL 0xFF000000
  312. #define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
  313. #define TIMINGAREF_VAL 0x5d
  314. #define TIMINGROW_VAL 0x345A8692
  315. #define TIMINGDATA_VAL 0x3630065C
  316. #define TIMINGPOWER_VAL 0x50380336
  317. #define DFI_INIT_COMPLETE (1 << 3)
  318. #define BRBRSVCONTROL_VAL 0x00000033
  319. #define BRBRSVCONFIG_VAL 0x88778877
  320. /* Clock Gating Control (CGCONTROL) register */
  321. #define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
  322. #define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
  323. #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
  324. #define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
  325. #define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
  326. BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
  327. /* DMC PHY Control0 register */
  328. #define PHY_CONTROL0_RESET_VAL 0x0
  329. #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
  330. #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
  331. #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
  332. #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
  333. /* Driver strength for CK, CKE, CS & CA */
  334. #define IMP_OUTPUT_DRV_40_OHM 0x5
  335. #define IMP_OUTPUT_DRV_30_OHM 0x7
  336. #define DA_3_DS_OFFSET 25
  337. #define DA_2_DS_OFFSET 22
  338. #define DA_1_DS_OFFSET 19
  339. #define DA_0_DS_OFFSET 16
  340. #define CA_CK_DRVR_DS_OFFSET 9
  341. #define CA_CKE_DRVR_DS_OFFSET 6
  342. #define CA_CS_DRVR_DS_OFFSET 3
  343. #define CA_ADR_DRVR_DS_OFFSET 0
  344. #define PHY_CON42_CTRL_BSTLEN_SHIFT 8
  345. #define PHY_CON42_CTRL_RDLAT_SHIFT 0
  346. /*
  347. * Definitions that differ with SoC's.
  348. * Below is the part defining macros for Exynos5250.
  349. * Else part introduces macros for Exynos5420.
  350. */
  351. #ifndef CONFIG_EXYNOS5420
  352. /* APLL_CON1 */
  353. #define APLL_CON1_VAL (0x00203800)
  354. /* MPLL_CON1 */
  355. #define MPLL_CON1_VAL (0x00203800)
  356. /* CPLL_CON1 */
  357. #define CPLL_CON1_VAL (0x00203800)
  358. /* DPLL_CON1 */
  359. #define DPLL_CON1_VAL (NOT_AVAILABLE)
  360. /* GPLL_CON1 */
  361. #define GPLL_CON1_VAL (0x00203800)
  362. /* EPLL_CON1, CON2 */
  363. #define EPLL_CON1_VAL 0x00000000
  364. #define EPLL_CON2_VAL 0x00000080
  365. /* VPLL_CON1, CON2 */
  366. #define VPLL_CON1_VAL 0x00000000
  367. #define VPLL_CON2_VAL 0x00000080
  368. /* RPLL_CON1, CON2 */
  369. #define RPLL_CON1_VAL NOT_AVAILABLE
  370. #define RPLL_CON2_VAL NOT_AVAILABLE
  371. /* BPLL_CON1 */
  372. #define BPLL_CON1_VAL 0x00203800
  373. /* SPLL_CON1 */
  374. #define SPLL_CON1_VAL NOT_AVAILABLE
  375. /* IPLL_CON1 */
  376. #define IPLL_CON1_VAL NOT_AVAILABLE
  377. /* KPLL_CON1 */
  378. #define KPLL_CON1_VAL NOT_AVAILABLE
  379. /* CLK_SRC_ISP */
  380. #define CLK_SRC_ISP_VAL NOT_AVAILABLE
  381. #define CLK_DIV_ISP0_VAL 0x31
  382. #define CLK_DIV_ISP1_VAL 0x0
  383. /* CLK_FSYS */
  384. #define CLK_SRC_FSYS0_VAL 0x66666
  385. #define CLK_DIV_FSYS0_VAL 0x0BB00000
  386. #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
  387. #define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
  388. /* CLK_SRC_CPU */
  389. /* 0 = MOUTAPLL, 1 = SCLKMPLL */
  390. #define MUX_HPM_SEL 0
  391. #define MUX_CPU_SEL 0
  392. #define MUX_APLL_SEL 1
  393. #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
  394. | (MUX_CPU_SEL << 16) \
  395. | (MUX_APLL_SEL))
  396. /* CLK_SRC_CDREX */
  397. #define CLK_SRC_CDREX_VAL 0x1
  398. /* CLK_DIV_CDREX */
  399. #define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
  400. #define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
  401. /* CLK_DIV_CPU0_VAL */
  402. #define CLK_DIV_CPU0_VAL NOT_AVAILABLE
  403. #define MCLK_CDREX2_RATIO 0x0
  404. #define ACLK_EFCON_RATIO 0x1
  405. #define MCLK_DPHY_RATIO 0x1
  406. #define MCLK_CDREX_RATIO 0x1
  407. #define ACLK_C2C_200_RATIO 0x1
  408. #define C2C_CLK_400_RATIO 0x1
  409. #define PCLK_CDREX_RATIO 0x1
  410. #define ACLK_CDREX_RATIO 0x1
  411. #define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
  412. | (C2C_CLK_400_RATIO << 6) \
  413. | (PCLK_CDREX_RATIO << 4) \
  414. | (ACLK_CDREX_RATIO))
  415. /* CLK_SRC_TOP0 */
  416. #define MUX_ACLK_300_GSCL_SEL 0x0
  417. #define MUX_ACLK_300_GSCL_MID_SEL 0x0
  418. #define MUX_ACLK_400_G3D_MID_SEL 0x0
  419. #define MUX_ACLK_333_SEL 0x0
  420. #define MUX_ACLK_300_DISP1_SEL 0x0
  421. #define MUX_ACLK_300_DISP1_MID_SEL 0x0
  422. #define MUX_ACLK_200_SEL 0x0
  423. #define MUX_ACLK_166_SEL 0x0
  424. #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
  425. | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
  426. | (MUX_ACLK_400_G3D_MID_SEL << 20) \
  427. | (MUX_ACLK_333_SEL << 16) \
  428. | (MUX_ACLK_300_DISP1_SEL << 15) \
  429. | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
  430. | (MUX_ACLK_200_SEL << 12) \
  431. | (MUX_ACLK_166_SEL << 8))
  432. /* CLK_SRC_TOP1 */
  433. #define MUX_ACLK_400_G3D_SEL 0x1
  434. #define MUX_ACLK_400_ISP_SEL 0x0
  435. #define MUX_ACLK_400_IOP_SEL 0x0
  436. #define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
  437. #define MUX_ACLK_300_GSCL_MID1_SEL 0x0
  438. #define MUX_ACLK_300_DISP1_MID1_SEL 0x0
  439. #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
  440. |(MUX_ACLK_400_ISP_SEL << 24) \
  441. |(MUX_ACLK_400_IOP_SEL << 20) \
  442. |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
  443. |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
  444. |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
  445. /* CLK_SRC_TOP2 */
  446. #define MUX_GPLL_SEL 0x1
  447. #define MUX_BPLL_USER_SEL 0x0
  448. #define MUX_MPLL_USER_SEL 0x0
  449. #define MUX_VPLL_SEL 0x1
  450. #define MUX_EPLL_SEL 0x1
  451. #define MUX_CPLL_SEL 0x1
  452. #define VPLLSRC_SEL 0x0
  453. #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
  454. | (MUX_BPLL_USER_SEL << 24) \
  455. | (MUX_MPLL_USER_SEL << 20) \
  456. | (MUX_VPLL_SEL << 16) \
  457. | (MUX_EPLL_SEL << 12) \
  458. | (MUX_CPLL_SEL << 8) \
  459. | (VPLLSRC_SEL))
  460. /* CLK_SRC_TOP3 */
  461. #define MUX_ACLK_333_SUB_SEL 0x1
  462. #define MUX_ACLK_400_SUB_SEL 0x1
  463. #define MUX_ACLK_266_ISP_SUB_SEL 0x1
  464. #define MUX_ACLK_266_GPS_SUB_SEL 0x0
  465. #define MUX_ACLK_300_GSCL_SUB_SEL 0x1
  466. #define MUX_ACLK_266_GSCL_SUB_SEL 0x1
  467. #define MUX_ACLK_300_DISP1_SUB_SEL 0x1
  468. #define MUX_ACLK_200_DISP1_SUB_SEL 0x1
  469. #define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
  470. | (MUX_ACLK_400_SUB_SEL << 20) \
  471. | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
  472. | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
  473. | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
  474. | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
  475. | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
  476. | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
  477. #define CLK_SRC_TOP4_VAL NOT_AVAILABLE
  478. #define CLK_SRC_TOP5_VAL NOT_AVAILABLE
  479. #define CLK_SRC_TOP6_VAL NOT_AVAILABLE
  480. #define CLK_SRC_TOP7_VAL NOT_AVAILABLE
  481. /* CLK_DIV_TOP0 */
  482. #define ACLK_300_DISP1_RATIO 0x2
  483. #define ACLK_400_G3D_RATIO 0x0
  484. #define ACLK_333_RATIO 0x0
  485. #define ACLK_266_RATIO 0x2
  486. #define ACLK_200_RATIO 0x3
  487. #define ACLK_166_RATIO 0x1
  488. #define ACLK_133_RATIO 0x1
  489. #define ACLK_66_RATIO 0x5
  490. #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
  491. | (ACLK_400_G3D_RATIO << 24) \
  492. | (ACLK_333_RATIO << 20) \
  493. | (ACLK_266_RATIO << 16) \
  494. | (ACLK_200_RATIO << 12) \
  495. | (ACLK_166_RATIO << 8) \
  496. | (ACLK_133_RATIO << 4) \
  497. | (ACLK_66_RATIO))
  498. /* CLK_DIV_TOP1 */
  499. #define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
  500. #define ACLK_66_PRE_RATIO 0x1
  501. #define ACLK_400_ISP_RATIO 0x1
  502. #define ACLK_400_IOP_RATIO 0x1
  503. #define ACLK_300_GSCL_RATIO 0x2
  504. #define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
  505. | (ACLK_66_PRE_RATIO << 24) \
  506. | (ACLK_400_ISP_RATIO << 20) \
  507. | (ACLK_400_IOP_RATIO << 16) \
  508. | (ACLK_300_GSCL_RATIO << 12))
  509. #define CLK_DIV_TOP2_VAL NOT_AVAILABLE
  510. /* PLL Lock Value Factor */
  511. #define PLL_LOCK_FACTOR 250
  512. #define PLL_X_LOCK_FACTOR 3000
  513. /* CLK_SRC_PERIC0 */
  514. #define PWM_SEL 6
  515. #define UART3_SEL 6
  516. #define UART2_SEL 6
  517. #define UART1_SEL 6
  518. #define UART0_SEL 6
  519. /* SRC_CLOCK = SCLK_MPLL */
  520. #define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
  521. | (UART3_SEL << 12) \
  522. | (UART2_SEL << 8) \
  523. | (UART1_SEL << 4) \
  524. | (UART0_SEL))
  525. /* CLK_SRC_PERIC1 */
  526. /* SRC_CLOCK = SCLK_MPLL */
  527. #define SPI0_SEL 6
  528. #define SPI1_SEL 6
  529. #define SPI2_SEL 6
  530. #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
  531. | (SPI1_SEL << 20) \
  532. | (SPI0_SEL << 16))
  533. /* CLK_DIV_PERIL0 */
  534. #define UART5_RATIO 7
  535. #define UART4_RATIO 7
  536. #define UART3_RATIO 7
  537. #define UART2_RATIO 7
  538. #define UART1_RATIO 7
  539. #define UART0_RATIO 7
  540. #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
  541. | (UART2_RATIO << 8) \
  542. | (UART1_RATIO << 4) \
  543. | (UART0_RATIO))
  544. /* CLK_DIV_PERIC1 */
  545. #define SPI1_RATIO 0x7
  546. #define SPI0_RATIO 0xf
  547. #define SPI1_SUB_RATIO 0x0
  548. #define SPI0_SUB_RATIO 0x0
  549. #define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
  550. | ((SPI1_RATIO << 16) \
  551. | (SPI0_SUB_RATIO << 8) \
  552. | (SPI0_RATIO << 0)))
  553. /* CLK_DIV_PERIC2 */
  554. #define SPI2_RATIO 0xf
  555. #define SPI2_SUB_RATIO 0x0
  556. #define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
  557. | (SPI2_RATIO << 0))
  558. /* CLK_DIV_PERIC3 */
  559. #define PWM_RATIO 8
  560. #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
  561. /* CLK_DIV_PERIC4 */
  562. #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
  563. /* CLK_SRC_DISP1_0 */
  564. #define CLK_SRC_DISP1_0_VAL 0x6
  565. #define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
  566. #define APLL_FOUT (1 << 0)
  567. #define KPLL_FOUT NOT_AVAILABLE
  568. #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
  569. #else
  570. #define CPU_CONFIG_STATUS_OFFSET 0x80
  571. #define CPU_RST_FLAG_VAL 0xFCBA0D10
  572. #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
  573. /* APLL_CON1 */
  574. #define APLL_CON1_VAL (0x0020F300)
  575. /* MPLL_CON1 */
  576. #define MPLL_CON1_VAL (0x0020F300)
  577. /* CPLL_CON1 */
  578. #define CPLL_CON1_VAL 0x0020f300
  579. /* DPLL_CON1 */
  580. #define DPLL_CON1_VAL (0x0020F300)
  581. /* GPLL_CON1 */
  582. #define GPLL_CON1_VAL (NOT_AVAILABLE)
  583. /* EPLL_CON1, CON2 */
  584. #define EPLL_CON1_VAL 0x00000000
  585. #define EPLL_CON2_VAL 0x00000080
  586. /* VPLL_CON1, CON2 */
  587. #define VPLL_CON1_VAL 0x0020f300
  588. #define VPLL_CON2_VAL NOT_AVAILABLE
  589. /* RPLL_CON1, CON2 */
  590. #define RPLL_CON1_VAL 0x00000000
  591. #define RPLL_CON2_VAL 0x00000080
  592. /* BPLL_CON1 */
  593. #define BPLL_CON1_VAL 0x0020f300
  594. /* SPLL_CON1 */
  595. #define SPLL_CON1_VAL 0x0020f300
  596. /* IPLL_CON1 */
  597. #define IPLL_CON1_VAL 0x00000080
  598. /* KPLL_CON1 */
  599. #define KPLL_CON1_VAL 0x200000
  600. /* CLK_SRC_ISP */
  601. #define CLK_SRC_ISP_VAL 0x33366000
  602. #define CLK_DIV_ISP0_VAL 0x13131300
  603. #define CLK_DIV_ISP1_VAL 0xbb110202
  604. /* CLK_FSYS */
  605. #define CLK_SRC_FSYS0_VAL 0x33033300
  606. #define CLK_DIV_FSYS0_VAL 0x0
  607. #define CLK_DIV_FSYS1_VAL 0x04f13c4f
  608. #define CLK_DIV_FSYS2_VAL 0x041d0000
  609. /* CLK_SRC_CPU */
  610. /* 0 = MOUTAPLL, 1 = SCLKMPLL */
  611. #define MUX_HPM_SEL 1
  612. #define MUX_CPU_SEL 0
  613. #define MUX_APLL_SEL 1
  614. #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
  615. | (MUX_CPU_SEL << 16) \
  616. | (MUX_APLL_SEL))
  617. /* CLK_SRC_CDREX */
  618. #define CLK_SRC_CDREX_VAL 0x00000011
  619. /* CLK_DIV_CDREX */
  620. #define CLK_DIV_CDREX0_VAL 0x30010100
  621. #define CLK_DIV_CDREX1_VAL 0x300
  622. #define CLK_DIV_CDREX_VAL 0x17010100
  623. /* CLK_DIV_CPU0_VAL */
  624. #define CLK_DIV_CPU0_VAL 0x01440020
  625. /* CLK_SRC_TOP */
  626. #define CLK_SRC_TOP0_VAL 0x12221222
  627. #define CLK_SRC_TOP1_VAL 0x00100200
  628. #define CLK_SRC_TOP2_VAL 0x11101000
  629. #define CLK_SRC_TOP3_VAL 0x11111111
  630. #define CLK_SRC_TOP4_VAL 0x11110111
  631. #define CLK_SRC_TOP5_VAL 0x11111101
  632. #define CLK_SRC_TOP6_VAL 0x11110111
  633. #define CLK_SRC_TOP7_VAL 0x00022200
  634. /* CLK_DIV_TOP */
  635. #define CLK_DIV_TOP0_VAL 0x23712311
  636. #define CLK_DIV_TOP1_VAL 0x13100B00
  637. #define CLK_DIV_TOP2_VAL 0x11101100
  638. /* PLL Lock Value Factor */
  639. #define PLL_LOCK_FACTOR 200
  640. #define PLL_X_LOCK_FACTOR 3000
  641. /* CLK_SRC_PERIC0 */
  642. #define SPDIF_SEL 1
  643. #define PWM_SEL 3
  644. #define UART4_SEL 3
  645. #define UART3_SEL 3
  646. #define UART2_SEL 3
  647. #define UART1_SEL 3
  648. #define UART0_SEL 3
  649. /* SRC_CLOCK = SCLK_RPLL */
  650. #define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
  651. | (PWM_SEL << 24) \
  652. | (UART4_SEL << 20) \
  653. | (UART3_SEL << 16) \
  654. | (UART2_SEL << 12) \
  655. | (UART1_SEL << 8) \
  656. | (UART0_SEL << 4))
  657. /* CLK_SRC_PERIC1 */
  658. /* SRC_CLOCK = SCLK_EPLL */
  659. #define SPI0_SEL 6
  660. #define SPI1_SEL 6
  661. #define SPI2_SEL 6
  662. #define AUDIO0_SEL 6
  663. #define AUDIO1_SEL 6
  664. #define AUDIO2_SEL 6
  665. #define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
  666. | (SPI1_SEL << 24) \
  667. | (SPI0_SEL << 20) \
  668. | (AUDIO2_SEL << 16) \
  669. | (AUDIO2_SEL << 12) \
  670. | (AUDIO2_SEL << 8))
  671. /* CLK_DIV_PERIC0 */
  672. #define PWM_RATIO 8
  673. #define UART4_RATIO 9
  674. #define UART3_RATIO 9
  675. #define UART2_RATIO 9
  676. #define UART1_RATIO 9
  677. #define UART0_RATIO 9
  678. #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
  679. | (UART4_RATIO << 24) \
  680. | (UART3_RATIO << 20) \
  681. | (UART2_RATIO << 16) \
  682. | (UART1_RATIO << 12) \
  683. | (UART0_RATIO << 8))
  684. /* CLK_DIV_PERIC1 */
  685. #define SPI2_RATIO 0x1
  686. #define SPI1_RATIO 0x1
  687. #define SPI0_RATIO 0x1
  688. #define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
  689. | (SPI1_RATIO << 24) \
  690. | (SPI0_RATIO << 20))
  691. /* CLK_DIV_PERIC2 */
  692. #define PCM2_RATIO 0x3
  693. #define PCM1_RATIO 0x3
  694. #define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
  695. | (PCM1_RATIO << 16))
  696. /* CLK_DIV_PERIC3 */
  697. #define AUDIO2_RATIO 0x5
  698. #define AUDIO1_RATIO 0x5
  699. #define AUDIO0_RATIO 0x5
  700. #define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
  701. | (AUDIO1_RATIO << 24) \
  702. | (AUDIO0_RATIO << 20))
  703. /* CLK_DIV_PERIC4 */
  704. #define SPI2_PRE_RATIO 0x2
  705. #define SPI1_PRE_RATIO 0x2
  706. #define SPI0_PRE_RATIO 0x2
  707. #define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
  708. | (SPI1_PRE_RATIO << 16) \
  709. | (SPI0_PRE_RATIO << 8))
  710. /* CLK_SRC_DISP1_0 */
  711. #define CLK_SRC_DISP1_0_VAL 0x10666600
  712. #define CLK_DIV_DISP1_0_VAL 0x01050211
  713. #define APLL_FOUT (1 << 0)
  714. #define KPLL_FOUT (1 << 0)
  715. #define CLK_DIV_CPERI1_VAL 0x3f3f0000
  716. #endif
  717. struct mem_timings;
  718. /* Errors that we can encourter in low-level setup */
  719. enum {
  720. SETUP_ERR_OK,
  721. SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
  722. SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
  723. };
  724. /*
  725. * Memory variant specific initialization code for DDR3
  726. *
  727. * @param mem Memory timings for this memory type.
  728. * @param reset Reset DDR PHY during initialization.
  729. * @return 0 if ok, SETUP_ERR_... if there is a problem
  730. */
  731. int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
  732. /* Memory variant specific initialization code for LPDDR3 */
  733. void lpddr3_mem_ctrl_init(void);
  734. /*
  735. * Configure ZQ I/O interface
  736. *
  737. * @param mem Memory timings for this memory type.
  738. * @param phy0_con16 Register address for dmc_phy0->phy_con16
  739. * @param phy1_con16 Register address for dmc_phy1->phy_con16
  740. * @param phy0_con17 Register address for dmc_phy0->phy_con17
  741. * @param phy1_con17 Register address for dmc_phy1->phy_con17
  742. * @return 0 if ok, -1 on error
  743. */
  744. int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
  745. uint32_t *phy1_con16, uint32_t *phy0_con17,
  746. uint32_t *phy1_con17);
  747. /*
  748. * Send NOP and MRS/EMRS Direct commands
  749. *
  750. * @param mem Memory timings for this memory type.
  751. * @param directcmd Register address for dmc_phy->directcmd
  752. */
  753. void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
  754. /*
  755. * Send PALL Direct commands
  756. *
  757. * @param mem Memory timings for this memory type.
  758. * @param directcmd Register address for dmc_phy->directcmd
  759. */
  760. void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
  761. /*
  762. * Reset the DLL. This function is common between DDR3 and LPDDR2.
  763. * However, the reset value is different. So we are passing a flag
  764. * ddr_mode to distinguish between LPDDR2 and DDR3.
  765. *
  766. * @param phycontrol0 Register address for dmc_phy->phycontrol0
  767. * @param ddr_mode Type of DDR memory
  768. */
  769. void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
  770. #endif