ast2500-board.c 1.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <ram.h>
  10. #include <timer.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/timer.h>
  13. #include <asm/arch/wdt.h>
  14. #include <linux/err.h>
  15. #include <dm/uclass.h>
  16. /*
  17. * Second Watchdog Timer by default is configured
  18. * to trigger secondary boot source.
  19. */
  20. #define AST_2ND_BOOT_WDT 1
  21. /*
  22. * Third Watchdog Timer by default is configured
  23. * to toggle Flash address mode switch before reset.
  24. */
  25. #define AST_FLASH_ADDR_DETECT_WDT 2
  26. DECLARE_GLOBAL_DATA_PTR;
  27. void lowlevel_init(void)
  28. {
  29. /*
  30. * These two watchdogs need to be stopped as soon as possible,
  31. * otherwise the board might hang. By default they are set to
  32. * a very short timeout and even simple debug write to serial
  33. * console early in the init process might cause them to fire.
  34. */
  35. struct ast_wdt *flash_addr_wdt =
  36. (struct ast_wdt *)(WDT_BASE +
  37. sizeof(struct ast_wdt) *
  38. AST_FLASH_ADDR_DETECT_WDT);
  39. clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
  40. #ifndef CONFIG_FIRMWARE_2ND_BOOT
  41. struct ast_wdt *sec_boot_wdt =
  42. (struct ast_wdt *)(WDT_BASE +
  43. sizeof(struct ast_wdt) *
  44. AST_2ND_BOOT_WDT);
  45. clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
  46. #endif
  47. }
  48. int board_init(void)
  49. {
  50. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  51. return 0;
  52. }
  53. int dram_init(void)
  54. {
  55. struct udevice *dev;
  56. struct ram_info ram;
  57. int ret;
  58. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  59. if (ret) {
  60. debug("DRAM FAIL1\r\n");
  61. return ret;
  62. }
  63. ret = ram_get_info(dev, &ram);
  64. if (ret) {
  65. debug("DRAM FAIL2\r\n");
  66. return ret;
  67. }
  68. gd->ram_size = ram.size;
  69. return 0;
  70. }