cache.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /* for now: just dummy functions to satisfy the linker */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <asm/cache.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /*
  14. * Flush range from all levels of d-cache/unified-cache.
  15. * Affects the range [start, start + size - 1].
  16. */
  17. __weak void flush_cache(unsigned long start, unsigned long size)
  18. {
  19. flush_dcache_range(start, start + size);
  20. }
  21. /*
  22. * Default implementation:
  23. * do a range flush for the entire range
  24. */
  25. __weak void flush_dcache_all(void)
  26. {
  27. flush_cache(0, ~0);
  28. }
  29. /*
  30. * Default implementation of enable_caches()
  31. * Real implementation should be in platform code
  32. */
  33. __weak void enable_caches(void)
  34. {
  35. puts("WARNING: Caches not enabled\n");
  36. }
  37. __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
  38. {
  39. /* An empty stub, real implementation should be in platform code */
  40. }
  41. __weak void flush_dcache_range(unsigned long start, unsigned long stop)
  42. {
  43. /* An empty stub, real implementation should be in platform code */
  44. }
  45. int check_cache_range(unsigned long start, unsigned long stop)
  46. {
  47. int ok = 1;
  48. if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
  49. ok = 0;
  50. if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
  51. ok = 0;
  52. if (!ok) {
  53. warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
  54. start, stop);
  55. }
  56. return ok;
  57. }
  58. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  59. /*
  60. * Reserve one MMU section worth of address space below the malloc() area that
  61. * will be mapped uncached.
  62. */
  63. static unsigned long noncached_start;
  64. static unsigned long noncached_end;
  65. static unsigned long noncached_next;
  66. void noncached_set_region(void)
  67. {
  68. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  69. mmu_set_region_dcache_behaviour(noncached_start,
  70. noncached_end - noncached_start,
  71. DCACHE_OFF);
  72. #endif
  73. }
  74. void noncached_init(void)
  75. {
  76. phys_addr_t start, end;
  77. size_t size;
  78. /* If this calculation changes, update board_f.c:reserve_noncached() */
  79. end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
  80. size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
  81. start = end - size;
  82. debug("mapping memory %pa-%pa non-cached\n", &start, &end);
  83. noncached_start = start;
  84. noncached_end = end;
  85. noncached_next = start;
  86. noncached_set_region();
  87. }
  88. phys_addr_t noncached_alloc(size_t size, size_t align)
  89. {
  90. phys_addr_t next = ALIGN(noncached_next, align);
  91. if (next >= noncached_end || (noncached_end - next) < size)
  92. return 0;
  93. debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
  94. noncached_next = next + size;
  95. return next;
  96. }
  97. #endif /* CONFIG_SYS_NONCACHED_MEMORY */
  98. #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
  99. void invalidate_l2_cache(void)
  100. {
  101. unsigned int val = 0;
  102. asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
  103. : : "r" (val) : "cc");
  104. isb();
  105. }
  106. #endif
  107. int arch_reserve_mmu(void)
  108. {
  109. return arm_reserve_mmu();
  110. }
  111. __weak int arm_reserve_mmu(void)
  112. {
  113. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  114. /* reserve TLB table */
  115. gd->arch.tlb_size = PGTABLE_SIZE;
  116. gd->relocaddr -= gd->arch.tlb_size;
  117. /* round down to next 64 kB limit */
  118. gd->relocaddr &= ~(0x10000 - 1);
  119. gd->arch.tlb_addr = gd->relocaddr;
  120. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  121. gd->arch.tlb_addr + gd->arch.tlb_size);
  122. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  123. /*
  124. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  125. * with location within secure ram.
  126. */
  127. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  128. #endif
  129. #endif
  130. return 0;
  131. }