cache-cp15.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <log.h>
  9. #include <asm/system.h>
  10. #include <asm/cache.h>
  11. #include <linux/compiler.h>
  12. #include <asm/armv7_mpu.h>
  13. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #ifdef CONFIG_SYS_ARM_MMU
  16. __weak void arm_init_before_mmu(void)
  17. {
  18. }
  19. __weak void arm_init_domains(void)
  20. {
  21. }
  22. void set_section_dcache(int section, enum dcache_option option)
  23. {
  24. #ifdef CONFIG_ARMV7_LPAE
  25. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  26. /* Need to set the access flag to not fault */
  27. u64 value = TTB_SECT_AP | TTB_SECT_AF;
  28. #else
  29. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  30. u32 value = TTB_SECT_AP;
  31. #endif
  32. /* Add the page offset */
  33. value |= ((u32)section << MMU_SECTION_SHIFT);
  34. /* Add caching bits */
  35. value |= option;
  36. /* Set PTE */
  37. page_table[section] = value;
  38. }
  39. __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  40. {
  41. debug("%s: Warning: not implemented\n", __func__);
  42. }
  43. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  44. enum dcache_option option)
  45. {
  46. #ifdef CONFIG_ARMV7_LPAE
  47. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  48. #else
  49. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  50. #endif
  51. unsigned long startpt, stoppt;
  52. unsigned long upto, end;
  53. /* div by 2 before start + size to avoid phys_addr_t overflow */
  54. end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
  55. >> (MMU_SECTION_SHIFT - 1);
  56. start = start >> MMU_SECTION_SHIFT;
  57. #ifdef CONFIG_ARMV7_LPAE
  58. debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
  59. option);
  60. #else
  61. debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  62. option);
  63. #endif
  64. for (upto = start; upto < end; upto++)
  65. set_section_dcache(upto, option);
  66. /*
  67. * Make sure range is cache line aligned
  68. * Only CPU maintains page tables, hence it is safe to always
  69. * flush complete cache lines...
  70. */
  71. startpt = (unsigned long)&page_table[start];
  72. startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  73. stoppt = (unsigned long)&page_table[end];
  74. stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  75. mmu_page_table_flush(startpt, stoppt);
  76. }
  77. __weak void dram_bank_mmu_setup(int bank)
  78. {
  79. bd_t *bd = gd->bd;
  80. int i;
  81. /* bd->bi_dram is available only after relocation */
  82. if ((gd->flags & GD_FLG_RELOC) == 0)
  83. return;
  84. debug("%s: bank: %d\n", __func__, bank);
  85. for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  86. i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  87. (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
  88. i++)
  89. set_section_dcache(i, DCACHE_DEFAULT_OPTION);
  90. }
  91. /* to activate the MMU we need to set up virtual memory: use 1M areas */
  92. static inline void mmu_setup(void)
  93. {
  94. int i;
  95. u32 reg;
  96. arm_init_before_mmu();
  97. /* Set up an identity-mapping for all 4GB, rw for everyone */
  98. for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
  99. set_section_dcache(i, DCACHE_OFF);
  100. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  101. dram_bank_mmu_setup(i);
  102. }
  103. #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
  104. /* Set up 4 PTE entries pointing to our 4 1GB page tables */
  105. for (i = 0; i < 4; i++) {
  106. u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
  107. u64 tpt = gd->arch.tlb_addr + (4096 * i);
  108. page_table[i] = tpt | TTB_PAGETABLE;
  109. }
  110. reg = TTBCR_EAE;
  111. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  112. reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
  113. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  114. reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
  115. #else
  116. reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
  117. #endif
  118. if (is_hyp()) {
  119. /* Set HTCR to enable LPAE */
  120. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  121. : : "r" (reg) : "memory");
  122. /* Set HTTBR0 */
  123. asm volatile("mcrr p15, 4, %0, %1, c2"
  124. :
  125. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  126. : "memory");
  127. /* Set HMAIR */
  128. asm volatile("mcr p15, 4, %0, c10, c2, 0"
  129. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  130. } else {
  131. /* Set TTBCR to enable LPAE */
  132. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  133. : : "r" (reg) : "memory");
  134. /* Set 64-bit TTBR0 */
  135. asm volatile("mcrr p15, 0, %0, %1, c2"
  136. :
  137. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  138. : "memory");
  139. /* Set MAIR */
  140. asm volatile("mcr p15, 0, %0, c10, c2, 0"
  141. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  142. }
  143. #elif defined(CONFIG_CPU_V7A)
  144. if (is_hyp()) {
  145. /* Set HTCR to disable LPAE */
  146. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  147. : : "r" (0) : "memory");
  148. } else {
  149. /* Set TTBCR to disable LPAE */
  150. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  151. : : "r" (0) : "memory");
  152. }
  153. /* Set TTBR0 */
  154. reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
  155. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  156. reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
  157. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  158. reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
  159. #else
  160. reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
  161. #endif
  162. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  163. : : "r" (reg) : "memory");
  164. #else
  165. /* Copy the page table address to cp15 */
  166. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  167. : : "r" (gd->arch.tlb_addr) : "memory");
  168. #endif
  169. /* Set the access control to all-supervisor */
  170. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  171. : : "r" (~0));
  172. arm_init_domains();
  173. /* and enable the mmu */
  174. reg = get_cr(); /* get control reg. */
  175. set_cr(reg | CR_M);
  176. }
  177. static int mmu_enabled(void)
  178. {
  179. return get_cr() & CR_M;
  180. }
  181. #endif /* CONFIG_SYS_ARM_MMU */
  182. /* cache_bit must be either CR_I or CR_C */
  183. static void cache_enable(uint32_t cache_bit)
  184. {
  185. uint32_t reg;
  186. /* The data cache is not active unless the mmu/mpu is enabled too */
  187. #ifdef CONFIG_SYS_ARM_MMU
  188. if ((cache_bit == CR_C) && !mmu_enabled())
  189. mmu_setup();
  190. #elif defined(CONFIG_SYS_ARM_MPU)
  191. if ((cache_bit == CR_C) && !mpu_enabled()) {
  192. printf("Consider enabling MPU before enabling caches\n");
  193. return;
  194. }
  195. #endif
  196. reg = get_cr(); /* get control reg. */
  197. set_cr(reg | cache_bit);
  198. }
  199. /* cache_bit must be either CR_I or CR_C */
  200. static void cache_disable(uint32_t cache_bit)
  201. {
  202. uint32_t reg;
  203. reg = get_cr();
  204. if (cache_bit == CR_C) {
  205. /* if cache isn;t enabled no need to disable */
  206. if ((reg & CR_C) != CR_C)
  207. return;
  208. #ifdef CONFIG_SYS_ARM_MMU
  209. /* if disabling data cache, disable mmu too */
  210. cache_bit |= CR_M;
  211. #endif
  212. }
  213. reg = get_cr();
  214. #ifdef CONFIG_SYS_ARM_MMU
  215. if (cache_bit == (CR_C | CR_M))
  216. #elif defined(CONFIG_SYS_ARM_MPU)
  217. if (cache_bit == CR_C)
  218. #endif
  219. flush_dcache_all();
  220. set_cr(reg & ~cache_bit);
  221. }
  222. #endif
  223. #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  224. void icache_enable(void)
  225. {
  226. return;
  227. }
  228. void icache_disable(void)
  229. {
  230. return;
  231. }
  232. int icache_status(void)
  233. {
  234. return 0; /* always off */
  235. }
  236. #else
  237. void icache_enable(void)
  238. {
  239. cache_enable(CR_I);
  240. }
  241. void icache_disable(void)
  242. {
  243. cache_disable(CR_I);
  244. }
  245. int icache_status(void)
  246. {
  247. return (get_cr() & CR_I) != 0;
  248. }
  249. #endif
  250. #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  251. void dcache_enable(void)
  252. {
  253. return;
  254. }
  255. void dcache_disable(void)
  256. {
  257. return;
  258. }
  259. int dcache_status(void)
  260. {
  261. return 0; /* always off */
  262. }
  263. #else
  264. void dcache_enable(void)
  265. {
  266. cache_enable(CR_C);
  267. }
  268. void dcache_disable(void)
  269. {
  270. cache_disable(CR_C);
  271. }
  272. int dcache_status(void)
  273. {
  274. return (get_cr() & CR_C) != 0;
  275. }
  276. #endif