system.h 19 KB

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  1. #ifndef __ASM_ARM_SYSTEM_H
  2. #define __ASM_ARM_SYSTEM_H
  3. #include <linux/compiler.h>
  4. #include <asm/barriers.h>
  5. #ifdef CONFIG_ARM64
  6. /*
  7. * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
  8. */
  9. #define CR_M (1 << 0) /* MMU enable */
  10. #define CR_A (1 << 1) /* Alignment abort enable */
  11. #define CR_C (1 << 2) /* Dcache enable */
  12. #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
  13. #define CR_I (1 << 12) /* Icache enable */
  14. #define CR_WXN (1 << 19) /* Write Permision Imply XN */
  15. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  16. #define ES_TO_AARCH64 1
  17. #define ES_TO_AARCH32 0
  18. /*
  19. * SCR_EL3 bits definitions
  20. */
  21. #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
  22. #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
  23. #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
  24. #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
  25. #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
  26. #define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
  27. #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
  28. /*
  29. * SPSR_EL3/SPSR_EL2 bits definitions
  30. */
  31. #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
  32. #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
  33. #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
  34. #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
  35. #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
  36. #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
  37. #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
  38. #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
  39. #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
  40. #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
  41. #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
  42. #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
  43. #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
  44. /*
  45. * CPTR_EL2 bits definitions
  46. */
  47. #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
  48. /*
  49. * SCTLR_EL2 bits definitions
  50. */
  51. #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
  52. 1 << 11 | 3 << 4) /* Reserved, RES1 */
  53. #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
  54. #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
  55. #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
  56. #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
  57. #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
  58. #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
  59. #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
  60. /*
  61. * CNTHCTL_EL2 bits definitions
  62. */
  63. #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
  64. #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
  65. /*
  66. * HCR_EL2 bits definitions
  67. */
  68. #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
  69. #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
  70. #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
  71. /*
  72. * CPACR_EL1 bits definitions
  73. */
  74. #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
  75. /*
  76. * SCTLR_EL1 bits definitions
  77. */
  78. #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
  79. 1 << 11) /* Reserved, RES1 */
  80. #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
  81. #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
  82. #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
  83. #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
  84. #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
  85. #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
  86. #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
  87. #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
  88. #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
  89. #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
  90. #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
  91. #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
  92. #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
  93. #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
  94. #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
  95. #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
  96. #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
  97. #ifndef __ASSEMBLY__
  98. struct pt_regs;
  99. u64 get_page_table_size(void);
  100. #define PGTABLE_SIZE get_page_table_size()
  101. /* 2MB granularity */
  102. #define MMU_SECTION_SHIFT 21
  103. #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
  104. /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
  105. enum dcache_option {
  106. DCACHE_OFF = 0 << 2,
  107. DCACHE_WRITETHROUGH = 3 << 2,
  108. DCACHE_WRITEBACK = 4 << 2,
  109. DCACHE_WRITEALLOC = 4 << 2,
  110. };
  111. #define wfi() \
  112. ({asm volatile( \
  113. "wfi" : : : "memory"); \
  114. })
  115. static inline unsigned int current_el(void)
  116. {
  117. unsigned int el;
  118. asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
  119. return el >> 2;
  120. }
  121. static inline unsigned int get_sctlr(void)
  122. {
  123. unsigned int el, val;
  124. el = current_el();
  125. if (el == 1)
  126. asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
  127. else if (el == 2)
  128. asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
  129. else
  130. asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
  131. return val;
  132. }
  133. static inline void set_sctlr(unsigned int val)
  134. {
  135. unsigned int el;
  136. el = current_el();
  137. if (el == 1)
  138. asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
  139. else if (el == 2)
  140. asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
  141. else
  142. asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
  143. asm volatile("isb");
  144. }
  145. static inline unsigned long read_mpidr(void)
  146. {
  147. unsigned long val;
  148. asm volatile("mrs %0, mpidr_el1" : "=r" (val));
  149. return val;
  150. }
  151. #define BSP_COREID 0
  152. void __asm_flush_dcache_all(void);
  153. void __asm_invalidate_dcache_all(void);
  154. void __asm_flush_dcache_range(u64 start, u64 end);
  155. /**
  156. * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
  157. *
  158. * This performance an invalidate from @start to @end - 1. Both addresses
  159. * should be cache-aligned, otherwise this function will align the start
  160. * address and may continue past the end address.
  161. *
  162. * Data in the address range is evicted from the cache and is not written back
  163. * to memory.
  164. *
  165. * @start: Start address to invalidate
  166. * @end: End address to invalidate up to (exclusive)
  167. */
  168. void __asm_invalidate_dcache_range(u64 start, u64 end);
  169. void __asm_invalidate_tlb_all(void);
  170. void __asm_invalidate_icache_all(void);
  171. int __asm_invalidate_l3_dcache(void);
  172. int __asm_flush_l3_dcache(void);
  173. int __asm_invalidate_l3_icache(void);
  174. void __asm_switch_ttbr(u64 new_ttbr);
  175. /*
  176. * Switch from EL3 to EL2 for ARMv8
  177. *
  178. * @args: For loading 64-bit OS, fdt address.
  179. * For loading 32-bit OS, zero.
  180. * @mach_nr: For loading 64-bit OS, zero.
  181. * For loading 32-bit OS, machine nr
  182. * @fdt_addr: For loading 64-bit OS, zero.
  183. * For loading 32-bit OS, fdt address.
  184. * @arg4: Input argument.
  185. * @entry_point: kernel entry point
  186. * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
  187. */
  188. void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
  189. u64 arg4, u64 entry_point, u64 es_flag);
  190. /*
  191. * Switch from EL2 to EL1 for ARMv8
  192. *
  193. * @args: For loading 64-bit OS, fdt address.
  194. * For loading 32-bit OS, zero.
  195. * @mach_nr: For loading 64-bit OS, zero.
  196. * For loading 32-bit OS, machine nr
  197. * @fdt_addr: For loading 64-bit OS, zero.
  198. * For loading 32-bit OS, fdt address.
  199. * @arg4: Input argument.
  200. * @entry_point: kernel entry point
  201. * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
  202. */
  203. void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
  204. u64 arg4, u64 entry_point, u64 es_flag);
  205. void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
  206. u64 arg4, u64 entry_point);
  207. void gic_init(void);
  208. void gic_send_sgi(unsigned long sgino);
  209. void wait_for_wakeup(void);
  210. void protect_secure_region(void);
  211. void smp_kick_all_cpus(void);
  212. void flush_l3_cache(void);
  213. void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
  214. /*
  215. *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
  216. * DEN0028A
  217. *
  218. * @args: input and output arguments
  219. *
  220. */
  221. void smc_call(struct pt_regs *args);
  222. void __noreturn psci_system_reset(void);
  223. void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
  224. void __noreturn psci_system_off(void);
  225. #ifdef CONFIG_ARMV8_PSCI
  226. extern char __secure_start[];
  227. extern char __secure_end[];
  228. extern char __secure_stack_start[];
  229. extern char __secure_stack_end[];
  230. void armv8_setup_psci(void);
  231. void psci_setup_vectors(void);
  232. void psci_arch_init(void);
  233. #endif
  234. #endif /* __ASSEMBLY__ */
  235. #else /* CONFIG_ARM64 */
  236. #ifdef __KERNEL__
  237. #define CPU_ARCH_UNKNOWN 0
  238. #define CPU_ARCH_ARMv3 1
  239. #define CPU_ARCH_ARMv4 2
  240. #define CPU_ARCH_ARMv4T 3
  241. #define CPU_ARCH_ARMv5 4
  242. #define CPU_ARCH_ARMv5T 5
  243. #define CPU_ARCH_ARMv5TE 6
  244. #define CPU_ARCH_ARMv5TEJ 7
  245. #define CPU_ARCH_ARMv6 8
  246. #define CPU_ARCH_ARMv7 9
  247. /*
  248. * CR1 bits (CP#15 CR1)
  249. */
  250. #define CR_M (1 << 0) /* MMU enable */
  251. #define CR_A (1 << 1) /* Alignment abort enable */
  252. #define CR_C (1 << 2) /* Dcache enable */
  253. #define CR_W (1 << 3) /* Write buffer enable */
  254. #define CR_P (1 << 4) /* 32-bit exception handler */
  255. #define CR_D (1 << 5) /* 32-bit data address range */
  256. #define CR_L (1 << 6) /* Implementation defined */
  257. #define CR_B (1 << 7) /* Big endian */
  258. #define CR_S (1 << 8) /* System MMU protection */
  259. #define CR_R (1 << 9) /* ROM MMU protection */
  260. #define CR_F (1 << 10) /* Implementation defined */
  261. #define CR_Z (1 << 11) /* Implementation defined */
  262. #define CR_I (1 << 12) /* Icache enable */
  263. #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
  264. #define CR_RR (1 << 14) /* Round Robin cache replacement */
  265. #define CR_L4 (1 << 15) /* LDR pc can set T bit */
  266. #define CR_DT (1 << 16)
  267. #define CR_IT (1 << 18)
  268. #define CR_ST (1 << 19)
  269. #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
  270. #define CR_U (1 << 22) /* Unaligned access operation */
  271. #define CR_XP (1 << 23) /* Extended page tables */
  272. #define CR_VE (1 << 24) /* Vectored interrupts */
  273. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  274. #define CR_TRE (1 << 28) /* TEX remap enable */
  275. #define CR_AFE (1 << 29) /* Access flag enable */
  276. #define CR_TE (1 << 30) /* Thumb exception enable */
  277. #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
  278. #define PGTABLE_SIZE (4096 * 5)
  279. #elif !defined(PGTABLE_SIZE)
  280. #define PGTABLE_SIZE (4096 * 4)
  281. #endif
  282. /*
  283. * This is used to ensure the compiler did actually allocate the register we
  284. * asked it for some inline assembly sequences. Apparently we can't trust
  285. * the compiler from one version to another so a bit of paranoia won't hurt.
  286. * This string is meant to be concatenated with the inline asm string and
  287. * will cause compilation to stop on mismatch.
  288. * (for details, see gcc PR 15089)
  289. */
  290. #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
  291. #ifndef __ASSEMBLY__
  292. #ifdef CONFIG_ARMV7_LPAE
  293. void switch_to_hypervisor_ret(void);
  294. #endif
  295. #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
  296. #ifdef __ARM_ARCH_7A__
  297. #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  298. #else
  299. #define wfi()
  300. #endif
  301. static inline unsigned long get_cpsr(void)
  302. {
  303. unsigned long cpsr;
  304. asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
  305. return cpsr;
  306. }
  307. static inline int is_hyp(void)
  308. {
  309. #ifdef CONFIG_ARMV7_LPAE
  310. /* HYP mode requires LPAE ... */
  311. return ((get_cpsr() & 0x1f) == 0x1a);
  312. #else
  313. /* ... so without LPAE support we can optimize all hyp code away */
  314. return 0;
  315. #endif
  316. }
  317. static inline unsigned int get_cr(void)
  318. {
  319. unsigned int val;
  320. if (is_hyp())
  321. asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
  322. :
  323. : "cc");
  324. else
  325. asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
  326. :
  327. : "cc");
  328. return val;
  329. }
  330. static inline void set_cr(unsigned int val)
  331. {
  332. if (is_hyp())
  333. asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
  334. : "r" (val)
  335. : "cc");
  336. else
  337. asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
  338. : "r" (val)
  339. : "cc");
  340. isb();
  341. }
  342. static inline unsigned int get_dacr(void)
  343. {
  344. unsigned int val;
  345. asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
  346. return val;
  347. }
  348. static inline void set_dacr(unsigned int val)
  349. {
  350. asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
  351. : : "r" (val) : "cc");
  352. isb();
  353. }
  354. #ifdef CONFIG_ARMV7_LPAE
  355. /* Long-Descriptor Translation Table Level 1/2 Bits */
  356. #define TTB_SECT_XN_MASK (1ULL << 54)
  357. #define TTB_SECT_NG_MASK (1 << 11)
  358. #define TTB_SECT_AF (1 << 10)
  359. #define TTB_SECT_SH_MASK (3 << 8)
  360. #define TTB_SECT_NS_MASK (1 << 5)
  361. #define TTB_SECT_AP (1 << 6)
  362. /* Note: TTB AP bits are set elsewhere */
  363. #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
  364. #define TTB_SECT (1 << 0)
  365. #define TTB_PAGETABLE (3 << 0)
  366. /* TTBCR flags */
  367. #define TTBCR_EAE (1 << 31)
  368. #define TTBCR_T0SZ(x) ((x) << 0)
  369. #define TTBCR_T1SZ(x) ((x) << 16)
  370. #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
  371. #define TTBCR_IRGN0_NC (0 << 8)
  372. #define TTBCR_IRGN0_WBWA (1 << 8)
  373. #define TTBCR_IRGN0_WT (2 << 8)
  374. #define TTBCR_IRGN0_WBNWA (3 << 8)
  375. #define TTBCR_IRGN0_MASK (3 << 8)
  376. #define TTBCR_ORGN0_NC (0 << 10)
  377. #define TTBCR_ORGN0_WBWA (1 << 10)
  378. #define TTBCR_ORGN0_WT (2 << 10)
  379. #define TTBCR_ORGN0_WBNWA (3 << 10)
  380. #define TTBCR_ORGN0_MASK (3 << 10)
  381. #define TTBCR_SHARED_NON (0 << 12)
  382. #define TTBCR_SHARED_OUTER (2 << 12)
  383. #define TTBCR_SHARED_INNER (3 << 12)
  384. #define TTBCR_EPD0 (0 << 7)
  385. /*
  386. * Memory types
  387. */
  388. #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
  389. (0xcc << (2 * 8)) | (0xff << (3 * 8)))
  390. /* options available for data cache on each page */
  391. enum dcache_option {
  392. DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
  393. DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
  394. DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
  395. DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
  396. };
  397. #elif defined(CONFIG_CPU_V7A)
  398. /* Short-Descriptor Translation Table Level 1 Bits */
  399. #define TTB_SECT_NS_MASK (1 << 19)
  400. #define TTB_SECT_NG_MASK (1 << 17)
  401. #define TTB_SECT_S_MASK (1 << 16)
  402. /* Note: TTB AP bits are set elsewhere */
  403. #define TTB_SECT_AP (3 << 10)
  404. #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
  405. #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
  406. #define TTB_SECT_XN_MASK (1 << 4)
  407. #define TTB_SECT_C_MASK (1 << 3)
  408. #define TTB_SECT_B_MASK (1 << 2)
  409. #define TTB_SECT (2 << 0)
  410. /* options available for data cache on each page */
  411. enum dcache_option {
  412. DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  413. DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
  414. DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
  415. DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
  416. };
  417. #else
  418. #define TTB_SECT_AP (3 << 10)
  419. /* options available for data cache on each page */
  420. enum dcache_option {
  421. DCACHE_OFF = 0x12,
  422. DCACHE_WRITETHROUGH = 0x1a,
  423. DCACHE_WRITEBACK = 0x1e,
  424. DCACHE_WRITEALLOC = 0x16,
  425. };
  426. #endif
  427. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  428. #define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
  429. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  430. #define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
  431. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
  432. #define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
  433. #endif
  434. /* Size of an MMU section */
  435. enum {
  436. #ifdef CONFIG_ARMV7_LPAE
  437. MMU_SECTION_SHIFT = 21, /* 2MB */
  438. #else
  439. MMU_SECTION_SHIFT = 20, /* 1MB */
  440. #endif
  441. MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
  442. };
  443. #ifdef CONFIG_CPU_V7A
  444. /* TTBR0 bits */
  445. #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
  446. #define TTBR0_RGN_NC (0 << 3)
  447. #define TTBR0_RGN_WBWA (1 << 3)
  448. #define TTBR0_RGN_WT (2 << 3)
  449. #define TTBR0_RGN_WB (3 << 3)
  450. /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
  451. #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
  452. #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
  453. #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
  454. #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
  455. #endif
  456. /**
  457. * Register an update to the page tables, and flush the TLB
  458. *
  459. * \param start start address of update in page table
  460. * \param stop stop address of update in page table
  461. */
  462. void mmu_page_table_flush(unsigned long start, unsigned long stop);
  463. #ifdef CONFIG_ARMV7_PSCI
  464. void psci_arch_cpu_entry(void);
  465. u32 psci_version(void);
  466. s32 psci_features(u32 function_id, u32 psci_fid);
  467. s32 psci_cpu_off(void);
  468. s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
  469. u32 context_id);
  470. s32 psci_affinity_info(u32 function_id, u32 target_affinity,
  471. u32 lowest_affinity_level);
  472. u32 psci_migrate_info_type(void);
  473. void psci_system_off(void);
  474. void psci_system_reset(void);
  475. s32 psci_features(u32 function_id, u32 psci_fid);
  476. #endif
  477. #endif /* __ASSEMBLY__ */
  478. #define arch_align_stack(x) (x)
  479. #endif /* __KERNEL__ */
  480. #endif /* CONFIG_ARM64 */
  481. #ifndef __ASSEMBLY__
  482. /**
  483. * save_boot_params() - Save boot parameters before starting reset sequence
  484. *
  485. * If you provide this function it will be called immediately U-Boot starts,
  486. * both for SPL and U-Boot proper.
  487. *
  488. * All registers are unchanged from U-Boot entry. No registers need be
  489. * preserved.
  490. *
  491. * This is not a normal C function. There is no stack. Return by branching to
  492. * save_boot_params_ret.
  493. *
  494. * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
  495. */
  496. /**
  497. * save_boot_params_ret() - Return from save_boot_params()
  498. *
  499. * If you provide save_boot_params(), then you should jump back to this
  500. * function when done. Try to preserve all registers.
  501. *
  502. * If your implementation of save_boot_params() is in C then it is acceptable
  503. * to simply call save_boot_params_ret() at the end of your function. Since
  504. * there is no link register set up, you cannot just exit the function. U-Boot
  505. * will return to the (initialised) value of lr, and likely crash/hang.
  506. *
  507. * If your implementation of save_boot_params() is in assembler then you
  508. * should use 'b' or 'bx' to return to save_boot_params_ret.
  509. */
  510. void save_boot_params_ret(void);
  511. /**
  512. * Change the cache settings for a region.
  513. *
  514. * \param start start address of memory region to change
  515. * \param size size of memory region to change
  516. * \param option dcache option to select
  517. */
  518. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  519. enum dcache_option option);
  520. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  521. void noncached_init(void);
  522. phys_addr_t noncached_alloc(size_t size, size_t align);
  523. #endif /* CONFIG_SYS_NONCACHED_MEMORY */
  524. #endif /* __ASSEMBLY__ */
  525. #endif