gic.h 3.2 KB

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  1. #ifndef __GIC_H__
  2. #define __GIC_H__
  3. /* Register offsets for the ARM generic interrupt controller (GIC) */
  4. #define GIC_DIST_OFFSET 0x1000
  5. #define GIC_CPU_OFFSET_A9 0x0100
  6. #define GIC_CPU_OFFSET_A15 0x2000
  7. /* Distributor Registers */
  8. #define GICD_CTLR 0x0000
  9. #define GICD_TYPER 0x0004
  10. #define GICD_IIDR 0x0008
  11. #define GICD_STATUSR 0x0010
  12. #define GICD_SETSPI_NSR 0x0040
  13. #define GICD_CLRSPI_NSR 0x0048
  14. #define GICD_SETSPI_SR 0x0050
  15. #define GICD_CLRSPI_SR 0x0058
  16. #define GICD_SEIR 0x0068
  17. #define GICD_IGROUPRn 0x0080
  18. #define GICD_ISENABLERn 0x0100
  19. #define GICD_ICENABLERn 0x0180
  20. #define GICD_ISPENDRn 0x0200
  21. #define GICD_ICPENDRn 0x0280
  22. #define GICD_ISACTIVERn 0x0300
  23. #define GICD_ICACTIVERn 0x0380
  24. #define GICD_IPRIORITYRn 0x0400
  25. #define GICD_ITARGETSRn 0x0800
  26. #define GICD_ICFGR 0x0c00
  27. #define GICD_IGROUPMODRn 0x0d00
  28. #define GICD_NSACRn 0x0e00
  29. #define GICD_SGIR 0x0f00
  30. #define GICD_CPENDSGIRn 0x0f10
  31. #define GICD_SPENDSGIRn 0x0f20
  32. #define GICD_IROUTERn 0x6000
  33. /* Cpu Interface Memory Mapped Registers */
  34. #define GICC_CTLR 0x0000
  35. #define GICC_PMR 0x0004
  36. #define GICC_BPR 0x0008
  37. #define GICC_IAR 0x000C
  38. #define GICC_EOIR 0x0010
  39. #define GICC_RPR 0x0014
  40. #define GICC_HPPIR 0x0018
  41. #define GICC_ABPR 0x001c
  42. #define GICC_AIAR 0x0020
  43. #define GICC_AEOIR 0x0024
  44. #define GICC_AHPPIR 0x0028
  45. #define GICC_APRn 0x00d0
  46. #define GICC_NSAPRn 0x00e0
  47. #define GICC_IIDR 0x00fc
  48. #define GICC_DIR 0x1000
  49. /* ReDistributor Registers for Control and Physical LPIs */
  50. #define GICR_CTLR 0x0000
  51. #define GICR_IIDR 0x0004
  52. #define GICR_TYPER 0x0008
  53. #define GICR_STATUSR 0x0010
  54. #define GICR_WAKER 0x0014
  55. #define GICR_SETLPIR 0x0040
  56. #define GICR_CLRLPIR 0x0048
  57. #define GICR_SEIR 0x0068
  58. #define GICR_PROPBASER 0x0070
  59. #define GICR_PENDBASER 0x0078
  60. #define GICR_INVLPIR 0x00a0
  61. #define GICR_INVALLR 0x00b0
  62. #define GICR_SYNCR 0x00c0
  63. #define GICR_MOVLPIR 0x0100
  64. #define GICR_MOVALLR 0x0110
  65. /* ReDistributor Registers for SGIs and PPIs */
  66. #define GICR_IGROUPRn 0x0080
  67. #define GICR_ISENABLERn 0x0100
  68. #define GICR_ICENABLERn 0x0180
  69. #define GICR_ISPENDRn 0x0200
  70. #define GICR_ICPENDRn 0x0280
  71. #define GICR_ISACTIVERn 0x0300
  72. #define GICR_ICACTIVERn 0x0380
  73. #define GICR_IPRIORITYRn 0x0400
  74. #define GICR_ICFGR0 0x0c00
  75. #define GICR_ICFGR1 0x0c04
  76. #define GICR_IGROUPMODRn 0x0d00
  77. #define GICR_NSACRn 0x0e00
  78. /* Cpu Interface System Registers */
  79. #define ICC_IAR0_EL1 S3_0_C12_C8_0
  80. #define ICC_IAR1_EL1 S3_0_C12_C12_0
  81. #define ICC_EOIR0_EL1 S3_0_C12_C8_1
  82. #define ICC_EOIR1_EL1 S3_0_C12_C12_1
  83. #define ICC_HPPIR0_EL1 S3_0_C12_C8_2
  84. #define ICC_HPPIR1_EL1 S3_0_C12_C12_2
  85. #define ICC_BPR0_EL1 S3_0_C12_C8_3
  86. #define ICC_BPR1_EL1 S3_0_C12_C12_3
  87. #define ICC_DIR_EL1 S3_0_C12_C11_1
  88. #define ICC_PMR_EL1 S3_0_C4_C6_0
  89. #define ICC_RPR_EL1 S3_0_C12_C11_3
  90. #define ICC_CTLR_EL1 S3_0_C12_C12_4
  91. #define ICC_CTLR_EL3 S3_6_C12_C12_4
  92. #define ICC_SRE_EL1 S3_0_C12_C12_5
  93. #define ICC_SRE_EL2 S3_4_C12_C9_5
  94. #define ICC_SRE_EL3 S3_6_C12_C12_5
  95. #define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
  96. #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
  97. #define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
  98. #define ICC_SEIEN_EL1 S3_0_C12_C13_0
  99. #define ICC_SGI0R_EL1 S3_0_C12_C11_7
  100. #define ICC_SGI1R_EL1 S3_0_C12_C11_5
  101. #define ICC_ASGI1R_EL1 S3_0_C12_C11_6
  102. #endif /* __GIC_H__ */