crm_regs.h 8.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
  6. #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
  7. #ifndef __ASSEMBLY__
  8. #include <linux/types.h>
  9. /* Clock Controller Module (CCM) */
  10. struct ccm_reg {
  11. u32 ccr;
  12. u32 csr;
  13. u32 ccsr;
  14. u32 cacrr;
  15. u32 cscmr1;
  16. u32 cscdr1;
  17. u32 cscdr2;
  18. u32 cscdr3;
  19. u32 cscmr2;
  20. u32 cscdr4;
  21. u32 ctor;
  22. u32 clpcr;
  23. u32 cisr;
  24. u32 cimr;
  25. u32 ccosr;
  26. u32 cgpr;
  27. u32 ccgr0;
  28. u32 ccgr1;
  29. u32 ccgr2;
  30. u32 ccgr3;
  31. u32 ccgr4;
  32. u32 ccgr5;
  33. u32 ccgr6;
  34. u32 ccgr7;
  35. u32 ccgr8;
  36. u32 ccgr9;
  37. u32 ccgr10;
  38. u32 ccgr11;
  39. u32 cmeor0;
  40. u32 cmeor1;
  41. u32 cmeor2;
  42. u32 cmeor3;
  43. u32 cmeor4;
  44. u32 cmeor5;
  45. u32 cppdsr;
  46. u32 ccowr;
  47. u32 ccpgr0;
  48. u32 ccpgr1;
  49. u32 ccpgr2;
  50. u32 ccpgr3;
  51. };
  52. /* Analog components control digital interface (ANADIG) */
  53. struct anadig_reg {
  54. u32 reserved_0x000[4];
  55. u32 pll3_ctrl;
  56. u32 reserved_0x014[3];
  57. u32 pll7_ctrl;
  58. u32 reserved_0x024[3];
  59. u32 pll2_ctrl;
  60. u32 reserved_0x034[3];
  61. u32 pll2_ss;
  62. u32 reserved_0x044[3];
  63. u32 pll2_num;
  64. u32 reserved_0x054[3];
  65. u32 pll2_denom;
  66. u32 reserved_0x064[3];
  67. u32 pll4_ctrl;
  68. u32 reserved_0x074[3];
  69. u32 pll4_num;
  70. u32 reserved_0x084[3];
  71. u32 pll4_denom;
  72. u32 reserved_0x094[3];
  73. u32 pll6_ctrl;
  74. u32 reserved_0x0A4[3];
  75. u32 pll6_num;
  76. u32 reserved_0x0B4[3];
  77. u32 pll6_denom;
  78. u32 reserved_0x0C4[7];
  79. u32 pll5_ctrl;
  80. u32 reserved_0x0E4[3];
  81. u32 pll3_pfd;
  82. u32 reserved_0x0F4[3];
  83. u32 pll2_pfd;
  84. u32 reserved_0x104[3];
  85. u32 reg_1p1;
  86. u32 reserved_0x114[3];
  87. u32 reg_3p0;
  88. u32 reserved_0x124[3];
  89. u32 reg_2p5;
  90. u32 reserved_0x134[7];
  91. u32 ana_misc0;
  92. u32 reserved_0x154[3];
  93. u32 ana_misc1;
  94. u32 reserved_0x164[63];
  95. u32 anadig_digprog;
  96. u32 reserved_0x264[3];
  97. u32 pll1_ctrl;
  98. u32 reserved_0x274[3];
  99. u32 pll1_ss;
  100. u32 reserved_0x284[3];
  101. u32 pll1_num;
  102. u32 reserved_0x294[3];
  103. u32 pll1_denom;
  104. u32 reserved_0x2A4[3];
  105. u32 pll1_pdf;
  106. u32 reserved_0x2B4[3];
  107. u32 pll_lock;
  108. };
  109. #endif
  110. #define CCM_CCR_FIRC_EN (1 << 16)
  111. #define CCM_CCR_OSCNT_MASK 0xff
  112. #define CCM_CCR_OSCNT(v) ((v) & 0xff)
  113. #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
  114. #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
  115. #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
  116. #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
  117. #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
  118. #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
  119. #define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
  120. #define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
  121. #define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
  122. #define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
  123. #define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
  124. #define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
  125. #define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
  126. #define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
  127. #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
  128. #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
  129. #define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
  130. #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
  131. #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
  132. #define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
  133. #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
  134. #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
  135. #define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
  136. #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
  137. #define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
  138. #define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
  139. #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
  140. #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
  141. #define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
  142. #define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28)
  143. #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
  144. #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
  145. #define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
  146. #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
  147. #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
  148. #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
  149. #define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12
  150. #define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12)
  151. #define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12)
  152. #define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
  153. #define CCM_CSCDR2_NFC_EN (1 << 9)
  154. #define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13)
  155. #define CCM_CSCDR2_NFC_CLK_INV (1 << 14)
  156. #define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4
  157. #define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4)
  158. #define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4)
  159. #define CCM_CSCDR2_ESDHC1_EN (1 << 29)
  160. #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
  161. #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
  162. #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
  163. #define CCM_CSCDR3_DCU1_EN (1 << 23)
  164. #define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
  165. #define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
  166. #define CCM_CSCDR3_DCU0_EN (1 << 19)
  167. #define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
  168. #define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
  169. #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
  170. #define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
  171. #define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
  172. #define CCM_CSCDR3_QSPI0_EN (1 << 4)
  173. #define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
  174. #define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
  175. #define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
  176. #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
  177. #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
  178. #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
  179. #define CCM_REG_CTRL_MASK 0xffffffff
  180. #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
  181. #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
  182. #define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18)
  183. #define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
  184. #define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
  185. #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
  186. #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
  187. #define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
  188. #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
  189. #define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
  190. #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
  191. #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
  192. #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
  193. #define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
  194. #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
  195. #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
  196. #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
  197. #define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
  198. #define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
  199. #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
  200. #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
  201. #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
  202. #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
  203. #define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14)
  204. #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
  205. #define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
  206. #define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
  207. #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
  208. #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
  209. #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
  210. #define CCM_CCGR9_FEC0_CTRL_MASK 0x3
  211. #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
  212. #define CCM_CCGR10_NFC_CTRL_MASK 0x3
  213. #define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12)
  214. #define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14)
  215. #define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
  216. #define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
  217. #define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12)
  218. #define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
  219. #define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
  220. #define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
  221. #define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
  222. #define ANADIG_PLL5_CTRL_DIV_SELECT 1
  223. #define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
  224. #define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
  225. #define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12)
  226. #define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
  227. #define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
  228. #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
  229. #define ANADIG_PLL2_CTRL_DIV_SELECT 1
  230. #define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
  231. #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
  232. #define ANADIG_PLL1_CTRL_DIV_SELECT 1
  233. #define FASE_CLK_FREQ 24000000
  234. #define SLOW_CLK_FREQ 32000
  235. #define PLL1_PFD1_FREQ 500000000
  236. #define PLL1_PFD2_FREQ 452000000
  237. #define PLL1_PFD3_FREQ 396000000
  238. #define PLL1_PFD4_FREQ 528000000
  239. #define PLL1_MAIN_FREQ 528000000
  240. #define PLL2_PFD1_FREQ 500000000
  241. #define PLL2_PFD2_FREQ 396000000
  242. #define PLL2_PFD3_FREQ 339000000
  243. #define PLL2_PFD4_FREQ 413000000
  244. #define PLL2_MAIN_FREQ 528000000
  245. #define PLL3_MAIN_FREQ 480000000
  246. #define PLL3_PFD3_FREQ 298000000
  247. #define PLL5_MAIN_FREQ 500000000
  248. #define ENET_EXTERNAL_CLK 50000000
  249. #define AUDIO_EXTERNAL_CLK 24576000
  250. #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */