flow.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _TEGRA210_FLOW_H_
  7. #define _TEGRA210_FLOW_H_
  8. struct flow_ctlr {
  9. u32 halt_cpu_events; /* offset 0x00 */
  10. u32 halt_cop_events; /* offset 0x04 */
  11. u32 cpu_csr; /* offset 0x08 */
  12. u32 cop_csr; /* offset 0x0c */
  13. u32 xrq_events; /* offset 0x10 */
  14. u32 halt_cpu1_events; /* offset 0x14 */
  15. u32 cpu1_csr; /* offset 0x18 */
  16. u32 halt_cpu2_events; /* offset 0x1c */
  17. u32 cpu2_csr; /* offset 0x20 */
  18. u32 halt_cpu3_events; /* offset 0x24 */
  19. u32 cpu3_csr; /* offset 0x28 */
  20. u32 cluster_control; /* offset 0x2c */
  21. u32 halt_cop1_events; /* offset 0x30 */
  22. u32 halt_cop1_csr; /* offset 0x34 */
  23. u32 cpu_pwr_csr; /* offset 0x38 */
  24. u32 mpid; /* offset 0x3c */
  25. u32 ram_repair; /* offset 0x40 */
  26. };
  27. /* HALT_COP_EVENTS_0, 0x04 */
  28. #define EVENT_MSEC (1 << 24)
  29. #define EVENT_USEC (1 << 25)
  30. #define EVENT_JTAG (1 << 28)
  31. #define EVENT_MODE_STOP (2 << 29)
  32. /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
  33. #define ACTIVE_LP (1 << 0)
  34. /* CPUn_CSR_0 */
  35. #define CSR_ENABLE (1 << 0)
  36. #define CSR_IMMEDIATE_WAKE (1 << 3)
  37. #define CSR_WAIT_WFI_SHIFT 8
  38. #endif /* _TEGRA210_FLOW_H_ */