sci.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #ifndef _SC_SCI_H
  6. #define _SC_SCI_H
  7. #include <log.h>
  8. #include <asm/arch/sci/types.h>
  9. #include <asm/arch/sci/svc/misc/api.h>
  10. #include <asm/arch/sci/svc/pad/api.h>
  11. #include <asm/arch/sci/svc/pm/api.h>
  12. #include <asm/arch/sci/svc/rm/api.h>
  13. #include <asm/arch/sci/svc/seco/api.h>
  14. #include <asm/arch/sci/rpc.h>
  15. #include <dt-bindings/soc/imx_rsrc.h>
  16. #include <linux/errno.h>
  17. static inline int sc_err_to_linux(sc_err_t err)
  18. {
  19. int ret;
  20. switch (err) {
  21. case SC_ERR_NONE:
  22. return 0;
  23. case SC_ERR_VERSION:
  24. case SC_ERR_CONFIG:
  25. case SC_ERR_PARM:
  26. ret = -EINVAL;
  27. break;
  28. case SC_ERR_NOACCESS:
  29. case SC_ERR_LOCKED:
  30. case SC_ERR_UNAVAILABLE:
  31. ret = -EACCES;
  32. break;
  33. case SC_ERR_NOTFOUND:
  34. case SC_ERR_NOPOWER:
  35. ret = -ENODEV;
  36. break;
  37. case SC_ERR_IPC:
  38. ret = -EIO;
  39. break;
  40. case SC_ERR_BUSY:
  41. ret = -EBUSY;
  42. break;
  43. case SC_ERR_FAIL:
  44. ret = -EIO;
  45. break;
  46. default:
  47. ret = 0;
  48. break;
  49. }
  50. debug("%s %d %d\n", __func__, err, ret);
  51. return ret;
  52. }
  53. /* PM API*/
  54. int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
  55. sc_pm_power_mode_t mode);
  56. int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
  57. sc_pm_power_mode_t *mode);
  58. int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
  59. sc_pm_clock_rate_t *rate);
  60. int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
  61. sc_pm_clock_rate_t *rate);
  62. int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
  63. sc_bool_t enable, sc_bool_t autog);
  64. int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
  65. sc_pm_clk_parent_t parent);
  66. int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
  67. sc_faddr_t address);
  68. sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
  69. int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
  70. /* MISC API */
  71. int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
  72. sc_ctrl_t ctrl, u32 val);
  73. int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
  74. u32 *val);
  75. void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
  76. void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
  77. void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
  78. int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
  79. int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
  80. s16 *celsius, s8 *tenths);
  81. /* RM API */
  82. sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
  83. int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
  84. sc_faddr_t addr_end);
  85. int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
  86. sc_rm_pt_t pt, sc_rm_perm_t perm);
  87. int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
  88. sc_faddr_t *addr_end);
  89. sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
  90. int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
  91. sc_bool_t isolated, sc_bool_t restricted,
  92. sc_bool_t grant, sc_bool_t coherent);
  93. int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
  94. int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
  95. int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
  96. int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
  97. int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
  98. sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
  99. int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
  100. sc_rm_pt_t *pt);
  101. /* PAD API */
  102. int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
  103. int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
  104. /* SMMU API */
  105. int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
  106. /* SECO API */
  107. int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
  108. sc_faddr_t addr);
  109. int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
  110. int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
  111. u32 *uid_h);
  112. void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
  113. int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
  114. int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
  115. sc_faddr_t export_addr, u16 max_size);
  116. int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
  117. int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
  118. int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
  119. u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
  120. int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
  121. int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
  122. u32 *data0, u32 *data1, u32 *data2, u32 *data3,
  123. u32 *data4, u8 size);
  124. #endif