pinmux.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Linaro.
  4. * Peter Griffin <peter.griffin@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <fdtdec.h>
  8. #include <log.h>
  9. #include <asm/gpio.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/pinmux.h>
  12. struct hi6220_pinmux0_regs *pmx0 =
  13. (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
  14. struct hi6220_pinmux1_regs *pmx1 =
  15. (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
  16. static void hi6220_uart_config(int peripheral)
  17. {
  18. switch (peripheral) {
  19. case PERIPH_ID_UART0:
  20. writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
  21. writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
  22. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
  23. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
  24. break;
  25. case PERIPH_ID_UART1:
  26. writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
  27. writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
  28. writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
  29. writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
  30. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
  31. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
  32. writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
  33. writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
  34. break;
  35. case PERIPH_ID_UART2:
  36. writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
  37. writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
  38. writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
  39. writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
  40. writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
  41. writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
  42. writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
  43. writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
  44. break;
  45. case PERIPH_ID_UART3:
  46. writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
  47. writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
  48. writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
  49. writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
  50. /* UART3_TXD */
  51. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
  52. /* UART3_RTS_N */
  53. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
  54. /* UART3_RXD */
  55. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
  56. /* UART3_TXD */
  57. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
  58. break;
  59. case PERIPH_ID_UART4:
  60. writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
  61. writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
  62. writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
  63. writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
  64. /* UART4_CTS_N */
  65. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
  66. /* UART4_RTS_N */
  67. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
  68. /* UART4_RXD */
  69. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
  70. /* UART4_TXD */
  71. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
  72. break;
  73. case PERIPH_ID_UART5:
  74. writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
  75. writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
  76. /* UART5_RXD */
  77. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
  78. /* UART5_TXD */
  79. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
  80. break;
  81. default:
  82. debug("%s: invalid peripheral %d", __func__, peripheral);
  83. return;
  84. }
  85. }
  86. static int hi6220_mmc_config(int peripheral)
  87. {
  88. u32 tmp;
  89. switch (peripheral) {
  90. case PERIPH_ID_SDMMC0:
  91. /* eMMC pinmux config */
  92. writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
  93. writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
  94. writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
  95. writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
  96. writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
  97. writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
  98. writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
  99. writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
  100. writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
  101. writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
  102. /*eMMC configure up/down/drive */
  103. writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
  104. tmp = DRIVE1_04MA | PULL_UP;
  105. writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
  106. writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
  107. writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
  108. writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
  109. writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
  110. writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
  111. writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
  112. writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
  113. writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
  114. writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
  115. break;
  116. case PERIPH_ID_SDMMC1:
  117. writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
  118. writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
  119. writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
  120. writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
  121. writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
  122. writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
  123. writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
  124. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
  125. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
  126. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
  127. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
  128. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
  129. break;
  130. default:
  131. debug("%s: invalid peripheral %d", __func__, peripheral);
  132. return -1;
  133. }
  134. return 0;
  135. }
  136. int hi6220_pinmux_config(int peripheral)
  137. {
  138. switch (peripheral) {
  139. case PERIPH_ID_UART0:
  140. case PERIPH_ID_UART1:
  141. case PERIPH_ID_UART2:
  142. case PERIPH_ID_UART3:
  143. hi6220_uart_config(peripheral);
  144. break;
  145. case PERIPH_ID_SDMMC0:
  146. case PERIPH_ID_SDMMC1:
  147. return hi6220_mmc_config(peripheral);
  148. default:
  149. debug("%s: invalid peripheral %d", __func__, peripheral);
  150. return -1;
  151. }
  152. return 0;
  153. }