soc.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <fsl_immap.h>
  11. #include <fsl_ifc.h>
  12. #include <init.h>
  13. #include <linux/sizes.h>
  14. #include <log.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/cache.h>
  18. #include <asm/io.h>
  19. #include <asm/global_data.h>
  20. #include <asm/arch-fsl-layerscape/config.h>
  21. #include <asm/arch-fsl-layerscape/ns_access.h>
  22. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  23. #include <asm/gic-v3.h>
  24. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  25. #include <fsl_csu.h>
  26. #endif
  27. #ifdef CONFIG_SYS_FSL_DDR
  28. #include <fsl_ddr_sdram.h>
  29. #include <fsl_ddr.h>
  30. #endif
  31. #ifdef CONFIG_CHAIN_OF_TRUST
  32. #include <fsl_validate.h>
  33. #endif
  34. #include <fsl_immap.h>
  35. #ifdef CONFIG_TFABOOT
  36. #include <env_internal.h>
  37. #endif
  38. #if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #endif
  41. #ifdef CONFIG_GIC_V3_ITS
  42. #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
  43. #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
  44. #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
  45. PROPTABLE_MAX_SZ, SZ_1M)
  46. static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
  47. {
  48. u32 phandle;
  49. int err;
  50. struct fdt_memory gic_rd_tables;
  51. gic_rd_tables.start = base;
  52. gic_rd_tables.end = base + size - 1;
  53. err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
  54. &phandle);
  55. if (err < 0)
  56. debug("%s: failed to add reserved memory: %d\n", __func__, err);
  57. return err;
  58. }
  59. int ls_gic_rd_tables_init(void *blob)
  60. {
  61. u64 gic_lpi_base;
  62. int ret;
  63. gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
  64. ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
  65. if (ret)
  66. return ret;
  67. ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
  68. if (ret)
  69. debug("%s: failed to init gic-lpi-tables\n", __func__);
  70. return ret;
  71. }
  72. #endif
  73. bool soc_has_dp_ddr(void)
  74. {
  75. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  76. u32 svr = gur_in32(&gur->svr);
  77. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  78. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  79. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  80. (SVR_SOC_VER(svr) == SVR_LS2048A))
  81. return true;
  82. return false;
  83. }
  84. bool soc_has_aiop(void)
  85. {
  86. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  87. u32 svr = gur_in32(&gur->svr);
  88. /* LS2085A has AIOP */
  89. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  90. return true;
  91. return false;
  92. }
  93. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  94. {
  95. scfg_clrsetbits32(scfg + offset / 4,
  96. 0xF << 6,
  97. SCFG_USB_TXVREFTUNE << 6);
  98. }
  99. static void erratum_a009008(void)
  100. {
  101. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  102. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  103. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  104. defined(CONFIG_ARCH_LS1012A)
  105. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  106. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  107. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  108. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  109. #endif
  110. #elif defined(CONFIG_ARCH_LS2080A)
  111. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  112. #endif
  113. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  114. }
  115. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  116. {
  117. scfg_clrbits32(scfg + offset / 4,
  118. SCFG_USB_SQRXTUNE_MASK << 23);
  119. }
  120. static void erratum_a009798(void)
  121. {
  122. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  123. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  124. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  125. defined(CONFIG_ARCH_LS1012A)
  126. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  127. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  128. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  129. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  130. #endif
  131. #elif defined(CONFIG_ARCH_LS2080A)
  132. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  133. #endif
  134. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  135. }
  136. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  137. defined(CONFIG_ARCH_LS1012A)
  138. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  139. {
  140. scfg_clrsetbits32(scfg + offset / 4,
  141. 0x7F << 9,
  142. SCFG_USB_PCSTXSWINGFULL << 9);
  143. }
  144. #endif
  145. static void erratum_a008997(void)
  146. {
  147. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  148. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  149. defined(CONFIG_ARCH_LS1012A)
  150. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  151. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  152. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  153. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  154. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  155. #endif
  156. #elif defined(CONFIG_ARCH_LS1028A)
  157. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  158. 0x7F << 11,
  159. DCSR_USB_PCSTXSWINGFULL << 11);
  160. #endif
  161. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  162. }
  163. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  164. defined(CONFIG_ARCH_LS1012A)
  165. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  166. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  167. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  168. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  169. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  170. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  171. defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
  172. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  173. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  174. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  175. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  176. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  177. #endif
  178. static void erratum_a009007(void)
  179. {
  180. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  181. defined(CONFIG_ARCH_LS1012A)
  182. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  183. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  184. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  185. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  186. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  187. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  188. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  189. #endif
  190. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  191. defined(CONFIG_ARCH_LS1028A)
  192. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  193. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  194. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  195. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  196. }
  197. #if defined(CONFIG_FSL_LSCH3)
  198. static void erratum_a050106(void)
  199. {
  200. #if defined(CONFIG_ARCH_LX2160A)
  201. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  202. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  203. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  204. #endif
  205. }
  206. /*
  207. * This erratum requires setting a value to eddrtqcr1 to
  208. * optimal the DDR performance.
  209. */
  210. static void erratum_a008336(void)
  211. {
  212. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  213. u32 *eddrtqcr1;
  214. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  215. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  216. if (fsl_ddr_get_version(0) == 0x50200)
  217. out_le32(eddrtqcr1, 0x63b30002);
  218. #endif
  219. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  220. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  221. if (fsl_ddr_get_version(0) == 0x50200)
  222. out_le32(eddrtqcr1, 0x63b30002);
  223. #endif
  224. #endif
  225. }
  226. /*
  227. * This erratum requires a register write before being Memory
  228. * controller 3 being enabled.
  229. */
  230. static void erratum_a008514(void)
  231. {
  232. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  233. u32 *eddrtqcr1;
  234. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  235. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  236. out_le32(eddrtqcr1, 0x63b20002);
  237. #endif
  238. #endif
  239. }
  240. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  241. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  242. static unsigned long get_internval_val_mhz(void)
  243. {
  244. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  245. /*
  246. * interval is the number of platform cycles(MHz) between
  247. * wake up events generated by EPU.
  248. */
  249. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  250. if (interval)
  251. interval_mhz = simple_strtoul(interval, NULL, 10);
  252. return interval_mhz;
  253. }
  254. void erratum_a009635(void)
  255. {
  256. u32 val;
  257. unsigned long interval_mhz = get_internval_val_mhz();
  258. if (!interval_mhz)
  259. return;
  260. val = in_le32(DCSR_CGACRE5);
  261. writel(val | 0x00000200, DCSR_CGACRE5);
  262. val = in_le32(EPU_EPCMPR5);
  263. writel(interval_mhz, EPU_EPCMPR5);
  264. val = in_le32(EPU_EPCCR5);
  265. writel(val | 0x82820000, EPU_EPCCR5);
  266. val = in_le32(EPU_EPSMCR5);
  267. writel(val | 0x002f0000, EPU_EPSMCR5);
  268. val = in_le32(EPU_EPECR5);
  269. writel(val | 0x20000000, EPU_EPECR5);
  270. val = in_le32(EPU_EPGCR);
  271. writel(val | 0x80000000, EPU_EPGCR);
  272. }
  273. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  274. static void erratum_rcw_src(void)
  275. {
  276. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  277. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  278. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  279. u32 val;
  280. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  281. val &= ~DCFG_PORSR1_RCW_SRC;
  282. val |= DCFG_PORSR1_RCW_SRC_NOR;
  283. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  284. #endif
  285. }
  286. #define I2C_DEBUG_REG 0x6
  287. #define I2C_GLITCH_EN 0x8
  288. /*
  289. * This erratum requires setting glitch_en bit to enable
  290. * digital glitch filter to improve clock stability.
  291. */
  292. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  293. static void erratum_a009203(void)
  294. {
  295. #ifdef CONFIG_SYS_I2C
  296. u8 __iomem *ptr;
  297. #ifdef I2C1_BASE_ADDR
  298. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  299. writeb(I2C_GLITCH_EN, ptr);
  300. #endif
  301. #ifdef I2C2_BASE_ADDR
  302. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  303. writeb(I2C_GLITCH_EN, ptr);
  304. #endif
  305. #ifdef I2C3_BASE_ADDR
  306. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  307. writeb(I2C_GLITCH_EN, ptr);
  308. #endif
  309. #ifdef I2C4_BASE_ADDR
  310. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  311. writeb(I2C_GLITCH_EN, ptr);
  312. #endif
  313. #endif
  314. }
  315. #endif
  316. void bypass_smmu(void)
  317. {
  318. u32 val;
  319. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  320. out_le32(SMMU_SCR0, val);
  321. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  322. out_le32(SMMU_NSCR0, val);
  323. }
  324. void fsl_lsch3_early_init_f(void)
  325. {
  326. erratum_rcw_src();
  327. #ifdef CONFIG_FSL_IFC
  328. init_early_memctl_regs(); /* tighten IFC timing */
  329. #endif
  330. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  331. erratum_a009203();
  332. #endif
  333. erratum_a008514();
  334. erratum_a008336();
  335. erratum_a009008();
  336. erratum_a009798();
  337. erratum_a008997();
  338. erratum_a009007();
  339. erratum_a050106();
  340. #ifdef CONFIG_CHAIN_OF_TRUST
  341. /* In case of Secure Boot, the IBR configures the SMMU
  342. * to allow only Secure transactions.
  343. * SMMU must be reset in bypass mode.
  344. * Set the ClientPD bit and Clear the USFCFG Bit
  345. */
  346. if (fsl_check_boot_mode_secure() == 1)
  347. bypass_smmu();
  348. #endif
  349. #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
  350. defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
  351. set_icids();
  352. #endif
  353. }
  354. /* Get VDD in the unit mV from voltage ID */
  355. int get_core_volt_from_fuse(void)
  356. {
  357. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  358. int vdd;
  359. u32 fusesr;
  360. u8 vid;
  361. /* get the voltage ID from fuse status register */
  362. fusesr = in_le32(&gur->dcfg_fusesr);
  363. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  364. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  365. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  366. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  367. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  368. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  369. }
  370. debug("%s: VID = 0x%x\n", __func__, vid);
  371. switch (vid) {
  372. case 0x00: /* VID isn't supported */
  373. vdd = -EINVAL;
  374. debug("%s: The VID feature is not supported\n", __func__);
  375. break;
  376. case 0x08: /* 0.9V silicon */
  377. vdd = 900;
  378. break;
  379. case 0x10: /* 1.0V silicon */
  380. vdd = 1000;
  381. break;
  382. default: /* Other core voltage */
  383. vdd = -EINVAL;
  384. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  385. break;
  386. }
  387. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  388. return vdd;
  389. }
  390. #elif defined(CONFIG_FSL_LSCH2)
  391. static void erratum_a009929(void)
  392. {
  393. #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
  394. struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  395. u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
  396. u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
  397. rstrqmr1 |= 0x00000400;
  398. gur_out32(&gur->rstrqmr1, rstrqmr1);
  399. writel(0x01000000, dcsr_cop_ccp);
  400. #endif
  401. }
  402. /*
  403. * This erratum requires setting a value to eddrtqcr1 to optimal
  404. * the DDR performance. The eddrtqcr1 register is in SCFG space
  405. * of LS1043A and the offset is 0x157_020c.
  406. */
  407. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  408. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  409. #error A009660 and A008514 can not be both enabled.
  410. #endif
  411. static void erratum_a009660(void)
  412. {
  413. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  414. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  415. out_be32(eddrtqcr1, 0x63b20042);
  416. #endif
  417. }
  418. static void erratum_a008850_early(void)
  419. {
  420. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  421. /* part 1 of 2 */
  422. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  423. CONFIG_SYS_CCI400_OFFSET);
  424. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  425. /* Skip if running at lower exception level */
  426. if (current_el() < 3)
  427. return;
  428. /* disables propagation of barrier transactions to DDRC from CCI400 */
  429. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  430. /* disable the re-ordering in DDRC */
  431. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  432. #endif
  433. }
  434. void erratum_a008850_post(void)
  435. {
  436. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  437. /* part 2 of 2 */
  438. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  439. CONFIG_SYS_CCI400_OFFSET);
  440. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  441. u32 tmp;
  442. /* Skip if running at lower exception level */
  443. if (current_el() < 3)
  444. return;
  445. /* enable propagation of barrier transactions to DDRC from CCI400 */
  446. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  447. /* enable the re-ordering in DDRC */
  448. tmp = ddr_in32(&ddr->eor);
  449. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  450. ddr_out32(&ddr->eor, tmp);
  451. #endif
  452. }
  453. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  454. void erratum_a010315(void)
  455. {
  456. int i;
  457. for (i = PCIE1; i <= PCIE4; i++)
  458. if (!is_serdes_configured(i)) {
  459. debug("PCIe%d: disabled all R/W permission!\n", i);
  460. set_pcie_ns_access(i, 0);
  461. }
  462. }
  463. #endif
  464. static void erratum_a010539(void)
  465. {
  466. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  467. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  468. u32 porsr1;
  469. porsr1 = in_be32(&gur->porsr1);
  470. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  471. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  472. porsr1);
  473. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  474. #endif
  475. }
  476. /* Get VDD in the unit mV from voltage ID */
  477. int get_core_volt_from_fuse(void)
  478. {
  479. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  480. int vdd;
  481. u32 fusesr;
  482. u8 vid;
  483. fusesr = in_be32(&gur->dcfg_fusesr);
  484. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  485. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  486. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  487. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  488. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  489. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  490. }
  491. debug("%s: VID = 0x%x\n", __func__, vid);
  492. switch (vid) {
  493. case 0x00: /* VID isn't supported */
  494. vdd = -EINVAL;
  495. debug("%s: The VID feature is not supported\n", __func__);
  496. break;
  497. case 0x08: /* 0.9V silicon */
  498. vdd = 900;
  499. break;
  500. case 0x10: /* 1.0V silicon */
  501. vdd = 1000;
  502. break;
  503. default: /* Other core voltage */
  504. vdd = -EINVAL;
  505. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  506. break;
  507. }
  508. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  509. return vdd;
  510. }
  511. __weak int board_switch_core_volt(u32 vdd)
  512. {
  513. return 0;
  514. }
  515. static int setup_core_volt(u32 vdd)
  516. {
  517. return board_setup_core_volt(vdd);
  518. }
  519. #ifdef CONFIG_SYS_FSL_DDR
  520. static void ddr_enable_0v9_volt(bool en)
  521. {
  522. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  523. u32 tmp;
  524. tmp = ddr_in32(&ddr->ddr_cdr1);
  525. if (en)
  526. tmp |= DDR_CDR1_V0PT9_EN;
  527. else
  528. tmp &= ~DDR_CDR1_V0PT9_EN;
  529. ddr_out32(&ddr->ddr_cdr1, tmp);
  530. }
  531. #endif
  532. int setup_chip_volt(void)
  533. {
  534. int vdd;
  535. vdd = get_core_volt_from_fuse();
  536. /* Nothing to do for silicons doesn't support VID */
  537. if (vdd < 0)
  538. return vdd;
  539. if (setup_core_volt(vdd))
  540. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  541. #ifdef CONFIG_SYS_HAS_SERDES
  542. if (setup_serdes_volt(vdd))
  543. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  544. #endif
  545. #ifdef CONFIG_SYS_FSL_DDR
  546. if (vdd == 900)
  547. ddr_enable_0v9_volt(true);
  548. #endif
  549. return 0;
  550. }
  551. #ifdef CONFIG_FSL_PFE
  552. void init_pfe_scfg_dcfg_regs(void)
  553. {
  554. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  555. u32 ecccr2;
  556. out_be32(&scfg->pfeasbcr,
  557. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  558. out_be32(&scfg->pfebsbcr,
  559. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  560. /* CCI-400 QoS settings for PFE */
  561. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  562. | SCFG_WR_QOS1_PFE2_QOS));
  563. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  564. | SCFG_RD_QOS1_PFE2_QOS));
  565. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  566. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  567. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  568. }
  569. #endif
  570. void fsl_lsch2_early_init_f(void)
  571. {
  572. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  573. CONFIG_SYS_CCI400_OFFSET);
  574. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  575. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  576. enum boot_src src;
  577. #endif
  578. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  579. enable_layerscape_ns_access();
  580. #endif
  581. #ifdef CONFIG_FSL_IFC
  582. init_early_memctl_regs(); /* tighten IFC timing */
  583. #endif
  584. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  585. src = get_boot_src();
  586. if (src != BOOT_SOURCE_QSPI_NOR)
  587. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  588. #else
  589. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  590. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  591. #endif
  592. #endif
  593. /* Make SEC reads and writes snoopable */
  594. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  595. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  596. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  597. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
  598. SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
  599. SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  600. SCFG_SNPCNFGCR_SATAWRSNP);
  601. #elif defined(CONFIG_ARCH_LS1012A)
  602. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  603. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  604. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  605. SCFG_SNPCNFGCR_SATAWRSNP);
  606. #else
  607. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  608. SCFG_SNPCNFGCR_SECWRSNP |
  609. SCFG_SNPCNFGCR_SATARDSNP |
  610. SCFG_SNPCNFGCR_SATAWRSNP);
  611. #endif
  612. /*
  613. * Enable snoop requests and DVM message requests for
  614. * Slave insterface S4 (A53 core cluster)
  615. */
  616. if (current_el() == 3) {
  617. out_le32(&cci->slave[4].snoop_ctrl,
  618. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  619. }
  620. /*
  621. * Program Central Security Unit (CSU) to grant access
  622. * permission for USB 2.0 controller
  623. */
  624. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  625. if (current_el() == 3)
  626. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  627. #endif
  628. /* Erratum */
  629. erratum_a008850_early(); /* part 1 of 2 */
  630. erratum_a009929();
  631. erratum_a009660();
  632. erratum_a010539();
  633. erratum_a009008();
  634. erratum_a009798();
  635. erratum_a008997();
  636. erratum_a009007();
  637. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  638. set_icids();
  639. #endif
  640. }
  641. #endif
  642. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  643. int fspi_ahb_init(void)
  644. {
  645. /* Enable 4bytes address support and fast read */
  646. u32 *fspi_lut, lut_key, *fspi_key;
  647. fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
  648. fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
  649. lut_key = in_be32(fspi_key);
  650. if (lut_key == SYS_NXP_FSPI_LUTKEY) {
  651. /* That means the register is BE */
  652. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  653. /* Unlock the lut table */
  654. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  655. /* Create READ LUT */
  656. out_be32(fspi_lut, 0x0820040c);
  657. out_be32(fspi_lut + 1, 0x24003008);
  658. out_be32(fspi_lut + 2, 0x00000000);
  659. /* Lock the lut table */
  660. out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  661. out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  662. } else {
  663. /* That means the register is LE */
  664. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  665. /* Unlock the lut table */
  666. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
  667. /* Create READ LUT */
  668. out_le32(fspi_lut, 0x0820040c);
  669. out_le32(fspi_lut + 1, 0x24003008);
  670. out_le32(fspi_lut + 2, 0x00000000);
  671. /* Lock the lut table */
  672. out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
  673. out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
  674. }
  675. return 0;
  676. }
  677. #endif
  678. #ifdef CONFIG_QSPI_AHB_INIT
  679. /* Enable 4bytes address support and fast read */
  680. int qspi_ahb_init(void)
  681. {
  682. u32 *qspi_lut, lut_key, *qspi_key;
  683. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  684. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  685. lut_key = in_be32(qspi_key);
  686. if (lut_key == 0x5af05af0) {
  687. /* That means the register is BE */
  688. out_be32(qspi_key, 0x5af05af0);
  689. /* Unlock the lut table */
  690. out_be32(qspi_key + 1, 0x00000002);
  691. out_be32(qspi_lut, 0x0820040c);
  692. out_be32(qspi_lut + 1, 0x1c080c08);
  693. out_be32(qspi_lut + 2, 0x00002400);
  694. /* Lock the lut table */
  695. out_be32(qspi_key, 0x5af05af0);
  696. out_be32(qspi_key + 1, 0x00000001);
  697. } else {
  698. /* That means the register is LE */
  699. out_le32(qspi_key, 0x5af05af0);
  700. /* Unlock the lut table */
  701. out_le32(qspi_key + 1, 0x00000002);
  702. out_le32(qspi_lut, 0x0820040c);
  703. out_le32(qspi_lut + 1, 0x1c080c08);
  704. out_le32(qspi_lut + 2, 0x00002400);
  705. /* Lock the lut table */
  706. out_le32(qspi_key, 0x5af05af0);
  707. out_le32(qspi_key + 1, 0x00000001);
  708. }
  709. return 0;
  710. }
  711. #endif
  712. #ifdef CONFIG_TFABOOT
  713. #define MAX_BOOTCMD_SIZE 512
  714. int fsl_setenv_bootcmd(void)
  715. {
  716. int ret;
  717. enum boot_src src = get_boot_src();
  718. char bootcmd_str[MAX_BOOTCMD_SIZE];
  719. switch (src) {
  720. #ifdef IFC_NOR_BOOTCOMMAND
  721. case BOOT_SOURCE_IFC_NOR:
  722. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  723. break;
  724. #endif
  725. #ifdef QSPI_NOR_BOOTCOMMAND
  726. case BOOT_SOURCE_QSPI_NOR:
  727. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  728. break;
  729. #endif
  730. #ifdef XSPI_NOR_BOOTCOMMAND
  731. case BOOT_SOURCE_XSPI_NOR:
  732. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  733. break;
  734. #endif
  735. #ifdef IFC_NAND_BOOTCOMMAND
  736. case BOOT_SOURCE_IFC_NAND:
  737. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  738. break;
  739. #endif
  740. #ifdef QSPI_NAND_BOOTCOMMAND
  741. case BOOT_SOURCE_QSPI_NAND:
  742. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  743. break;
  744. #endif
  745. #ifdef XSPI_NAND_BOOTCOMMAND
  746. case BOOT_SOURCE_XSPI_NAND:
  747. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  748. break;
  749. #endif
  750. #ifdef SD_BOOTCOMMAND
  751. case BOOT_SOURCE_SD_MMC:
  752. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  753. break;
  754. #endif
  755. #ifdef SD2_BOOTCOMMAND
  756. case BOOT_SOURCE_SD_MMC2:
  757. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  758. break;
  759. #endif
  760. default:
  761. #ifdef QSPI_NOR_BOOTCOMMAND
  762. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  763. #endif
  764. break;
  765. }
  766. ret = env_set("bootcmd", bootcmd_str);
  767. if (ret) {
  768. printf("Failed to set bootcmd: ret = %d\n", ret);
  769. return ret;
  770. }
  771. return 0;
  772. }
  773. int fsl_setenv_mcinitcmd(void)
  774. {
  775. int ret = 0;
  776. enum boot_src src = get_boot_src();
  777. switch (src) {
  778. #ifdef IFC_MC_INIT_CMD
  779. case BOOT_SOURCE_IFC_NAND:
  780. case BOOT_SOURCE_IFC_NOR:
  781. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  782. break;
  783. #endif
  784. #ifdef QSPI_MC_INIT_CMD
  785. case BOOT_SOURCE_QSPI_NAND:
  786. case BOOT_SOURCE_QSPI_NOR:
  787. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  788. break;
  789. #endif
  790. #ifdef XSPI_MC_INIT_CMD
  791. case BOOT_SOURCE_XSPI_NAND:
  792. case BOOT_SOURCE_XSPI_NOR:
  793. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  794. break;
  795. #endif
  796. #ifdef SD_MC_INIT_CMD
  797. case BOOT_SOURCE_SD_MMC:
  798. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  799. break;
  800. #endif
  801. #ifdef SD2_MC_INIT_CMD
  802. case BOOT_SOURCE_SD_MMC2:
  803. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  804. break;
  805. #endif
  806. default:
  807. #ifdef QSPI_MC_INIT_CMD
  808. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  809. #endif
  810. break;
  811. }
  812. if (ret) {
  813. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  814. return ret;
  815. }
  816. return 0;
  817. }
  818. #endif
  819. #ifdef CONFIG_BOARD_LATE_INIT
  820. __weak int fsl_board_late_init(void)
  821. {
  822. return 0;
  823. }
  824. int board_late_init(void)
  825. {
  826. #ifdef CONFIG_CHAIN_OF_TRUST
  827. fsl_setenv_chain_of_trust();
  828. #endif
  829. #ifdef CONFIG_TFABOOT
  830. /*
  831. * check if gd->env_addr is default_environment; then setenv bootcmd
  832. * and mcinitcmd.
  833. */
  834. #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
  835. if (gd->env_addr == (ulong)&default_environment[0]) {
  836. #else
  837. if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  838. #endif
  839. fsl_setenv_bootcmd();
  840. fsl_setenv_mcinitcmd();
  841. }
  842. /*
  843. * If the boot mode is secure, default environment is not present then
  844. * setenv command needs to be run by default
  845. */
  846. #ifdef CONFIG_CHAIN_OF_TRUST
  847. if ((fsl_check_boot_mode_secure() == 1)) {
  848. fsl_setenv_bootcmd();
  849. fsl_setenv_mcinitcmd();
  850. }
  851. #endif
  852. #endif
  853. #ifdef CONFIG_QSPI_AHB_INIT
  854. qspi_ahb_init();
  855. #endif
  856. #ifdef CONFIG_FSPI_AHB_EN_4BYTE
  857. fspi_ahb_init();
  858. #endif
  859. return fsl_board_late_init();
  860. }
  861. #endif