fsl_lsch3_serdes.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016-2018 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/arch/soc.h>
  13. #include <fsl-mc/ldpaa_wriop.h>
  14. #ifdef CONFIG_SYS_FSL_SRDS_1
  15. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  16. #endif
  17. #ifdef CONFIG_SYS_FSL_SRDS_2
  18. static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  19. #endif
  20. #ifdef CONFIG_SYS_NXP_SRDS_3
  21. static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  22. #endif
  23. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  24. #ifdef CONFIG_ARCH_LX2160A
  25. int xfi_dpmac[XFI14 + 1];
  26. int sgmii_dpmac[SGMII18 + 1];
  27. int a25gaui_dpmac[_25GE10 + 1];
  28. int xlaui_dpmac[_40GE2 + 1];
  29. int caui2_dpmac[_50GE2 + 1];
  30. int caui4_dpmac[_100GE2 + 1];
  31. #else
  32. int xfi_dpmac[XFI8 + 1];
  33. int sgmii_dpmac[SGMII16 + 1];
  34. #endif
  35. #endif
  36. __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  37. {
  38. return;
  39. }
  40. /*
  41. *The return value of this func is the serdes protocol used.
  42. *Typically this function is called number of times depending
  43. *upon the number of serdes blocks in the Silicon.
  44. *Zero is used to denote that no serdes was enabled,
  45. *this is the case when golden RCW was used where DPAA2 bring was
  46. *intentionally removed to achieve boot to prompt
  47. */
  48. __weak int serdes_get_number(int serdes, int cfg)
  49. {
  50. return cfg;
  51. }
  52. int is_serdes_configured(enum srds_prtcl device)
  53. {
  54. int ret = 0;
  55. #ifdef CONFIG_SYS_FSL_SRDS_1
  56. if (!serdes1_prtcl_map[NONE])
  57. fsl_serdes_init();
  58. ret |= serdes1_prtcl_map[device];
  59. #endif
  60. #ifdef CONFIG_SYS_FSL_SRDS_2
  61. if (!serdes2_prtcl_map[NONE])
  62. fsl_serdes_init();
  63. ret |= serdes2_prtcl_map[device];
  64. #endif
  65. #ifdef CONFIG_SYS_NXP_SRDS_3
  66. if (!serdes3_prtcl_map[NONE])
  67. fsl_serdes_init();
  68. ret |= serdes3_prtcl_map[device];
  69. #endif
  70. return !!ret;
  71. }
  72. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  73. {
  74. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  75. u32 cfg = 0;
  76. int i;
  77. switch (sd) {
  78. #ifdef CONFIG_SYS_FSL_SRDS_1
  79. case FSL_SRDS_1:
  80. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  81. cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  82. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  83. break;
  84. #endif
  85. #ifdef CONFIG_SYS_FSL_SRDS_2
  86. case FSL_SRDS_2:
  87. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  88. cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
  89. cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
  90. break;
  91. #endif
  92. #ifdef CONFIG_SYS_NXP_SRDS_3
  93. case NXP_SRDS_3:
  94. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  95. cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
  96. cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
  97. break;
  98. #endif
  99. default:
  100. printf("invalid SerDes%d\n", sd);
  101. break;
  102. }
  103. cfg = serdes_get_number(sd, cfg);
  104. /* Is serdes enabled at all? */
  105. if (cfg == 0)
  106. return -ENODEV;
  107. for (i = 0; i < SRDS_MAX_LANES; i++) {
  108. if (serdes_get_prtcl(sd, cfg, i) == device)
  109. return i;
  110. }
  111. return -ENODEV;
  112. }
  113. void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
  114. u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  115. {
  116. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  117. u32 cfg;
  118. int lane;
  119. if (serdes_prtcl_map[NONE])
  120. return;
  121. memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
  122. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  123. cfg >>= sd_prctl_shift;
  124. cfg = serdes_get_number(sd, cfg);
  125. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  126. if (!is_serdes_prtcl_valid(sd, cfg))
  127. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  128. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  129. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  130. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  131. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  132. else {
  133. serdes_prtcl_map[lane_prtcl] = 1;
  134. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  135. #ifdef CONFIG_ARCH_LX2160A
  136. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
  137. wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
  138. (int)lane_prtcl);
  139. if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
  140. wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
  141. (int)lane_prtcl);
  142. if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
  143. wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
  144. (int)lane_prtcl);
  145. if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
  146. wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
  147. (int)lane_prtcl);
  148. if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
  149. wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
  150. (int)lane_prtcl);
  151. if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
  152. wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
  153. (int)lane_prtcl);
  154. #else
  155. switch (lane_prtcl) {
  156. case QSGMII_A:
  157. case QSGMII_B:
  158. case QSGMII_C:
  159. case QSGMII_D:
  160. wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
  161. break;
  162. default:
  163. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
  164. wriop_init_dpmac(sd,
  165. xfi_dpmac[lane_prtcl],
  166. (int)lane_prtcl);
  167. if (lane_prtcl >= SGMII1 &&
  168. lane_prtcl <= SGMII16)
  169. wriop_init_dpmac(sd, sgmii_dpmac[
  170. lane_prtcl],
  171. (int)lane_prtcl);
  172. break;
  173. }
  174. #endif
  175. #endif
  176. }
  177. }
  178. /* Set the first element to indicate serdes has been initialized */
  179. serdes_prtcl_map[NONE] = 1;
  180. }
  181. __weak int get_serdes_volt(void)
  182. {
  183. return -1;
  184. }
  185. __weak int set_serdes_volt(int svdd)
  186. {
  187. return -1;
  188. }
  189. #define LNAGCR0_RT_RSTB 0x00600000
  190. #define RSTCTL_RESET_MASK 0x000000E0
  191. #define RSTCTL_RSTREQ 0x80000000
  192. #define RSTCTL_RST_DONE 0x40000000
  193. #define RSTCTL_RSTERR 0x20000000
  194. #define RSTCTL_SDEN 0x00000020
  195. #define RSTCTL_SDRST_B 0x00000040
  196. #define RSTCTL_PLLRST_B 0x00000080
  197. #define TCALCR_CALRST_B 0x08000000
  198. struct serdes_prctl_info {
  199. u32 id;
  200. u32 mask;
  201. u32 shift;
  202. };
  203. struct serdes_prctl_info srds_prctl_info[] = {
  204. #ifdef CONFIG_SYS_FSL_SRDS_1
  205. {.id = 1,
  206. .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  207. .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
  208. },
  209. #endif
  210. #ifdef CONFIG_SYS_FSL_SRDS_2
  211. {.id = 2,
  212. .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  213. .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
  214. },
  215. #endif
  216. #ifdef CONFIG_SYS_NXP_SRDS_3
  217. {.id = 3,
  218. .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  219. .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
  220. },
  221. #endif
  222. {} /* NULL ENTRY */
  223. };
  224. static int get_serdes_prctl_info_idx(u32 serdes_id)
  225. {
  226. int pos = 0;
  227. struct serdes_prctl_info *srds_info;
  228. /* loop until NULL ENTRY defined by .id=0 */
  229. for (srds_info = srds_prctl_info; srds_info->id != 0;
  230. srds_info++, pos++) {
  231. if (srds_info->id == serdes_id)
  232. return pos;
  233. }
  234. return -1;
  235. }
  236. static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
  237. struct ccsr_serdes __iomem *serdes_base,
  238. bool cmplt)
  239. {
  240. int i, pos;
  241. u32 cfg_tmp;
  242. pos = get_serdes_prctl_info_idx(serdes_id);
  243. if (pos == -1) {
  244. printf("invalid serdes_id %d\n", serdes_id);
  245. return;
  246. }
  247. cfg_tmp = cfg & srds_prctl_info[pos].mask;
  248. cfg_tmp >>= srds_prctl_info[pos].shift;
  249. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  250. if (cmplt)
  251. setbits_le32(&serdes_base->lane[i].gcr0,
  252. LNAGCR0_RT_RSTB);
  253. else
  254. clrbits_le32(&serdes_base->lane[i].gcr0,
  255. LNAGCR0_RT_RSTB);
  256. }
  257. }
  258. static void do_pll_reset(u32 cfg,
  259. struct ccsr_serdes __iomem *serdes_base)
  260. {
  261. int i;
  262. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  263. clrbits_le32(&serdes_base->bank[i].rstctl,
  264. RSTCTL_RESET_MASK);
  265. udelay(1);
  266. setbits_le32(&serdes_base->bank[i].rstctl,
  267. RSTCTL_RSTREQ);
  268. }
  269. udelay(1);
  270. }
  271. static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
  272. {
  273. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  274. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  275. }
  276. static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
  277. struct ccsr_serdes __iomem *serdes_base)
  278. {
  279. if (!(cfg == 0x3 && i == 1)) {
  280. udelay(1);
  281. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  282. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  283. }
  284. udelay(1);
  285. }
  286. static void do_pll_reset_done(u32 cfg,
  287. struct ccsr_serdes __iomem *serdes_base)
  288. {
  289. int i;
  290. u32 reg = 0;
  291. for (i = 0; i < 2; i++) {
  292. reg = in_le32(&serdes_base->bank[i].pllcr0);
  293. if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
  294. setbits_le32(&serdes_base->bank[i].rstctl,
  295. RSTCTL_RST_DONE);
  296. }
  297. }
  298. }
  299. static void do_serdes_enable(u32 cfg,
  300. struct ccsr_serdes __iomem *serdes_base)
  301. {
  302. int i;
  303. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  304. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
  305. udelay(1);
  306. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
  307. udelay(1);
  308. /* Take the Rx/Tx calibration out of reset */
  309. do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
  310. }
  311. }
  312. static void do_pll_lock(u32 cfg,
  313. struct ccsr_serdes __iomem *serdes_base)
  314. {
  315. int i;
  316. u32 reg = 0;
  317. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  318. /* if the PLL is not locked, set RST_ERR */
  319. reg = in_le32(&serdes_base->bank[i].pllcr0);
  320. if (!((reg >> 23) & 0x1)) {
  321. setbits_le32(&serdes_base->bank[i].rstctl,
  322. RSTCTL_RSTERR);
  323. } else {
  324. udelay(1);
  325. setbits_le32(&serdes_base->bank[i].rstctl,
  326. RSTCTL_SDRST_B);
  327. udelay(1);
  328. }
  329. }
  330. }
  331. int setup_serdes_volt(u32 svdd)
  332. {
  333. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  334. struct ccsr_serdes __iomem *serdes1_base =
  335. (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
  336. u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  337. #ifdef CONFIG_SYS_FSL_SRDS_2
  338. struct ccsr_serdes __iomem *serdes2_base =
  339. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
  340. u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  341. #endif
  342. #ifdef CONFIG_SYS_NXP_SRDS_3
  343. struct ccsr_serdes __iomem *serdes3_base =
  344. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
  345. u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  346. #endif
  347. u32 cfg_tmp;
  348. int svdd_cur, svdd_tar;
  349. int ret = 1;
  350. /* Only support switch SVDD to 900mV */
  351. if (svdd != 900)
  352. return -EINVAL;
  353. /* Scale up to the LTC resolution is 1/4096V */
  354. svdd = (svdd * 4096) / 1000;
  355. svdd_tar = svdd;
  356. svdd_cur = get_serdes_volt();
  357. if (svdd_cur < 0)
  358. return -EINVAL;
  359. debug("%s: current SVDD: %x; target SVDD: %x\n",
  360. __func__, svdd_cur, svdd_tar);
  361. if (svdd_cur == svdd_tar)
  362. return 0;
  363. /* Put the all enabled lanes in reset */
  364. #ifdef CONFIG_SYS_FSL_SRDS_1
  365. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
  366. #endif
  367. #ifdef CONFIG_SYS_FSL_SRDS_2
  368. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
  369. #endif
  370. #ifdef CONFIG_SYS_NXP_SRDS_3
  371. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
  372. #endif
  373. /* Put the all enabled PLL in reset */
  374. #ifdef CONFIG_SYS_FSL_SRDS_1
  375. cfg_tmp = cfg_rcwsrds1 & 0x3;
  376. do_pll_reset(cfg_tmp, serdes1_base);
  377. #endif
  378. #ifdef CONFIG_SYS_FSL_SRDS_2
  379. cfg_tmp = cfg_rcwsrds1 & 0xC;
  380. cfg_tmp >>= 2;
  381. do_pll_reset(cfg_tmp, serdes2_base);
  382. #endif
  383. #ifdef CONFIG_SYS_NXP_SRDS_3
  384. cfg_tmp = cfg_rcwsrds3 & 0x30;
  385. cfg_tmp >>= 4;
  386. do_pll_reset(cfg_tmp, serdes3_base);
  387. #endif
  388. /* Put the Rx/Tx calibration into reset */
  389. #ifdef CONFIG_SYS_FSL_SRDS_1
  390. do_rx_tx_cal_reset(serdes1_base);
  391. #endif
  392. #ifdef CONFIG_SYS_FSL_SRDS_2
  393. do_rx_tx_cal_reset(serdes2_base);
  394. #endif
  395. #ifdef CONFIG_SYS_NXP_SRDS_3
  396. do_rx_tx_cal_reset(serdes3_base);
  397. #endif
  398. ret = set_serdes_volt(svdd);
  399. if (ret < 0) {
  400. printf("could not change SVDD\n");
  401. ret = -1;
  402. }
  403. /* For each PLL that’s not disabled via RCW enable the SERDES */
  404. #ifdef CONFIG_SYS_FSL_SRDS_1
  405. cfg_tmp = cfg_rcwsrds1 & 0x3;
  406. do_serdes_enable(cfg_tmp, serdes1_base);
  407. #endif
  408. #ifdef CONFIG_SYS_FSL_SRDS_2
  409. cfg_tmp = cfg_rcwsrds1 & 0xC;
  410. cfg_tmp >>= 2;
  411. do_serdes_enable(cfg_tmp, serdes2_base);
  412. #endif
  413. #ifdef CONFIG_SYS_NXP_SRDS_3
  414. cfg_tmp = cfg_rcwsrds3 & 0x30;
  415. cfg_tmp >>= 4;
  416. do_serdes_enable(cfg_tmp, serdes3_base);
  417. #endif
  418. /* Wait for at at least 625us, ensure the PLLs being reset are locked */
  419. udelay(800);
  420. #ifdef CONFIG_SYS_FSL_SRDS_1
  421. cfg_tmp = cfg_rcwsrds1 & 0x3;
  422. do_pll_lock(cfg_tmp, serdes1_base);
  423. #endif
  424. #ifdef CONFIG_SYS_FSL_SRDS_2
  425. cfg_tmp = cfg_rcwsrds1 & 0xC;
  426. cfg_tmp >>= 2;
  427. do_pll_lock(cfg_tmp, serdes2_base);
  428. #endif
  429. #ifdef CONFIG_SYS_NXP_SRDS_3
  430. cfg_tmp = cfg_rcwsrds3 & 0x30;
  431. cfg_tmp >>= 4;
  432. do_pll_lock(cfg_tmp, serdes3_base);
  433. #endif
  434. /* Take the all enabled lanes out of reset */
  435. #ifdef CONFIG_SYS_FSL_SRDS_1
  436. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
  437. #endif
  438. #ifdef CONFIG_SYS_FSL_SRDS_2
  439. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
  440. #endif
  441. #ifdef CONFIG_SYS_NXP_SRDS_3
  442. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
  443. #endif
  444. /* For each PLL being reset, and achieved PLL lock set RST_DONE */
  445. #ifdef CONFIG_SYS_FSL_SRDS_1
  446. cfg_tmp = cfg_rcwsrds1 & 0x3;
  447. do_pll_reset_done(cfg_tmp, serdes1_base);
  448. #endif
  449. #ifdef CONFIG_SYS_FSL_SRDS_2
  450. cfg_tmp = cfg_rcwsrds1 & 0xC;
  451. cfg_tmp >>= 2;
  452. do_pll_reset_done(cfg_tmp, serdes2_base);
  453. #endif
  454. #ifdef CONFIG_SYS_NXP_SRDS_3
  455. cfg_tmp = cfg_rcwsrds3 & 0x30;
  456. cfg_tmp >>= 4;
  457. do_pll_reset_done(cfg_tmp, serdes3_base);
  458. #endif
  459. return ret;
  460. }
  461. void fsl_serdes_init(void)
  462. {
  463. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  464. int i , j;
  465. #ifdef CONFIG_ARCH_LX2160A
  466. for (i = XFI1, j = 1; i <= XFI14; i++, j++)
  467. xfi_dpmac[i] = j;
  468. for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
  469. sgmii_dpmac[i] = j;
  470. for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
  471. a25gaui_dpmac[i] = j;
  472. for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
  473. xlaui_dpmac[i] = j;
  474. for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
  475. caui2_dpmac[i] = j;
  476. for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
  477. caui4_dpmac[i] = j;
  478. #else
  479. for (i = XFI1, j = 1; i <= XFI8; i++, j++)
  480. xfi_dpmac[i] = j;
  481. for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
  482. sgmii_dpmac[i] = j;
  483. #endif
  484. #endif
  485. #ifdef CONFIG_SYS_FSL_SRDS_1
  486. serdes_init(FSL_SRDS_1,
  487. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
  488. FSL_CHASSIS3_SRDS1_REGSR,
  489. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  490. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
  491. serdes1_prtcl_map);
  492. #endif
  493. #ifdef CONFIG_SYS_FSL_SRDS_2
  494. serdes_init(FSL_SRDS_2,
  495. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
  496. FSL_CHASSIS3_SRDS2_REGSR,
  497. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  498. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
  499. serdes2_prtcl_map);
  500. #endif
  501. #ifdef CONFIG_SYS_NXP_SRDS_3
  502. serdes_init(NXP_SRDS_3,
  503. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
  504. FSL_CHASSIS3_SRDS3_REGSR,
  505. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  506. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
  507. serdes3_prtcl_map);
  508. #endif
  509. }
  510. int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
  511. {
  512. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  513. char scfg[16], snum[16];
  514. int cfgr = 0;
  515. u32 cfg;
  516. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  517. cfg >>= sd_prctl_shift;
  518. cfg = serdes_get_number(sd, cfg);
  519. #if defined(SRDS_BITS_PER_LANE)
  520. /*
  521. * reverse lanes, lane 0 should be printed first so it must be moved to
  522. * high order bits.
  523. * For example bb58 should read 85bb, lane 0 being protocol 8.
  524. * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
  525. * independent per-lane protocol configuration, at this time LS1028A and
  526. * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
  527. * lanes as a single value.
  528. */
  529. for (int i = 0; i < SRDS_MAX_LANES; i++) {
  530. int tmp;
  531. tmp = cfg >> (i * SRDS_BITS_PER_LANE);
  532. tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
  533. tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
  534. cfgr |= tmp;
  535. }
  536. #endif /* SRDS_BITS_PER_LANE */
  537. snprintf(snum, 16, "serdes%d", sd);
  538. snprintf(scfg, 16, "%x", cfgr);
  539. env_set(snum, scfg);
  540. return 0;
  541. }
  542. int serdes_misc_init(void)
  543. {
  544. #ifdef CONFIG_SYS_FSL_SRDS_1
  545. serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
  546. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  547. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
  548. #endif
  549. #ifdef CONFIG_SYS_FSL_SRDS_2
  550. serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
  551. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  552. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
  553. #endif
  554. #ifdef CONFIG_SYS_NXP_SRDS_3
  555. serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
  556. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  557. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
  558. #endif
  559. return 0;
  560. }