cache_v8.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. *
  6. * (C) Copyright 2016
  7. * Alexander Graf <agraf@suse.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <hang.h>
  12. #include <log.h>
  13. #include <asm/cache.h>
  14. #include <asm/system.h>
  15. #include <asm/armv8/mmu.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  18. /*
  19. * With 4k page granule, a virtual address is split into 4 lookup parts
  20. * spanning 9 bits each:
  21. *
  22. * _______________________________________________
  23. * | | | | | | |
  24. * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
  25. * |_______|_______|_______|_______|_______|_______|
  26. * 63-48 47-39 38-30 29-21 20-12 11-00
  27. *
  28. * mask page size
  29. *
  30. * Lv0: FF8000000000 --
  31. * Lv1: 7FC0000000 1G
  32. * Lv2: 3FE00000 2M
  33. * Lv3: 1FF000 4K
  34. * off: FFF
  35. */
  36. u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
  37. {
  38. u64 max_addr = 0;
  39. u64 ips, va_bits;
  40. u64 tcr;
  41. int i;
  42. /* Find the largest address we need to support */
  43. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  44. max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
  45. /* Calculate the maximum physical (and thus virtual) address */
  46. if (max_addr > (1ULL << 44)) {
  47. ips = 5;
  48. va_bits = 48;
  49. } else if (max_addr > (1ULL << 42)) {
  50. ips = 4;
  51. va_bits = 44;
  52. } else if (max_addr > (1ULL << 40)) {
  53. ips = 3;
  54. va_bits = 42;
  55. } else if (max_addr > (1ULL << 36)) {
  56. ips = 2;
  57. va_bits = 40;
  58. } else if (max_addr > (1ULL << 32)) {
  59. ips = 1;
  60. va_bits = 36;
  61. } else {
  62. ips = 0;
  63. va_bits = 32;
  64. }
  65. if (el == 1) {
  66. tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
  67. } else if (el == 2) {
  68. tcr = TCR_EL2_RSVD | (ips << 16);
  69. } else {
  70. tcr = TCR_EL3_RSVD | (ips << 16);
  71. }
  72. /* PTWs cacheable, inner/outer WBWA and inner shareable */
  73. tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
  74. tcr |= TCR_T0SZ(va_bits);
  75. if (pips)
  76. *pips = ips;
  77. if (pva_bits)
  78. *pva_bits = va_bits;
  79. return tcr;
  80. }
  81. #define MAX_PTE_ENTRIES 512
  82. static int pte_type(u64 *pte)
  83. {
  84. return *pte & PTE_TYPE_MASK;
  85. }
  86. /* Returns the LSB number for a PTE on level <level> */
  87. static int level2shift(int level)
  88. {
  89. /* Page is 12 bits wide, every level translates 9 bits */
  90. return (12 + 9 * (3 - level));
  91. }
  92. static u64 *find_pte(u64 addr, int level)
  93. {
  94. int start_level = 0;
  95. u64 *pte;
  96. u64 idx;
  97. u64 va_bits;
  98. int i;
  99. debug("addr=%llx level=%d\n", addr, level);
  100. get_tcr(0, NULL, &va_bits);
  101. if (va_bits < 39)
  102. start_level = 1;
  103. if (level < start_level)
  104. return NULL;
  105. /* Walk through all page table levels to find our PTE */
  106. pte = (u64*)gd->arch.tlb_addr;
  107. for (i = start_level; i < 4; i++) {
  108. idx = (addr >> level2shift(i)) & 0x1FF;
  109. pte += idx;
  110. debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
  111. /* Found it */
  112. if (i == level)
  113. return pte;
  114. /* PTE is no table (either invalid or block), can't traverse */
  115. if (pte_type(pte) != PTE_TYPE_TABLE)
  116. return NULL;
  117. /* Off to the next level */
  118. pte = (u64*)(*pte & 0x0000fffffffff000ULL);
  119. }
  120. /* Should never reach here */
  121. return NULL;
  122. }
  123. /* Returns and creates a new full table (512 entries) */
  124. static u64 *create_table(void)
  125. {
  126. u64 *new_table = (u64*)gd->arch.tlb_fillptr;
  127. u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
  128. /* Allocate MAX_PTE_ENTRIES pte entries */
  129. gd->arch.tlb_fillptr += pt_len;
  130. if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
  131. panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
  132. "Please increase the size in get_page_table_size()",
  133. gd->arch.tlb_fillptr - gd->arch.tlb_addr,
  134. gd->arch.tlb_size);
  135. /* Mark all entries as invalid */
  136. memset(new_table, 0, pt_len);
  137. return new_table;
  138. }
  139. static void set_pte_table(u64 *pte, u64 *table)
  140. {
  141. /* Point *pte to the new table */
  142. debug("Setting %p to addr=%p\n", pte, table);
  143. *pte = PTE_TYPE_TABLE | (ulong)table;
  144. }
  145. /* Splits a block PTE into table with subpages spanning the old block */
  146. static void split_block(u64 *pte, int level)
  147. {
  148. u64 old_pte = *pte;
  149. u64 *new_table;
  150. u64 i = 0;
  151. /* level describes the parent level, we need the child ones */
  152. int levelshift = level2shift(level + 1);
  153. if (pte_type(pte) != PTE_TYPE_BLOCK)
  154. panic("PTE %p (%llx) is not a block. Some driver code wants to "
  155. "modify dcache settings for an range not covered in "
  156. "mem_map.", pte, old_pte);
  157. new_table = create_table();
  158. debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
  159. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  160. new_table[i] = old_pte | (i << levelshift);
  161. /* Level 3 block PTEs have the table type */
  162. if ((level + 1) == 3)
  163. new_table[i] |= PTE_TYPE_TABLE;
  164. debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
  165. }
  166. /* Set the new table into effect */
  167. set_pte_table(pte, new_table);
  168. }
  169. /* Add one mm_region map entry to the page tables */
  170. static void add_map(struct mm_region *map)
  171. {
  172. u64 *pte;
  173. u64 virt = map->virt;
  174. u64 phys = map->phys;
  175. u64 size = map->size;
  176. u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
  177. u64 blocksize;
  178. int level;
  179. u64 *new_table;
  180. while (size) {
  181. pte = find_pte(virt, 0);
  182. if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
  183. debug("Creating table for virt 0x%llx\n", virt);
  184. new_table = create_table();
  185. set_pte_table(pte, new_table);
  186. }
  187. for (level = 1; level < 4; level++) {
  188. pte = find_pte(virt, level);
  189. if (!pte)
  190. panic("pte not found\n");
  191. blocksize = 1ULL << level2shift(level);
  192. debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
  193. virt, size, blocksize);
  194. if (size >= blocksize && !(virt & (blocksize - 1))) {
  195. /* Page fits, create block PTE */
  196. debug("Setting PTE %p to block virt=%llx\n",
  197. pte, virt);
  198. if (level == 3)
  199. *pte = phys | attrs | PTE_TYPE_PAGE;
  200. else
  201. *pte = phys | attrs;
  202. virt += blocksize;
  203. phys += blocksize;
  204. size -= blocksize;
  205. break;
  206. } else if (pte_type(pte) == PTE_TYPE_FAULT) {
  207. /* Page doesn't fit, create subpages */
  208. debug("Creating subtable for virt 0x%llx blksize=%llx\n",
  209. virt, blocksize);
  210. new_table = create_table();
  211. set_pte_table(pte, new_table);
  212. } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
  213. debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
  214. virt, blocksize);
  215. split_block(pte, level);
  216. }
  217. }
  218. }
  219. }
  220. enum pte_type {
  221. PTE_INVAL,
  222. PTE_BLOCK,
  223. PTE_LEVEL,
  224. };
  225. /*
  226. * This is a recursively called function to count the number of
  227. * page tables we need to cover a particular PTE range. If you
  228. * call this with level = -1 you basically get the full 48 bit
  229. * coverage.
  230. */
  231. static int count_required_pts(u64 addr, int level, u64 maxaddr)
  232. {
  233. int levelshift = level2shift(level);
  234. u64 levelsize = 1ULL << levelshift;
  235. u64 levelmask = levelsize - 1;
  236. u64 levelend = addr + levelsize;
  237. int r = 0;
  238. int i;
  239. enum pte_type pte_type = PTE_INVAL;
  240. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
  241. struct mm_region *map = &mem_map[i];
  242. u64 start = map->virt;
  243. u64 end = start + map->size;
  244. /* Check if the PTE would overlap with the map */
  245. if (max(addr, start) <= min(levelend, end)) {
  246. start = max(addr, start);
  247. end = min(levelend, end);
  248. /* We need a sub-pt for this level */
  249. if ((start & levelmask) || (end & levelmask)) {
  250. pte_type = PTE_LEVEL;
  251. break;
  252. }
  253. /* Lv0 can not do block PTEs, so do levels here too */
  254. if (level <= 0) {
  255. pte_type = PTE_LEVEL;
  256. break;
  257. }
  258. /* PTE is active, but fits into a block */
  259. pte_type = PTE_BLOCK;
  260. }
  261. }
  262. /*
  263. * Block PTEs at this level are already covered by the parent page
  264. * table, so we only need to count sub page tables.
  265. */
  266. if (pte_type == PTE_LEVEL) {
  267. int sublevel = level + 1;
  268. u64 sublevelsize = 1ULL << level2shift(sublevel);
  269. /* Account for the new sub page table ... */
  270. r = 1;
  271. /* ... and for all child page tables that one might have */
  272. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  273. r += count_required_pts(addr, sublevel, maxaddr);
  274. addr += sublevelsize;
  275. if (addr >= maxaddr) {
  276. /*
  277. * We reached the end of address space, no need
  278. * to look any further.
  279. */
  280. break;
  281. }
  282. }
  283. }
  284. return r;
  285. }
  286. /* Returns the estimated required size of all page tables */
  287. __weak u64 get_page_table_size(void)
  288. {
  289. u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
  290. u64 size = 0;
  291. u64 va_bits;
  292. int start_level = 0;
  293. get_tcr(0, NULL, &va_bits);
  294. if (va_bits < 39)
  295. start_level = 1;
  296. /* Account for all page tables we would need to cover our memory map */
  297. size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
  298. /*
  299. * We need to duplicate our page table once to have an emergency pt to
  300. * resort to when splitting page tables later on
  301. */
  302. size *= 2;
  303. /*
  304. * We may need to split page tables later on if dcache settings change,
  305. * so reserve up to 4 (random pick) page tables for that.
  306. */
  307. size += one_pt * 4;
  308. return size;
  309. }
  310. void setup_pgtables(void)
  311. {
  312. int i;
  313. if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
  314. panic("Page table pointer not setup.");
  315. /*
  316. * Allocate the first level we're on with invalidate entries.
  317. * If the starting level is 0 (va_bits >= 39), then this is our
  318. * Lv0 page table, otherwise it's the entry Lv1 page table.
  319. */
  320. create_table();
  321. /* Now add all MMU table entries one after another to the table */
  322. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  323. add_map(&mem_map[i]);
  324. }
  325. static void setup_all_pgtables(void)
  326. {
  327. u64 tlb_addr = gd->arch.tlb_addr;
  328. u64 tlb_size = gd->arch.tlb_size;
  329. /* Reset the fill ptr */
  330. gd->arch.tlb_fillptr = tlb_addr;
  331. /* Create normal system page tables */
  332. setup_pgtables();
  333. /* Create emergency page tables */
  334. gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
  335. (uintptr_t)gd->arch.tlb_addr;
  336. gd->arch.tlb_addr = gd->arch.tlb_fillptr;
  337. setup_pgtables();
  338. gd->arch.tlb_emerg = gd->arch.tlb_addr;
  339. gd->arch.tlb_addr = tlb_addr;
  340. gd->arch.tlb_size = tlb_size;
  341. }
  342. /* to activate the MMU we need to set up virtual memory */
  343. __weak void mmu_setup(void)
  344. {
  345. int el;
  346. /* Set up page tables only once */
  347. if (!gd->arch.tlb_fillptr)
  348. setup_all_pgtables();
  349. el = current_el();
  350. set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
  351. MEMORY_ATTRIBUTES);
  352. /* enable the mmu */
  353. set_sctlr(get_sctlr() | CR_M);
  354. }
  355. /*
  356. * Performs a invalidation of the entire data cache at all levels
  357. */
  358. void invalidate_dcache_all(void)
  359. {
  360. __asm_invalidate_dcache_all();
  361. __asm_invalidate_l3_dcache();
  362. }
  363. /*
  364. * Performs a clean & invalidation of the entire data cache at all levels.
  365. * This function needs to be inline to avoid using stack.
  366. * __asm_flush_l3_dcache return status of timeout
  367. */
  368. inline void flush_dcache_all(void)
  369. {
  370. int ret;
  371. __asm_flush_dcache_all();
  372. ret = __asm_flush_l3_dcache();
  373. if (ret)
  374. debug("flushing dcache returns 0x%x\n", ret);
  375. else
  376. debug("flushing dcache successfully.\n");
  377. }
  378. #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
  379. /*
  380. * Invalidates range in all levels of D-cache/unified cache
  381. */
  382. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  383. {
  384. __asm_invalidate_dcache_range(start, stop);
  385. }
  386. /*
  387. * Flush range(clean & invalidate) from all levels of D-cache/unified cache
  388. */
  389. void flush_dcache_range(unsigned long start, unsigned long stop)
  390. {
  391. __asm_flush_dcache_range(start, stop);
  392. }
  393. #else
  394. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  395. {
  396. }
  397. void flush_dcache_range(unsigned long start, unsigned long stop)
  398. {
  399. }
  400. #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
  401. void dcache_enable(void)
  402. {
  403. /* The data cache is not active unless the mmu is enabled */
  404. if (!(get_sctlr() & CR_M)) {
  405. invalidate_dcache_all();
  406. __asm_invalidate_tlb_all();
  407. mmu_setup();
  408. }
  409. set_sctlr(get_sctlr() | CR_C);
  410. }
  411. void dcache_disable(void)
  412. {
  413. uint32_t sctlr;
  414. sctlr = get_sctlr();
  415. /* if cache isn't enabled no need to disable */
  416. if (!(sctlr & CR_C))
  417. return;
  418. set_sctlr(sctlr & ~(CR_C|CR_M));
  419. flush_dcache_all();
  420. __asm_invalidate_tlb_all();
  421. }
  422. int dcache_status(void)
  423. {
  424. return (get_sctlr() & CR_C) != 0;
  425. }
  426. u64 *__weak arch_get_page_table(void) {
  427. puts("No page table offset defined\n");
  428. return NULL;
  429. }
  430. static bool is_aligned(u64 addr, u64 size, u64 align)
  431. {
  432. return !(addr & (align - 1)) && !(size & (align - 1));
  433. }
  434. /* Use flag to indicate if attrs has more than d-cache attributes */
  435. static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
  436. {
  437. int levelshift = level2shift(level);
  438. u64 levelsize = 1ULL << levelshift;
  439. u64 *pte = find_pte(start, level);
  440. /* Can we can just modify the current level block PTE? */
  441. if (is_aligned(start, size, levelsize)) {
  442. if (flag) {
  443. *pte &= ~PMD_ATTRMASK;
  444. *pte |= attrs & PMD_ATTRMASK;
  445. } else {
  446. *pte &= ~PMD_ATTRINDX_MASK;
  447. *pte |= attrs & PMD_ATTRINDX_MASK;
  448. }
  449. debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
  450. return levelsize;
  451. }
  452. /* Unaligned or doesn't fit, maybe split block into table */
  453. debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
  454. /* Maybe we need to split the block into a table */
  455. if (pte_type(pte) == PTE_TYPE_BLOCK)
  456. split_block(pte, level);
  457. /* And then double-check it became a table or already is one */
  458. if (pte_type(pte) != PTE_TYPE_TABLE)
  459. panic("PTE %p (%llx) for addr=%llx should be a table",
  460. pte, *pte, start);
  461. /* Roll on to the next page table level */
  462. return 0;
  463. }
  464. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  465. enum dcache_option option)
  466. {
  467. u64 attrs = PMD_ATTRINDX(option);
  468. u64 real_start = start;
  469. u64 real_size = size;
  470. debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
  471. if (!gd->arch.tlb_emerg)
  472. panic("Emergency page table not setup.");
  473. /*
  474. * We can not modify page tables that we're currently running on,
  475. * so we first need to switch to the "emergency" page tables where
  476. * we can safely modify our primary page tables and then switch back
  477. */
  478. __asm_switch_ttbr(gd->arch.tlb_emerg);
  479. /*
  480. * Loop through the address range until we find a page granule that fits
  481. * our alignment constraints, then set it to the new cache attributes
  482. */
  483. while (size > 0) {
  484. int level;
  485. u64 r;
  486. for (level = 1; level < 4; level++) {
  487. /* Set d-cache attributes only */
  488. r = set_one_region(start, size, attrs, false, level);
  489. if (r) {
  490. /* PTE successfully replaced */
  491. size -= r;
  492. start += r;
  493. break;
  494. }
  495. }
  496. }
  497. /* We're done modifying page tables, switch back to our primary ones */
  498. __asm_switch_ttbr(gd->arch.tlb_addr);
  499. /*
  500. * Make sure there's nothing stale in dcache for a region that might
  501. * have caches off now
  502. */
  503. flush_dcache_range(real_start, real_start + real_size);
  504. }
  505. /*
  506. * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
  507. * The procecess is break-before-make. The target region will be marked as
  508. * invalid during the process of changing.
  509. */
  510. void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
  511. {
  512. int level;
  513. u64 r, size, start;
  514. start = addr;
  515. size = siz;
  516. /*
  517. * Loop through the address range until we find a page granule that fits
  518. * our alignment constraints, then set it to "invalid".
  519. */
  520. while (size > 0) {
  521. for (level = 1; level < 4; level++) {
  522. /* Set PTE to fault */
  523. r = set_one_region(start, size, PTE_TYPE_FAULT, true,
  524. level);
  525. if (r) {
  526. /* PTE successfully invalidated */
  527. size -= r;
  528. start += r;
  529. break;
  530. }
  531. }
  532. }
  533. flush_dcache_range(gd->arch.tlb_addr,
  534. gd->arch.tlb_addr + gd->arch.tlb_size);
  535. __asm_invalidate_tlb_all();
  536. /*
  537. * Loop through the address range until we find a page granule that fits
  538. * our alignment constraints, then set it to the new cache attributes
  539. */
  540. start = addr;
  541. size = siz;
  542. while (size > 0) {
  543. for (level = 1; level < 4; level++) {
  544. /* Set PTE to new attributes */
  545. r = set_one_region(start, size, attrs, true, level);
  546. if (r) {
  547. /* PTE successfully updated */
  548. size -= r;
  549. start += r;
  550. break;
  551. }
  552. }
  553. }
  554. flush_dcache_range(gd->arch.tlb_addr,
  555. gd->arch.tlb_addr + gd->arch.tlb_size);
  556. __asm_invalidate_tlb_all();
  557. }
  558. #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  559. /*
  560. * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
  561. * running however really wants to have dcache and the MMU active. Check that
  562. * everything is sane and give the developer a hint if it isn't.
  563. */
  564. #ifndef CONFIG_SPL_BUILD
  565. #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
  566. #endif
  567. void invalidate_dcache_all(void)
  568. {
  569. }
  570. void flush_dcache_all(void)
  571. {
  572. }
  573. void dcache_enable(void)
  574. {
  575. }
  576. void dcache_disable(void)
  577. {
  578. }
  579. int dcache_status(void)
  580. {
  581. return 0;
  582. }
  583. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  584. enum dcache_option option)
  585. {
  586. }
  587. #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  588. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  589. void icache_enable(void)
  590. {
  591. invalidate_icache_all();
  592. set_sctlr(get_sctlr() | CR_I);
  593. }
  594. void icache_disable(void)
  595. {
  596. set_sctlr(get_sctlr() & ~CR_I);
  597. }
  598. int icache_status(void)
  599. {
  600. return (get_sctlr() & CR_I) != 0;
  601. }
  602. void invalidate_icache_all(void)
  603. {
  604. __asm_invalidate_icache_all();
  605. __asm_invalidate_l3_icache();
  606. }
  607. #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  608. void icache_enable(void)
  609. {
  610. }
  611. void icache_disable(void)
  612. {
  613. }
  614. int icache_status(void)
  615. {
  616. return 0;
  617. }
  618. void invalidate_icache_all(void)
  619. {
  620. }
  621. #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  622. /*
  623. * Enable dCache & iCache, whether cache is actually enabled
  624. * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
  625. */
  626. void __weak enable_caches(void)
  627. {
  628. icache_enable();
  629. dcache_enable();
  630. }