soc.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/arch/immap_ls102xa.h>
  11. #include <asm/arch/ls102xa_soc.h>
  12. #include <asm/arch/ls102xa_stream_id.h>
  13. #include <fsl_csu.h>
  14. #include <fsl_ddr_sdram.h>
  15. struct liodn_id_table sec_liodn_tbl[] = {
  16. SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  17. SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  18. SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  19. SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  20. SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  21. SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  22. SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  23. SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  24. SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  25. SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  26. SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  27. SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  28. SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  29. SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  30. SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  31. SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  32. };
  33. struct smmu_stream_id dev_stream_id[] = {
  34. { 0x100, 0x01, "ETSEC MAC1" },
  35. { 0x104, 0x02, "ETSEC MAC2" },
  36. { 0x108, 0x03, "ETSEC MAC3" },
  37. { 0x10c, 0x04, "PEX1" },
  38. { 0x110, 0x05, "PEX2" },
  39. { 0x114, 0x06, "qDMA" },
  40. { 0x118, 0x07, "SATA" },
  41. { 0x11c, 0x08, "USB3" },
  42. { 0x120, 0x09, "QE" },
  43. { 0x124, 0x0a, "eSDHC" },
  44. { 0x128, 0x0b, "eMA" },
  45. { 0x14c, 0x0c, "2D-ACE" },
  46. { 0x150, 0x0d, "USB2" },
  47. { 0x18c, 0x0e, "DEBUG" },
  48. };
  49. unsigned int get_soc_major_rev(void)
  50. {
  51. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  52. unsigned int svr, major;
  53. svr = in_be32(&gur->svr);
  54. major = SVR_MAJ(svr);
  55. return major;
  56. }
  57. static void erratum_a009008(void)
  58. {
  59. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  60. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  61. clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  62. 0xF << 6,
  63. SCFG_USB_TXVREFTUNE << 6);
  64. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  65. }
  66. static void erratum_a009798(void)
  67. {
  68. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  69. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  70. clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  71. SCFG_USB_SQRXTUNE_MASK << 23);
  72. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  73. }
  74. static void erratum_a008997(void)
  75. {
  76. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  77. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  78. clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
  79. SCFG_USB_PCSTXSWINGFULL_MASK,
  80. SCFG_USB_PCSTXSWINGFULL_VAL);
  81. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  82. }
  83. static void erratum_a009007(void)
  84. {
  85. #ifdef CONFIG_SYS_FSL_ERRATUM_A009007
  86. void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
  87. out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
  88. out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
  89. out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
  90. out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
  91. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  92. }
  93. static void erratum_a008850_early(void)
  94. {
  95. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  96. /* part 1 of 2 */
  97. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  98. CONFIG_SYS_CCI400_OFFSET);
  99. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  100. /* disables propagation of barrier transactions to DDRC from CCI400 */
  101. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  102. /* disable the re-ordering in DDRC */
  103. out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  104. #endif
  105. }
  106. void erratum_a008850_post(void)
  107. {
  108. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  109. /* part 2 of 2 */
  110. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  111. CONFIG_SYS_CCI400_OFFSET);
  112. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  113. u32 tmp;
  114. /* enable propagation of barrier transactions to DDRC from CCI400 */
  115. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  116. /* enable the re-ordering in DDRC */
  117. tmp = in_be32(&ddr->eor);
  118. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  119. out_be32(&ddr->eor, tmp);
  120. #endif
  121. }
  122. void s_init(void)
  123. {
  124. }
  125. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  126. void erratum_a010315(void)
  127. {
  128. int i;
  129. for (i = PCIE1; i <= PCIE2; i++)
  130. if (!is_serdes_configured(i)) {
  131. debug("PCIe%d: disabled all R/W permission!\n", i);
  132. set_pcie_ns_access(i, 0);
  133. }
  134. }
  135. #endif
  136. int arch_soc_init(void)
  137. {
  138. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  139. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  140. CONFIG_SYS_CCI400_OFFSET);
  141. unsigned int major;
  142. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  143. enable_layerscape_ns_access();
  144. #endif
  145. #ifdef CONFIG_FSL_QSPI
  146. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  147. #endif
  148. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  149. out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
  150. #endif
  151. /* Configure Little endian for SAI, ASRC and SPDIF */
  152. out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
  153. /*
  154. * Enable snoop requests and DVM message requests for
  155. * All the slave insterfaces.
  156. */
  157. out_le32(&cci->slave[0].snoop_ctrl,
  158. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  159. out_le32(&cci->slave[1].snoop_ctrl,
  160. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  161. out_le32(&cci->slave[2].snoop_ctrl,
  162. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  163. out_le32(&cci->slave[4].snoop_ctrl,
  164. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  165. major = get_soc_major_rev();
  166. if (major == SOC_MAJOR_VER_1_0) {
  167. /*
  168. * Set CCI-400 Slave interface S1, S2 Shareable Override
  169. * Register All transactions are treated as non-shareable
  170. */
  171. out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
  172. out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
  173. }
  174. /* Enable all the snoop signal for various masters */
  175. out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
  176. SCFG_SNPCNFGCR_DCU_RD_WR |
  177. SCFG_SNPCNFGCR_SATA_RD_WR |
  178. SCFG_SNPCNFGCR_USB3_RD_WR |
  179. SCFG_SNPCNFGCR_DBG_RD_WR |
  180. SCFG_SNPCNFGCR_EDMA_SNP);
  181. /*
  182. * Memory controller require a register write before being enabled.
  183. * Affects: DDR
  184. * Register: EDDRTQCFG
  185. * Description: Memory controller performance is not optimal with
  186. * default internal target queue register values.
  187. * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
  188. */
  189. out_be32(&scfg->eddrtqcfg, 0x63b20042);
  190. /* Erratum */
  191. erratum_a008850_early();
  192. erratum_a009008();
  193. erratum_a009798();
  194. erratum_a008997();
  195. erratum_a009007();
  196. return 0;
  197. }
  198. int ls102xa_smmu_stream_id_init(void)
  199. {
  200. ls1021x_config_caam_stream_id(sec_liodn_tbl,
  201. ARRAY_SIZE(sec_liodn_tbl));
  202. ls102xa_config_smmu_stream_id(dev_stream_id,
  203. ARRAY_SIZE(dev_stream_id));
  204. return 0;
  205. }