clk-core.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Broadcom Corporation.
  4. */
  5. #include <linux/stddef.h>
  6. #ifdef CONFIG_CLK_DEBUG
  7. #undef writel
  8. #undef readl
  9. static inline void writel(u32 val, void *addr)
  10. {
  11. printf("Write [0x%p] = 0x%08x\n", addr, val);
  12. *(u32 *)addr = val;
  13. }
  14. static inline u32 readl(void *addr)
  15. {
  16. u32 val = *(u32 *)addr;
  17. printf("Read [0x%p] = 0x%08x\n", addr, val);
  18. return val;
  19. }
  20. #endif
  21. struct clk;
  22. struct clk_lookup {
  23. const char *dev_id;
  24. const char *con_id;
  25. struct clk *clk;
  26. };
  27. extern struct clk_lookup arch_clk_tbl[];
  28. extern unsigned int arch_clk_tbl_array_size;
  29. /**
  30. * struct clk_ops - standard clock operations
  31. * @enable: enable/disable clock, see clk_enable() and clk_disable()
  32. * @set_rate: set the clock rate, see clk_set_rate().
  33. * @get_rate: get the clock rate, see clk_get_rate().
  34. * @round_rate: round a given clock rate, see clk_round_rate().
  35. * @set_parent: set the clock's parent, see clk_set_parent().
  36. *
  37. * Group the common clock implementations together so that we
  38. * don't have to keep setting the same fiels again. We leave
  39. * enable in struct clk.
  40. *
  41. */
  42. struct clk_ops {
  43. int (*enable) (struct clk *c, int enable);
  44. int (*set_rate) (struct clk *c, unsigned long rate);
  45. unsigned long (*get_rate) (struct clk *c);
  46. unsigned long (*round_rate) (struct clk *c, unsigned long rate);
  47. int (*set_parent) (struct clk *c, struct clk *parent);
  48. };
  49. struct clk {
  50. struct clk *parent;
  51. const char *name;
  52. int use_cnt;
  53. unsigned long rate; /* in HZ */
  54. /* programmable divider. 0 means fixed ratio to parent clock */
  55. unsigned long div;
  56. struct clk_src *src;
  57. struct clk_ops *ops;
  58. unsigned long ccu_clk_mgr_base;
  59. int sel;
  60. };
  61. struct refclk *refclk_str_to_clk(const char *name);
  62. /* The common clock framework uses u8 to represent a parent index */
  63. #define PARENT_COUNT_MAX ((u32)U8_MAX)
  64. #define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
  65. #define BAD_CLK_NAME ((const char *)-1)
  66. #define BAD_SCALED_DIV_VALUE U64_MAX
  67. /*
  68. * Utility macros for object flag management. If possible, flags
  69. * should be defined such that 0 is the desired default value.
  70. */
  71. #define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
  72. #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
  73. #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
  74. #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
  75. #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
  76. /* Clock field state tests */
  77. #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
  78. #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
  79. #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
  80. #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
  81. #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
  82. #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
  83. #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
  84. #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
  85. #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
  86. #define divider_has_fraction(div) (!divider_is_fixed(div) && \
  87. (div)->frac_width > 0)
  88. #define selector_exists(sel) ((sel)->width != 0)
  89. #define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
  90. /* Clock type, used to tell common block what it's part of */
  91. enum bcm_clk_type {
  92. bcm_clk_none, /* undefined clock type */
  93. bcm_clk_bus,
  94. bcm_clk_core,
  95. bcm_clk_peri
  96. };
  97. /*
  98. * Gating control and status is managed by a 32-bit gate register.
  99. *
  100. * There are several types of gating available:
  101. * - (no gate)
  102. * A clock with no gate is assumed to be always enabled.
  103. * - hardware-only gating (auto-gating)
  104. * Enabling or disabling clocks with this type of gate is
  105. * managed automatically by the hardware. Such clocks can be
  106. * considered by the software to be enabled. The current status
  107. * of auto-gated clocks can be read from the gate status bit.
  108. * - software-only gating
  109. * Auto-gating is not available for this type of clock.
  110. * Instead, software manages whether it's enabled by setting or
  111. * clearing the enable bit. The current gate status of a gate
  112. * under software control can be read from the gate status bit.
  113. * To ensure a change to the gating status is complete, the
  114. * status bit can be polled to verify that the gate has entered
  115. * the desired state.
  116. * - selectable hardware or software gating
  117. * Gating for this type of clock can be configured to be either
  118. * under software or hardware control. Which type is in use is
  119. * determined by the hw_sw_sel bit of the gate register.
  120. */
  121. struct bcm_clk_gate {
  122. u32 offset; /* gate register offset */
  123. u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
  124. u32 en_bit; /* 0: disable; 1: enable */
  125. u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
  126. u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
  127. };
  128. /*
  129. * Gate flags:
  130. * HW means this gate can be auto-gated
  131. * SW means the state of this gate can be software controlled
  132. * NO_DISABLE means this gate is (only) enabled if under software control
  133. * SW_MANAGED means the status of this gate is under software control
  134. * ENABLED means this software-managed gate is *supposed* to be enabled
  135. */
  136. #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
  137. #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
  138. #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
  139. #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
  140. #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
  141. #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
  142. /*
  143. * Gate initialization macros.
  144. *
  145. * Any gate initially under software control will be enabled.
  146. */
  147. /* A hardware/software gate initially under software control */
  148. #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
  149. { \
  150. .offset = (_offset), \
  151. .status_bit = (_status_bit), \
  152. .en_bit = (_en_bit), \
  153. .hw_sw_sel_bit = (_hw_sw_sel_bit), \
  154. .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
  155. FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
  156. FLAG(GATE, EXISTS), \
  157. }
  158. /* A hardware/software gate initially under hardware control */
  159. #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
  160. { \
  161. .offset = (_offset), \
  162. .status_bit = (_status_bit), \
  163. .en_bit = (_en_bit), \
  164. .hw_sw_sel_bit = (_hw_sw_sel_bit), \
  165. .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
  166. FLAG(GATE, EXISTS), \
  167. }
  168. /* A hardware-or-enabled gate (enabled if not under hardware control) */
  169. #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
  170. { \
  171. .offset = (_offset), \
  172. .status_bit = (_status_bit), \
  173. .en_bit = (_en_bit), \
  174. .hw_sw_sel_bit = (_hw_sw_sel_bit), \
  175. .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
  176. FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
  177. }
  178. /* A software-only gate */
  179. #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
  180. { \
  181. .offset = (_offset), \
  182. .status_bit = (_status_bit), \
  183. .en_bit = (_en_bit), \
  184. .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
  185. FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
  186. }
  187. /* A hardware-only gate */
  188. #define HW_ONLY_GATE(_offset, _status_bit) \
  189. { \
  190. .offset = (_offset), \
  191. .status_bit = (_status_bit), \
  192. .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
  193. }
  194. /*
  195. * Each clock can have zero, one, or two dividers which change the
  196. * output rate of the clock. Each divider can be either fixed or
  197. * variable. If there are two dividers, they are the "pre-divider"
  198. * and the "regular" or "downstream" divider. If there is only one,
  199. * there is no pre-divider.
  200. *
  201. * A fixed divider is any non-zero (positive) value, and it
  202. * indicates how the input rate is affected by the divider.
  203. *
  204. * The value of a variable divider is maintained in a sub-field of a
  205. * 32-bit divider register. The position of the field in the
  206. * register is defined by its offset and width. The value recorded
  207. * in this field is always 1 less than the value it represents.
  208. *
  209. * In addition, a variable divider can indicate that some subset
  210. * of its bits represent a "fractional" part of the divider. Such
  211. * bits comprise the low-order portion of the divider field, and can
  212. * be viewed as representing the portion of the divider that lies to
  213. * the right of the decimal point. Most variable dividers have zero
  214. * fractional bits. Variable dividers with non-zero fraction width
  215. * still record a value 1 less than the value they represent; the
  216. * added 1 does *not* affect the low-order bit in this case, it
  217. * affects the bits above the fractional part only. (Often in this
  218. * code a divider field value is distinguished from the value it
  219. * represents by referring to the latter as a "divisor".)
  220. *
  221. * In order to avoid dealing with fractions, divider arithmetic is
  222. * performed using "scaled" values. A scaled value is one that's
  223. * been left-shifted by the fractional width of a divider. Dividing
  224. * a scaled value by a scaled divisor produces the desired quotient
  225. * without loss of precision and without any other special handling
  226. * for fractions.
  227. *
  228. * The recorded value of a variable divider can be modified. To
  229. * modify either divider (or both), a clock must be enabled (i.e.,
  230. * using its gate). In addition, a trigger register (described
  231. * below) must be used to commit the change, and polled to verify
  232. * the change is complete.
  233. */
  234. struct bcm_clk_div {
  235. union {
  236. struct { /* variable divider */
  237. u32 offset; /* divider register offset */
  238. u32 shift; /* field shift */
  239. u32 width; /* field width */
  240. u32 frac_width; /* field fraction width */
  241. u64 scaled_div; /* scaled divider value */
  242. };
  243. u32 fixed; /* non-zero fixed divider value */
  244. };
  245. u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
  246. };
  247. /*
  248. * Divider flags:
  249. * EXISTS means this divider exists
  250. * FIXED means it is a fixed-rate divider
  251. */
  252. #define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
  253. #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
  254. /* Divider initialization macros */
  255. /* A fixed (non-zero) divider */
  256. #define FIXED_DIVIDER(_value) \
  257. { \
  258. .fixed = (_value), \
  259. .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
  260. }
  261. /* A divider with an integral divisor */
  262. #define DIVIDER(_offset, _shift, _width) \
  263. { \
  264. .offset = (_offset), \
  265. .shift = (_shift), \
  266. .width = (_width), \
  267. .scaled_div = BAD_SCALED_DIV_VALUE, \
  268. .flags = FLAG(DIV, EXISTS), \
  269. }
  270. /* A divider whose divisor has an integer and fractional part */
  271. #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
  272. { \
  273. .offset = (_offset), \
  274. .shift = (_shift), \
  275. .width = (_width), \
  276. .frac_width = (_frac_width), \
  277. .scaled_div = BAD_SCALED_DIV_VALUE, \
  278. .flags = FLAG(DIV, EXISTS), \
  279. }
  280. /*
  281. * Clocks may have multiple "parent" clocks. If there is more than
  282. * one, a selector must be specified to define which of the parent
  283. * clocks is currently in use. The selected clock is indicated in a
  284. * sub-field of a 32-bit selector register. The range of
  285. * representable selector values typically exceeds the number of
  286. * available parent clocks. Occasionally the reset value of a
  287. * selector field is explicitly set to a (specific) value that does
  288. * not correspond to a defined input clock.
  289. *
  290. * We register all known parent clocks with the common clock code
  291. * using a packed array (i.e., no empty slots) of (parent) clock
  292. * names, and refer to them later using indexes into that array.
  293. * We maintain an array of selector values indexed by common clock
  294. * index values in order to map between these common clock indexes
  295. * and the selector values used by the hardware.
  296. *
  297. * Like dividers, a selector can be modified, but to do so a clock
  298. * must be enabled, and a trigger must be used to commit the change.
  299. */
  300. struct bcm_clk_sel {
  301. u32 offset; /* selector register offset */
  302. u32 shift; /* field shift */
  303. u32 width; /* field width */
  304. u32 parent_count; /* number of entries in parent_sel[] */
  305. u32 *parent_sel; /* array of parent selector values */
  306. u8 clk_index; /* current selected index in parent_sel[] */
  307. };
  308. /* Selector initialization macro */
  309. #define SELECTOR(_offset, _shift, _width) \
  310. { \
  311. .offset = (_offset), \
  312. .shift = (_shift), \
  313. .width = (_width), \
  314. .clk_index = BAD_CLK_INDEX, \
  315. }
  316. /*
  317. * Making changes to a variable divider or a selector for a clock
  318. * requires the use of a trigger. A trigger is defined by a single
  319. * bit within a register. To signal a change, a 1 is written into
  320. * that bit. To determine when the change has been completed, that
  321. * trigger bit is polled; the read value will be 1 while the change
  322. * is in progress, and 0 when it is complete.
  323. *
  324. * Occasionally a clock will have more than one trigger. In this
  325. * case, the "pre-trigger" will be used when changing a clock's
  326. * selector and/or its pre-divider.
  327. */
  328. struct bcm_clk_trig {
  329. u32 offset; /* trigger register offset */
  330. u32 bit; /* trigger bit */
  331. u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
  332. };
  333. /*
  334. * Trigger flags:
  335. * EXISTS means this trigger exists
  336. */
  337. #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
  338. /* Trigger initialization macro */
  339. #define TRIGGER(_offset, _bit) \
  340. { \
  341. .offset = (_offset), \
  342. .bit = (_bit), \
  343. .flags = FLAG(TRIG, EXISTS), \
  344. }
  345. struct bus_clk_data {
  346. struct bcm_clk_gate gate;
  347. };
  348. struct core_clk_data {
  349. struct bcm_clk_gate gate;
  350. };
  351. struct peri_clk_data {
  352. struct bcm_clk_gate gate;
  353. struct bcm_clk_trig pre_trig;
  354. struct bcm_clk_div pre_div;
  355. struct bcm_clk_trig trig;
  356. struct bcm_clk_div div;
  357. struct bcm_clk_sel sel;
  358. const char *clocks[]; /* must be last; use CLOCKS() to declare */
  359. };
  360. #define CLOCKS(...) { __VA_ARGS__, NULL, }
  361. #define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
  362. struct refclk {
  363. struct clk clk;
  364. };
  365. struct peri_clock {
  366. struct clk clk;
  367. struct peri_clk_data *data;
  368. };
  369. struct ccu_clock {
  370. struct clk clk;
  371. int num_policy_masks;
  372. unsigned long policy_freq_offset;
  373. int freq_bit_shift; /* 8 for most CCUs */
  374. unsigned long policy_ctl_offset;
  375. unsigned long policy0_mask_offset;
  376. unsigned long policy1_mask_offset;
  377. unsigned long policy2_mask_offset;
  378. unsigned long policy3_mask_offset;
  379. unsigned long policy0_mask2_offset;
  380. unsigned long policy1_mask2_offset;
  381. unsigned long policy2_mask2_offset;
  382. unsigned long policy3_mask2_offset;
  383. unsigned long lvm_en_offset;
  384. int freq_id;
  385. unsigned long *freq_tbl;
  386. };
  387. struct bus_clock {
  388. struct clk clk;
  389. struct bus_clk_data *data;
  390. unsigned long *freq_tbl;
  391. };
  392. struct ref_clock {
  393. struct clk clk;
  394. };
  395. static inline int is_same_clock(struct clk *a, struct clk *b)
  396. {
  397. return (a == b);
  398. }
  399. #define to_clk(p) (&((p)->clk))
  400. #define name_to_clk(name) (&((name##_clk).clk))
  401. /* declare a struct clk_lookup */
  402. #define CLK_LK(name) \
  403. {.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
  404. static inline struct refclk *to_refclk(struct clk *clock)
  405. {
  406. return container_of(clock, struct refclk, clk);
  407. }
  408. static inline struct peri_clock *to_peri_clk(struct clk *clock)
  409. {
  410. return container_of(clock, struct peri_clock, clk);
  411. }
  412. static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
  413. {
  414. return container_of(clock, struct ccu_clock, clk);
  415. }
  416. static inline struct bus_clock *to_bus_clk(struct clk *clock)
  417. {
  418. return container_of(clock, struct bus_clock, clk);
  419. }
  420. static inline struct ref_clock *to_ref_clk(struct clk *clock)
  421. {
  422. return container_of(clock, struct ref_clock, clk);
  423. }
  424. extern struct clk_ops peri_clk_ops;
  425. extern struct clk_ops ccu_clk_ops;
  426. extern struct clk_ops bus_clk_ops;
  427. extern struct clk_ops ref_clk_ops;
  428. extern int clk_get_and_enable(char *clkstr);