clk-core.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Broadcom Corporation.
  4. */
  5. /*
  6. *
  7. * bcm235xx architecture clock framework
  8. *
  9. */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <linux/errno.h>
  14. #include <bitfield.h>
  15. #include <asm/arch/sysmap.h>
  16. #include <asm/kona-common/clk.h>
  17. #include "clk-core.h"
  18. #define CLK_WR_ACCESS_PASSWORD 0x00a5a501
  19. #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
  20. #define POLICY_CTL_GO 1 /* Load and refresh policy masks */
  21. #define POLICY_CTL_GO_ATL 4 /* Active Load */
  22. /* Helper function */
  23. int clk_get_and_enable(char *clkstr)
  24. {
  25. int ret = 0;
  26. struct clk *c;
  27. debug("%s: %s\n", __func__, clkstr);
  28. c = clk_get(clkstr);
  29. if (c) {
  30. ret = clk_enable(c);
  31. if (ret)
  32. return ret;
  33. } else {
  34. printf("%s: Couldn't find %s\n", __func__, clkstr);
  35. return -EINVAL;
  36. }
  37. return ret;
  38. }
  39. /*
  40. * Poll a register in a CCU's address space, returning when the
  41. * specified bit in that register's value is set (or clear). Delay
  42. * a microsecond after each read of the register. Returns true if
  43. * successful, or false if we gave up trying.
  44. *
  45. * Caller must ensure the CCU lock is held.
  46. */
  47. #define CLK_GATE_DELAY_USEC 2000
  48. static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
  49. {
  50. unsigned int tries;
  51. u32 bit_mask = 1 << bit;
  52. for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
  53. u32 val;
  54. bool bit_val;
  55. val = readl(base + offset);
  56. bit_val = (val & bit_mask) ? 1 : 0;
  57. if (bit_val == want)
  58. return 0; /* success */
  59. udelay(1);
  60. }
  61. debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
  62. __func__, base + offset, bit, want);
  63. return -ETIMEDOUT;
  64. }
  65. /* Enable a peripheral clock */
  66. static int peri_clk_enable(struct clk *c, int enable)
  67. {
  68. int ret = 0;
  69. u32 reg;
  70. struct peri_clock *peri_clk = to_peri_clk(c);
  71. struct peri_clk_data *cd = peri_clk->data;
  72. struct bcm_clk_gate *gate = &cd->gate;
  73. void *base = (void *)c->ccu_clk_mgr_base;
  74. debug("%s: %s\n", __func__, c->name);
  75. clk_get_rate(c); /* Make sure rate and sel are filled in */
  76. /* enable access */
  77. writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
  78. if (enable) {
  79. debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
  80. __func__, c->name, c->rate, c->div, c->sel,
  81. c->parent->rate);
  82. /*
  83. * clkgate - only software controllable gates are
  84. * supported by u-boot which includes all clocks
  85. * that matter. This avoids bringing in a lot of extra
  86. * complexity as done in the kernel framework.
  87. */
  88. if (gate_exists(gate)) {
  89. reg = readl(base + cd->gate.offset);
  90. reg |= (1 << cd->gate.en_bit);
  91. writel(reg, base + cd->gate.offset);
  92. }
  93. /* div and pll select */
  94. if (divider_exists(&cd->div)) {
  95. reg = readl(base + cd->div.offset);
  96. bitfield_replace(reg, cd->div.shift, cd->div.width,
  97. c->div - 1);
  98. writel(reg, base + cd->div.offset);
  99. }
  100. /* frequency selector */
  101. if (selector_exists(&cd->sel)) {
  102. reg = readl(base + cd->sel.offset);
  103. bitfield_replace(reg, cd->sel.shift, cd->sel.width,
  104. c->sel);
  105. writel(reg, base + cd->sel.offset);
  106. }
  107. /* trigger */
  108. if (trigger_exists(&cd->trig)) {
  109. writel((1 << cd->trig.bit), base + cd->trig.offset);
  110. /* wait for trigger status bit to go to 0 */
  111. ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
  112. if (ret)
  113. return ret;
  114. }
  115. /* wait for running (status_bit = 1) */
  116. ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
  117. if (ret)
  118. return ret;
  119. } else {
  120. debug("%s disable clock %s\n", __func__, c->name);
  121. /* clkgate */
  122. reg = readl(base + cd->gate.offset);
  123. reg &= ~(1 << cd->gate.en_bit);
  124. writel(reg, base + cd->gate.offset);
  125. /* wait for stop (status_bit = 0) */
  126. ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
  127. }
  128. /* disable access */
  129. writel(0, base + WR_ACCESS_OFFSET);
  130. return ret;
  131. }
  132. /* Set the rate of a peripheral clock */
  133. static int peri_clk_set_rate(struct clk *c, unsigned long rate)
  134. {
  135. int ret = 0;
  136. int i;
  137. unsigned long diff;
  138. unsigned long new_rate = 0, div = 1;
  139. struct peri_clock *peri_clk = to_peri_clk(c);
  140. struct peri_clk_data *cd = peri_clk->data;
  141. const char **clock;
  142. debug("%s: %s\n", __func__, c->name);
  143. diff = rate;
  144. i = 0;
  145. for (clock = cd->clocks; *clock; clock++, i++) {
  146. struct refclk *ref = refclk_str_to_clk(*clock);
  147. if (!ref) {
  148. printf("%s: Lookup of %s failed\n", __func__, *clock);
  149. return -EINVAL;
  150. }
  151. /* round to the new rate */
  152. div = ref->clk.rate / rate;
  153. if (div == 0)
  154. div = 1;
  155. new_rate = ref->clk.rate / div;
  156. /* get the min diff */
  157. if (abs(new_rate - rate) < diff) {
  158. diff = abs(new_rate - rate);
  159. c->sel = i;
  160. c->parent = &ref->clk;
  161. c->rate = new_rate;
  162. c->div = div;
  163. }
  164. }
  165. debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
  166. c->name, c->rate, c->div, c->sel, c->parent->rate);
  167. return ret;
  168. }
  169. /* Get the rate of a peripheral clock */
  170. static unsigned long peri_clk_get_rate(struct clk *c)
  171. {
  172. struct peri_clock *peri_clk = to_peri_clk(c);
  173. struct peri_clk_data *cd = peri_clk->data;
  174. void *base = (void *)c->ccu_clk_mgr_base;
  175. int div = 1;
  176. const char **clock;
  177. struct refclk *ref;
  178. u32 reg;
  179. debug("%s: %s\n", __func__, c->name);
  180. if (selector_exists(&cd->sel)) {
  181. reg = readl(base + cd->sel.offset);
  182. c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
  183. } else {
  184. /*
  185. * For peri clocks that don't have a selector, the single
  186. * reference clock will always exist at index 0.
  187. */
  188. c->sel = 0;
  189. }
  190. if (divider_exists(&cd->div)) {
  191. reg = readl(base + cd->div.offset);
  192. div = bitfield_extract(reg, cd->div.shift, cd->div.width);
  193. div += 1;
  194. }
  195. clock = cd->clocks;
  196. ref = refclk_str_to_clk(clock[c->sel]);
  197. if (!ref) {
  198. printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
  199. return 0;
  200. }
  201. c->parent = &ref->clk;
  202. c->div = div;
  203. c->rate = c->parent->rate / c->div;
  204. debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
  205. c->parent->rate, div, c->sel, c->rate);
  206. return c->rate;
  207. }
  208. /* Peripheral clock operations */
  209. struct clk_ops peri_clk_ops = {
  210. .enable = peri_clk_enable,
  211. .set_rate = peri_clk_set_rate,
  212. .get_rate = peri_clk_get_rate,
  213. };
  214. /* Enable a CCU clock */
  215. static int ccu_clk_enable(struct clk *c, int enable)
  216. {
  217. struct ccu_clock *ccu_clk = to_ccu_clk(c);
  218. void *base = (void *)c->ccu_clk_mgr_base;
  219. int ret = 0;
  220. u32 reg;
  221. debug("%s: %s\n", __func__, c->name);
  222. if (!enable)
  223. return -EINVAL; /* CCU clock cannot shutdown */
  224. /* enable access */
  225. writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
  226. /* config enable for policy engine */
  227. writel(1, base + ccu_clk->lvm_en_offset);
  228. /* wait for bit to go to 0 */
  229. ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
  230. if (ret)
  231. return ret;
  232. /* freq ID */
  233. if (!ccu_clk->freq_bit_shift)
  234. ccu_clk->freq_bit_shift = 8;
  235. /* Set frequency id for each of the 4 policies */
  236. reg = ccu_clk->freq_id |
  237. (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
  238. (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
  239. (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
  240. writel(reg, base + ccu_clk->policy_freq_offset);
  241. /* enable all clock mask */
  242. writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
  243. writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
  244. writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
  245. writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
  246. if (ccu_clk->num_policy_masks == 2) {
  247. writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
  248. writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
  249. writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
  250. writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
  251. }
  252. /* start policy engine */
  253. reg = readl(base + ccu_clk->policy_ctl_offset);
  254. reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
  255. writel(reg, base + ccu_clk->policy_ctl_offset);
  256. /* wait till started */
  257. ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
  258. if (ret)
  259. return ret;
  260. /* disable access */
  261. writel(0, base + WR_ACCESS_OFFSET);
  262. return ret;
  263. }
  264. /* Get the CCU clock rate */
  265. static unsigned long ccu_clk_get_rate(struct clk *c)
  266. {
  267. struct ccu_clock *ccu_clk = to_ccu_clk(c);
  268. debug("%s: %s\n", __func__, c->name);
  269. c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
  270. return c->rate;
  271. }
  272. /* CCU clock operations */
  273. struct clk_ops ccu_clk_ops = {
  274. .enable = ccu_clk_enable,
  275. .get_rate = ccu_clk_get_rate,
  276. };
  277. /* Enable a bus clock */
  278. static int bus_clk_enable(struct clk *c, int enable)
  279. {
  280. struct bus_clock *bus_clk = to_bus_clk(c);
  281. struct bus_clk_data *cd = bus_clk->data;
  282. void *base = (void *)c->ccu_clk_mgr_base;
  283. int ret = 0;
  284. u32 reg;
  285. debug("%s: %s\n", __func__, c->name);
  286. /* enable access */
  287. writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
  288. /* enable gating */
  289. reg = readl(base + cd->gate.offset);
  290. if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
  291. debug("%s already %s\n", c->name,
  292. enable ? "enabled" : "disabled");
  293. else {
  294. int want = (enable) ? 1 : 0;
  295. reg |= (1 << cd->gate.hw_sw_sel_bit);
  296. if (enable)
  297. reg |= (1 << cd->gate.en_bit);
  298. else
  299. reg &= ~(1 << cd->gate.en_bit);
  300. writel(reg, base + cd->gate.offset);
  301. ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
  302. want);
  303. if (ret)
  304. return ret;
  305. }
  306. /* disable access */
  307. writel(0, base + WR_ACCESS_OFFSET);
  308. return ret;
  309. }
  310. /* Get the rate of a bus clock */
  311. static unsigned long bus_clk_get_rate(struct clk *c)
  312. {
  313. struct bus_clock *bus_clk = to_bus_clk(c);
  314. struct ccu_clock *ccu_clk;
  315. debug("%s: %s\n", __func__, c->name);
  316. ccu_clk = to_ccu_clk(c->parent);
  317. c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
  318. c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
  319. return c->rate;
  320. }
  321. /* Bus clock operations */
  322. struct clk_ops bus_clk_ops = {
  323. .enable = bus_clk_enable,
  324. .get_rate = bus_clk_get_rate,
  325. };
  326. /* Enable a reference clock */
  327. static int ref_clk_enable(struct clk *c, int enable)
  328. {
  329. debug("%s: %s\n", __func__, c->name);
  330. return 0;
  331. }
  332. /* Reference clock operations */
  333. struct clk_ops ref_clk_ops = {
  334. .enable = ref_clk_enable,
  335. };
  336. /*
  337. * clk.h implementation follows
  338. */
  339. /* Initialize the clock framework */
  340. int clk_init(void)
  341. {
  342. debug("%s:\n", __func__);
  343. return 0;
  344. }
  345. /* Get a clock handle, give a name string */
  346. struct clk *clk_get(const char *con_id)
  347. {
  348. int i;
  349. struct clk_lookup *clk_tblp;
  350. debug("%s: %s\n", __func__, con_id);
  351. clk_tblp = arch_clk_tbl;
  352. for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
  353. if (clk_tblp->con_id) {
  354. if (!con_id || strcmp(clk_tblp->con_id, con_id))
  355. continue;
  356. return clk_tblp->clk;
  357. }
  358. }
  359. return NULL;
  360. }
  361. /* Enable a clock */
  362. int clk_enable(struct clk *c)
  363. {
  364. int ret = 0;
  365. debug("%s: %s\n", __func__, c->name);
  366. if (!c->ops || !c->ops->enable)
  367. return -1;
  368. /* enable parent clock first */
  369. if (c->parent)
  370. ret = clk_enable(c->parent);
  371. if (ret)
  372. return ret;
  373. if (!c->use_cnt)
  374. ret = c->ops->enable(c, 1);
  375. c->use_cnt++;
  376. return ret;
  377. }
  378. /* Disable a clock */
  379. void clk_disable(struct clk *c)
  380. {
  381. debug("%s: %s\n", __func__, c->name);
  382. if (!c->ops || !c->ops->enable)
  383. return;
  384. if (c->use_cnt > 0) {
  385. c->use_cnt--;
  386. if (c->use_cnt == 0)
  387. c->ops->enable(c, 0);
  388. }
  389. /* disable parent */
  390. if (c->parent)
  391. clk_disable(c->parent);
  392. }
  393. /* Get the clock rate */
  394. unsigned long clk_get_rate(struct clk *c)
  395. {
  396. unsigned long rate;
  397. if (!c || !c->ops || !c->ops->get_rate)
  398. return 0;
  399. debug("%s: %s\n", __func__, c->name);
  400. rate = c->ops->get_rate(c);
  401. debug("%s: rate = %ld\n", __func__, rate);
  402. return rate;
  403. }
  404. /* Set the clock rate */
  405. int clk_set_rate(struct clk *c, unsigned long rate)
  406. {
  407. int ret;
  408. if (!c || !c->ops || !c->ops->set_rate)
  409. return -EINVAL;
  410. debug("%s: %s rate=%ld\n", __func__, c->name, rate);
  411. if (c->use_cnt)
  412. return -EINVAL;
  413. ret = c->ops->set_rate(c, rate);
  414. return ret;
  415. }
  416. /* Not required for this arch */
  417. /*
  418. long clk_round_rate(struct clk *clk, unsigned long rate);
  419. int clk_set_parent(struct clk *clk, struct clk *parent);
  420. struct clk *clk_get_parent(struct clk *clk);
  421. */