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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * armboot - Startup Code for ARM926EJS CPU-core
  4. *
  5. * Copyright (c) 2003 Texas Instruments
  6. *
  7. * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
  8. *
  9. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  10. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  11. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  12. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  13. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  14. */
  15. #include <config.h>
  16. /*
  17. *************************************************************************
  18. *
  19. * Startup Code (reset vector)
  20. *
  21. * The BootROM already initialized its own stack in the [0-0xb00] reserved
  22. * range of the SRAM. The SPL (in _main) will update the stack pointer to
  23. * its own SRAM area (right before the gd section).
  24. *
  25. *************************************************************************
  26. */
  27. .globl reset
  28. .globl back_to_bootrom
  29. reset:
  30. /*
  31. * SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
  32. * UART boot, USB boot): save registers in BootROM's stack and then the
  33. * BootROM's stack pointer in the SPL's data section.
  34. */
  35. push {r0-r12,lr}
  36. ldr r0, =bootrom_stash_sp
  37. str sp, [r0]
  38. /*
  39. * Flush v4 I/D caches
  40. */
  41. mov r0, #0
  42. mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
  43. mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */
  44. /*
  45. * Enable instruction cache
  46. */
  47. mrc p15, 0, r0, c1, c0, 0
  48. orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
  49. mcr p15, 0, r0, c1, c0, 0
  50. /*
  51. * Go setup Memory and board specific bits prior to relocation.
  52. * This call is not supposed to return.
  53. */
  54. b _main /* _main will call board_init_f */
  55. back_to_bootrom:
  56. pop {r0-r12,pc}