spl_power_init.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 Boot PMIC init
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <config.h>
  10. #include <hang.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include "mxs_init.h"
  15. #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
  16. #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
  17. POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
  18. #else
  19. #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
  20. POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
  21. #endif
  22. /**
  23. * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  24. *
  25. * This function switches the CPU core clock from PLL to 24MHz XTAL
  26. * oscilator. This is necessary if the PLL is being reconfigured to
  27. * prevent crash of the CPU core.
  28. */
  29. static void mxs_power_clock2xtal(void)
  30. {
  31. struct mxs_clkctrl_regs *clkctrl_regs =
  32. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  33. debug("SPL: Switching CPU clock to 24MHz XTAL\n");
  34. /* Set XTAL as CPU reference clock */
  35. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  36. &clkctrl_regs->hw_clkctrl_clkseq_set);
  37. }
  38. /**
  39. * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  40. *
  41. * This function switches the CPU core clock from 24MHz XTAL oscilator
  42. * to PLL. This can only be called once the PLL has re-locked and once
  43. * the PLL is stable after reconfiguration.
  44. */
  45. static void mxs_power_clock2pll(void)
  46. {
  47. struct mxs_clkctrl_regs *clkctrl_regs =
  48. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  49. debug("SPL: Switching CPU core clock source to PLL\n");
  50. /*
  51. * TODO: Are we really? It looks like we turn on PLL0, but we then
  52. * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
  53. * set by mxs_power_clock2xtal()). Clearing this bit here seems to
  54. * introduce some instability (causing the CPU core to hang). Maybe
  55. * we aren't giving PLL0 enough time to stabilise?
  56. */
  57. setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
  58. CLKCTRL_PLL0CTRL0_POWER);
  59. early_delay(100);
  60. /*
  61. * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
  62. * wait on the PLL0 LOCK bit?
  63. */
  64. setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
  65. CLKCTRL_CLKSEQ_BYPASS_CPU);
  66. }
  67. /**
  68. * mxs_power_set_auto_restart() - Set the auto-restart bit
  69. *
  70. * This function ungates the RTC block and sets the AUTO_RESTART
  71. * bit to work around a design bug on MX28EVK Rev. A .
  72. */
  73. static void mxs_power_set_auto_restart(void)
  74. {
  75. struct mxs_rtc_regs *rtc_regs =
  76. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  77. debug("SPL: Setting auto-restart bit\n");
  78. writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
  79. while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
  80. ;
  81. writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
  82. while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
  83. ;
  84. /* Do nothing if flag already set */
  85. if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
  86. return;
  87. while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
  88. ;
  89. setbits_le32(&rtc_regs->hw_rtc_persistent0,
  90. RTC_PERSISTENT0_AUTO_RESTART);
  91. writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
  92. writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
  93. while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
  94. ;
  95. while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
  96. ;
  97. }
  98. /**
  99. * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
  100. *
  101. * This function configures the VDDIO, VDDA and VDDD linear regulators output
  102. * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
  103. * converter. This is the recommended setting for the case where we use both
  104. * linear regulators and DC-DC converter to power the VDDIO rail.
  105. */
  106. static void mxs_power_set_linreg(void)
  107. {
  108. struct mxs_power_regs *power_regs =
  109. (struct mxs_power_regs *)MXS_POWER_BASE;
  110. /* Set linear regulator 25mV below switching converter */
  111. debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
  112. clrsetbits_le32(&power_regs->hw_power_vdddctrl,
  113. POWER_VDDDCTRL_LINREG_OFFSET_MASK,
  114. POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
  115. debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
  116. clrsetbits_le32(&power_regs->hw_power_vddactrl,
  117. POWER_VDDACTRL_LINREG_OFFSET_MASK,
  118. POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
  119. debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
  120. clrsetbits_le32(&power_regs->hw_power_vddioctrl,
  121. POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
  122. POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
  123. }
  124. /**
  125. * mxs_get_batt_volt() - Measure battery input voltage
  126. *
  127. * This function retrieves the battery input voltage and returns it.
  128. */
  129. static int mxs_get_batt_volt(void)
  130. {
  131. struct mxs_power_regs *power_regs =
  132. (struct mxs_power_regs *)MXS_POWER_BASE;
  133. uint32_t volt = readl(&power_regs->hw_power_battmonitor);
  134. volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
  135. volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
  136. volt *= 8;
  137. debug("SPL: Battery Voltage = %dmV\n", volt);
  138. return volt;
  139. }
  140. /**
  141. * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
  142. *
  143. * This function checks if the battery input voltage is higher than 3.6V and
  144. * therefore allows the system to successfully boot using this power source.
  145. */
  146. static int mxs_is_batt_ready(void)
  147. {
  148. return (mxs_get_batt_volt() >= 3600);
  149. }
  150. /**
  151. * mxs_is_batt_good() - Test if battery is operational at all
  152. *
  153. * This function starts recharging the battery and tests if the input current
  154. * provided by the 5V input recharging the battery is also sufficient to power
  155. * the DC-DC converter.
  156. */
  157. static int mxs_is_batt_good(void)
  158. {
  159. struct mxs_power_regs *power_regs =
  160. (struct mxs_power_regs *)MXS_POWER_BASE;
  161. uint32_t volt = mxs_get_batt_volt();
  162. if ((volt >= 2400) && (volt <= 4300)) {
  163. debug("SPL: Battery is good\n");
  164. return 1;
  165. }
  166. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  167. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  168. 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  169. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  170. &power_regs->hw_power_5vctrl_clr);
  171. clrsetbits_le32(&power_regs->hw_power_charge,
  172. POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
  173. POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
  174. writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
  175. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  176. &power_regs->hw_power_5vctrl_clr);
  177. early_delay(500000);
  178. volt = mxs_get_batt_volt();
  179. if (volt >= 3500) {
  180. debug("SPL: Battery Voltage too high\n");
  181. return 0;
  182. }
  183. if (volt >= 2400) {
  184. debug("SPL: Battery is good\n");
  185. return 1;
  186. }
  187. writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
  188. &power_regs->hw_power_charge_clr);
  189. writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
  190. debug("SPL: Battery Voltage too low\n");
  191. return 0;
  192. }
  193. /**
  194. * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
  195. *
  196. * This function enables the 5V detection comparator and sets the 5V valid
  197. * threshold to 4.4V . We use 4.4V threshold here to make sure that even
  198. * under high load, the voltage drop on the 5V input won't be so critical
  199. * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
  200. * converter and thus making the system crash.
  201. */
  202. static void mxs_power_setup_5v_detect(void)
  203. {
  204. struct mxs_power_regs *power_regs =
  205. (struct mxs_power_regs *)MXS_POWER_BASE;
  206. /* Start 5V detection */
  207. debug("SPL: Starting 5V input detection comparator\n");
  208. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  209. POWER_5VCTRL_VBUSVALID_TRSH_MASK,
  210. POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
  211. POWER_5VCTRL_PWRUP_VBUS_CMPS);
  212. }
  213. /**
  214. * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
  215. * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock
  216. *
  217. * This function configures and then enables an alternative PLL clock source
  218. * for the DC-DC converters.
  219. */
  220. void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
  221. {
  222. struct mxs_power_regs *power_regs =
  223. (struct mxs_power_regs *)MXS_POWER_BASE;
  224. /* Select clocksource for DC-DC converters */
  225. clrsetbits_le32(&power_regs->hw_power_misc,
  226. POWER_MISC_FREQSEL_MASK,
  227. freqsel);
  228. setbits_le32(&power_regs->hw_power_misc,
  229. POWER_MISC_SEL_PLLCLK);
  230. }
  231. /**
  232. * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
  233. *
  234. * Normally, there is no need to switch DC-DC clocksource. This is the reason,
  235. * why this function is a stub and does nothing. However, boards can implement
  236. * this function when required and call mxs_power_switch_dcdc_clocksource() to
  237. * switch to an alternative clock source.
  238. */
  239. __weak void mxs_power_setup_dcdc_clocksource(void)
  240. {
  241. debug("SPL: Using default DC-DC clocksource\n");
  242. }
  243. /**
  244. * mxs_src_power_init() - Preconfigure the power block
  245. *
  246. * This function configures reasonable values for the DC-DC control loop
  247. * and battery monitor.
  248. */
  249. static void mxs_src_power_init(void)
  250. {
  251. struct mxs_power_regs *power_regs =
  252. (struct mxs_power_regs *)MXS_POWER_BASE;
  253. debug("SPL: Pre-Configuring power block\n");
  254. /* Improve efficieny and reduce transient ripple */
  255. writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
  256. POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
  257. clrsetbits_le32(&power_regs->hw_power_dclimits,
  258. POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
  259. 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
  260. setbits_le32(&power_regs->hw_power_battmonitor,
  261. POWER_BATTMONITOR_EN_BATADJ);
  262. /* Increase the RCSCALE level for quick DCDC response to dynamic load */
  263. clrsetbits_le32(&power_regs->hw_power_loopctrl,
  264. POWER_LOOPCTRL_EN_RCSCALE_MASK,
  265. POWER_LOOPCTRL_RCSCALE_THRESH |
  266. POWER_LOOPCTRL_EN_RCSCALE_8X);
  267. clrsetbits_le32(&power_regs->hw_power_minpwr,
  268. POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
  269. /* 5V to battery handoff ... FIXME */
  270. setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  271. early_delay(30);
  272. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  273. }
  274. /**
  275. * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
  276. *
  277. * This function configures the necessary parameters for the 4P2 linear
  278. * regulator to supply the DC-DC converter from 5V input.
  279. */
  280. static void mxs_power_init_4p2_params(void)
  281. {
  282. struct mxs_power_regs *power_regs =
  283. (struct mxs_power_regs *)MXS_POWER_BASE;
  284. debug("SPL: Configuring common 4P2 regulator params\n");
  285. /* Setup 4P2 parameters */
  286. clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  287. POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
  288. POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
  289. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  290. POWER_5VCTRL_HEADROOM_ADJ_MASK,
  291. 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
  292. clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  293. POWER_DCDC4P2_DROPOUT_CTRL_MASK,
  294. DCDC4P2_DROPOUT_CONFIG);
  295. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  296. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  297. 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  298. }
  299. /**
  300. * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
  301. * @xfer: Select if the input shall be enabled or disabled
  302. *
  303. * This function enables or disables the 4P2 input into the DC-DC converter.
  304. */
  305. static void mxs_enable_4p2_dcdc_input(int xfer)
  306. {
  307. struct mxs_power_regs *power_regs =
  308. (struct mxs_power_regs *)MXS_POWER_BASE;
  309. uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
  310. uint32_t prev_5v_brnout, prev_5v_droop;
  311. debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
  312. if (xfer && (readl(&power_regs->hw_power_5vctrl) &
  313. POWER_5VCTRL_ENABLE_DCDC)) {
  314. return;
  315. }
  316. prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
  317. POWER_5VCTRL_PWDN_5VBRNOUT;
  318. prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
  319. POWER_CTRL_ENIRQ_VDD5V_DROOP;
  320. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
  321. writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
  322. &power_regs->hw_power_reset);
  323. clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
  324. /*
  325. * Recording orignal values that will be modified temporarlily
  326. * to handle a chip bug. See chip errata for CQ ENGR00115837
  327. */
  328. tmp = readl(&power_regs->hw_power_5vctrl);
  329. vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
  330. vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
  331. pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
  332. /*
  333. * Disable mechanisms that get erroneously tripped by when setting
  334. * the DCDC4P2 EN_DCDC
  335. */
  336. clrbits_le32(&power_regs->hw_power_5vctrl,
  337. POWER_5VCTRL_VBUSVALID_5VDETECT |
  338. POWER_5VCTRL_VBUSVALID_TRSH_MASK);
  339. writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
  340. if (xfer) {
  341. setbits_le32(&power_regs->hw_power_5vctrl,
  342. POWER_5VCTRL_DCDC_XFER);
  343. early_delay(20);
  344. clrbits_le32(&power_regs->hw_power_5vctrl,
  345. POWER_5VCTRL_DCDC_XFER);
  346. setbits_le32(&power_regs->hw_power_5vctrl,
  347. POWER_5VCTRL_ENABLE_DCDC);
  348. } else {
  349. setbits_le32(&power_regs->hw_power_dcdc4p2,
  350. POWER_DCDC4P2_ENABLE_DCDC);
  351. }
  352. early_delay(25);
  353. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  354. POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
  355. if (vbus_5vdetect)
  356. writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
  357. if (!pwd_bo)
  358. clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
  359. while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
  360. writel(POWER_CTRL_VBUS_VALID_IRQ,
  361. &power_regs->hw_power_ctrl_clr);
  362. if (prev_5v_brnout) {
  363. writel(POWER_5VCTRL_PWDN_5VBRNOUT,
  364. &power_regs->hw_power_5vctrl_set);
  365. writel(POWER_RESET_UNLOCK_KEY,
  366. &power_regs->hw_power_reset);
  367. } else {
  368. writel(POWER_5VCTRL_PWDN_5VBRNOUT,
  369. &power_regs->hw_power_5vctrl_clr);
  370. writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
  371. &power_regs->hw_power_reset);
  372. }
  373. while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
  374. writel(POWER_CTRL_VDD5V_DROOP_IRQ,
  375. &power_regs->hw_power_ctrl_clr);
  376. if (prev_5v_droop)
  377. clrbits_le32(&power_regs->hw_power_ctrl,
  378. POWER_CTRL_ENIRQ_VDD5V_DROOP);
  379. else
  380. setbits_le32(&power_regs->hw_power_ctrl,
  381. POWER_CTRL_ENIRQ_VDD5V_DROOP);
  382. }
  383. /**
  384. * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
  385. *
  386. * This function enables the 4P2 regulator and switches the DC-DC converter
  387. * to use the 4P2 input.
  388. */
  389. static void mxs_power_init_4p2_regulator(void)
  390. {
  391. struct mxs_power_regs *power_regs =
  392. (struct mxs_power_regs *)MXS_POWER_BASE;
  393. uint32_t tmp, tmp2;
  394. debug("SPL: Enabling 4P2 regulator\n");
  395. setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
  396. writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
  397. writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  398. &power_regs->hw_power_5vctrl_clr);
  399. clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
  400. /* Power up the 4p2 rail and logic/control */
  401. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  402. &power_regs->hw_power_5vctrl_clr);
  403. /*
  404. * Start charging up the 4p2 capacitor. We ramp of this charge
  405. * gradually to avoid large inrush current from the 5V cable which can
  406. * cause transients/problems
  407. */
  408. debug("SPL: Charging 4P2 capacitor\n");
  409. mxs_enable_4p2_dcdc_input(0);
  410. if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
  411. /*
  412. * If we arrived here, we were unable to recover from mx23 chip
  413. * errata 5837. 4P2 is disabled and sufficient battery power is
  414. * not present. Exiting to not enable DCDC power during 5V
  415. * connected state.
  416. */
  417. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  418. POWER_DCDC4P2_ENABLE_DCDC);
  419. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  420. &power_regs->hw_power_5vctrl_set);
  421. debug("SPL: Unable to recover from mx23 errata 5837\n");
  422. hang();
  423. }
  424. /*
  425. * Here we set the 4p2 brownout level to something very close to 4.2V.
  426. * We then check the brownout status. If the brownout status is false,
  427. * the voltage is already close to the target voltage of 4.2V so we
  428. * can go ahead and set the 4P2 current limit to our max target limit.
  429. * If the brownout status is true, we need to ramp us the current limit
  430. * so that we don't cause large inrush current issues. We step up the
  431. * current limit until the brownout status is false or until we've
  432. * reached our maximum defined 4p2 current limit.
  433. */
  434. debug("SPL: Setting 4P2 brownout level\n");
  435. clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  436. POWER_DCDC4P2_BO_MASK,
  437. 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
  438. if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
  439. setbits_le32(&power_regs->hw_power_5vctrl,
  440. 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  441. } else {
  442. tmp = (readl(&power_regs->hw_power_5vctrl) &
  443. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
  444. POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
  445. while (tmp < 0x3f) {
  446. if (!(readl(&power_regs->hw_power_sts) &
  447. POWER_STS_DCDC_4P2_BO)) {
  448. tmp = readl(&power_regs->hw_power_5vctrl);
  449. tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
  450. early_delay(100);
  451. writel(tmp, &power_regs->hw_power_5vctrl);
  452. break;
  453. } else {
  454. tmp++;
  455. tmp2 = readl(&power_regs->hw_power_5vctrl);
  456. tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
  457. tmp2 |= tmp <<
  458. POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
  459. writel(tmp2, &power_regs->hw_power_5vctrl);
  460. early_delay(100);
  461. }
  462. }
  463. }
  464. clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
  465. writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  466. }
  467. /**
  468. * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
  469. *
  470. * This function configures the DC-DC converter to be supplied from the 4P2
  471. * linear regulator.
  472. */
  473. static void mxs_power_init_dcdc_4p2_source(void)
  474. {
  475. struct mxs_power_regs *power_regs =
  476. (struct mxs_power_regs *)MXS_POWER_BASE;
  477. debug("SPL: Switching DC-DC converters to 4P2\n");
  478. if (!(readl(&power_regs->hw_power_dcdc4p2) &
  479. POWER_DCDC4P2_ENABLE_DCDC)) {
  480. debug("SPL: Already switched - aborting\n");
  481. hang();
  482. }
  483. mxs_enable_4p2_dcdc_input(1);
  484. if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
  485. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  486. POWER_DCDC4P2_ENABLE_DCDC);
  487. writel(POWER_5VCTRL_ENABLE_DCDC,
  488. &power_regs->hw_power_5vctrl_clr);
  489. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  490. &power_regs->hw_power_5vctrl_set);
  491. }
  492. }
  493. /**
  494. * mxs_power_enable_4p2() - Power up the 4P2 regulator
  495. *
  496. * This function drives the process of powering up the 4P2 linear regulator
  497. * and switching the DC-DC converter input over to the 4P2 linear regulator.
  498. */
  499. static void mxs_power_enable_4p2(void)
  500. {
  501. struct mxs_power_regs *power_regs =
  502. (struct mxs_power_regs *)MXS_POWER_BASE;
  503. uint32_t vdddctrl, vddactrl, vddioctrl;
  504. uint32_t tmp;
  505. debug("SPL: Powering up 4P2 regulator\n");
  506. vdddctrl = readl(&power_regs->hw_power_vdddctrl);
  507. vddactrl = readl(&power_regs->hw_power_vddactrl);
  508. vddioctrl = readl(&power_regs->hw_power_vddioctrl);
  509. setbits_le32(&power_regs->hw_power_vdddctrl,
  510. POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
  511. POWER_VDDDCTRL_PWDN_BRNOUT);
  512. setbits_le32(&power_regs->hw_power_vddactrl,
  513. POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
  514. POWER_VDDACTRL_PWDN_BRNOUT);
  515. setbits_le32(&power_regs->hw_power_vddioctrl,
  516. POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
  517. mxs_power_init_4p2_params();
  518. mxs_power_init_4p2_regulator();
  519. /* Shutdown battery (none present) */
  520. if (!mxs_is_batt_ready()) {
  521. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  522. POWER_DCDC4P2_BO_MASK);
  523. writel(POWER_CTRL_DCDC4P2_BO_IRQ,
  524. &power_regs->hw_power_ctrl_clr);
  525. writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
  526. &power_regs->hw_power_ctrl_clr);
  527. }
  528. mxs_power_init_dcdc_4p2_source();
  529. writel(vdddctrl, &power_regs->hw_power_vdddctrl);
  530. early_delay(20);
  531. writel(vddactrl, &power_regs->hw_power_vddactrl);
  532. early_delay(20);
  533. writel(vddioctrl, &power_regs->hw_power_vddioctrl);
  534. /*
  535. * Check if FET is enabled on either powerout and if so,
  536. * disable load.
  537. */
  538. tmp = 0;
  539. tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
  540. POWER_VDDDCTRL_DISABLE_FET);
  541. tmp |= !(readl(&power_regs->hw_power_vddactrl) &
  542. POWER_VDDACTRL_DISABLE_FET);
  543. tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
  544. POWER_VDDIOCTRL_DISABLE_FET);
  545. if (tmp)
  546. writel(POWER_CHARGE_ENABLE_LOAD,
  547. &power_regs->hw_power_charge_clr);
  548. debug("SPL: 4P2 regulator powered-up\n");
  549. }
  550. /**
  551. * mxs_boot_valid_5v() - Boot from 5V supply
  552. *
  553. * This function configures the power block to boot from valid 5V input.
  554. * This is called only if the 5V is reliable and can properly supply the
  555. * CPU. This function proceeds to configure the 4P2 converter to be supplied
  556. * from the 5V input.
  557. */
  558. static void mxs_boot_valid_5v(void)
  559. {
  560. struct mxs_power_regs *power_regs =
  561. (struct mxs_power_regs *)MXS_POWER_BASE;
  562. debug("SPL: Booting from 5V supply\n");
  563. /*
  564. * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
  565. * disconnect event. FIXME
  566. */
  567. writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
  568. &power_regs->hw_power_5vctrl_set);
  569. /* Configure polarity to check for 5V disconnection. */
  570. writel(POWER_CTRL_POLARITY_VBUSVALID |
  571. POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
  572. &power_regs->hw_power_ctrl_clr);
  573. writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
  574. &power_regs->hw_power_ctrl_clr);
  575. mxs_power_enable_4p2();
  576. }
  577. /**
  578. * mxs_powerdown() - Shut down the system
  579. *
  580. * This function powers down the CPU completely.
  581. */
  582. static void mxs_powerdown(void)
  583. {
  584. struct mxs_power_regs *power_regs =
  585. (struct mxs_power_regs *)MXS_POWER_BASE;
  586. debug("Powering Down\n");
  587. writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
  588. writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
  589. &power_regs->hw_power_reset);
  590. }
  591. /**
  592. * mxs_batt_boot() - Configure the power block to boot from battery input
  593. *
  594. * This function configures the power block to boot from the battery voltage
  595. * supply.
  596. */
  597. static void mxs_batt_boot(void)
  598. {
  599. struct mxs_power_regs *power_regs =
  600. (struct mxs_power_regs *)MXS_POWER_BASE;
  601. debug("SPL: Configuring power block to boot from battery\n");
  602. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
  603. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
  604. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  605. POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
  606. writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
  607. /* 5V to battery handoff. */
  608. setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  609. early_delay(30);
  610. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  611. writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
  612. clrsetbits_le32(&power_regs->hw_power_minpwr,
  613. POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
  614. mxs_power_set_linreg();
  615. clrbits_le32(&power_regs->hw_power_vdddctrl,
  616. POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
  617. clrbits_le32(&power_regs->hw_power_vddactrl,
  618. POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
  619. clrbits_le32(&power_regs->hw_power_vddioctrl,
  620. POWER_VDDIOCTRL_DISABLE_FET);
  621. setbits_le32(&power_regs->hw_power_5vctrl,
  622. POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
  623. setbits_le32(&power_regs->hw_power_5vctrl,
  624. POWER_5VCTRL_ENABLE_DCDC);
  625. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  626. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  627. 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  628. mxs_power_enable_4p2();
  629. }
  630. /**
  631. * mxs_handle_5v_conflict() - Test if the 5V input is reliable
  632. *
  633. * This function tests if the 5V input can reliably supply the system. If it
  634. * can, then proceed to configuring the system to boot from 5V source, otherwise
  635. * try booting from battery supply. If we can not boot from battery supply
  636. * either, shut down the system.
  637. */
  638. static void mxs_handle_5v_conflict(void)
  639. {
  640. struct mxs_power_regs *power_regs =
  641. (struct mxs_power_regs *)MXS_POWER_BASE;
  642. uint32_t tmp;
  643. debug("SPL: Resolving 5V conflict\n");
  644. setbits_le32(&power_regs->hw_power_vddioctrl,
  645. POWER_VDDIOCTRL_BO_OFFSET_MASK);
  646. for (;;) {
  647. tmp = readl(&power_regs->hw_power_sts);
  648. if (tmp & POWER_STS_VDDIO_BO) {
  649. /*
  650. * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
  651. * unreliable
  652. */
  653. debug("SPL: VDDIO has a brownout\n");
  654. mxs_powerdown();
  655. break;
  656. }
  657. if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
  658. debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
  659. mxs_boot_valid_5v();
  660. break;
  661. } else {
  662. debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
  663. mxs_powerdown();
  664. break;
  665. }
  666. /*
  667. * TODO: I can't see this being reached. We'll either
  668. * powerdown or boot from a stable 5V supply.
  669. */
  670. if (tmp & POWER_STS_PSWITCH_MASK) {
  671. debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
  672. mxs_batt_boot();
  673. break;
  674. }
  675. }
  676. }
  677. /**
  678. * mxs_5v_boot() - Configure the power block to boot from 5V input
  679. *
  680. * This function handles configuration of the power block when supplied by
  681. * a 5V input.
  682. */
  683. static void mxs_5v_boot(void)
  684. {
  685. struct mxs_power_regs *power_regs =
  686. (struct mxs_power_regs *)MXS_POWER_BASE;
  687. debug("SPL: Configuring power block to boot from 5V input\n");
  688. /*
  689. * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
  690. * but their implementation always returns 1 so we omit it here.
  691. */
  692. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  693. debug("SPL: 5V VDD good\n");
  694. mxs_boot_valid_5v();
  695. return;
  696. }
  697. early_delay(1000);
  698. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  699. debug("SPL: 5V VDD good (after delay)\n");
  700. mxs_boot_valid_5v();
  701. return;
  702. }
  703. debug("SPL: 5V VDD not good\n");
  704. mxs_handle_5v_conflict();
  705. }
  706. /**
  707. * mxs_init_batt_bo() - Configure battery brownout threshold
  708. *
  709. * This function configures the battery input brownout threshold. The value
  710. * at which the battery brownout happens is configured to 3.0V in the code.
  711. */
  712. static void mxs_init_batt_bo(void)
  713. {
  714. struct mxs_power_regs *power_regs =
  715. (struct mxs_power_regs *)MXS_POWER_BASE;
  716. debug("SPL: Initialising battery brown-out level to 3.0V\n");
  717. /* Brownout at 3V */
  718. clrsetbits_le32(&power_regs->hw_power_battmonitor,
  719. POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
  720. 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
  721. writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  722. writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
  723. }
  724. /**
  725. * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
  726. *
  727. * This function turns off the VDDD linear regulator and therefore makes
  728. * the VDDD rail be supplied only by the DC-DC converter.
  729. */
  730. static void mxs_switch_vddd_to_dcdc_source(void)
  731. {
  732. struct mxs_power_regs *power_regs =
  733. (struct mxs_power_regs *)MXS_POWER_BASE;
  734. debug("SPL: Switching VDDD to DC-DC converters\n");
  735. clrsetbits_le32(&power_regs->hw_power_vdddctrl,
  736. POWER_VDDDCTRL_LINREG_OFFSET_MASK,
  737. POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
  738. clrbits_le32(&power_regs->hw_power_vdddctrl,
  739. POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
  740. POWER_VDDDCTRL_DISABLE_STEPPING);
  741. }
  742. /**
  743. * mxs_power_configure_power_source() - Configure power block source
  744. *
  745. * This function is the core of the power configuration logic. The function
  746. * selects the power block input source and configures the whole power block
  747. * accordingly. After the configuration is complete and the system is stable
  748. * again, the function switches the CPU clock source back to PLL. Finally,
  749. * the function switches the voltage rails to DC-DC converter.
  750. */
  751. static void mxs_power_configure_power_source(void)
  752. {
  753. int batt_ready, batt_good;
  754. struct mxs_power_regs *power_regs =
  755. (struct mxs_power_regs *)MXS_POWER_BASE;
  756. struct mxs_lradc_regs *lradc_regs =
  757. (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  758. debug("SPL: Configuring power source\n");
  759. mxs_power_setup_dcdc_clocksource();
  760. mxs_src_power_init();
  761. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  762. batt_ready = mxs_is_batt_ready();
  763. if (batt_ready) {
  764. /* 5V source detected, good battery detected. */
  765. mxs_batt_boot();
  766. } else {
  767. batt_good = mxs_is_batt_good();
  768. if (!batt_good) {
  769. /* 5V source detected, bad battery detected. */
  770. writel(LRADC_CONVERSION_AUTOMATIC,
  771. &lradc_regs->hw_lradc_conversion_clr);
  772. clrbits_le32(&power_regs->hw_power_battmonitor,
  773. POWER_BATTMONITOR_BATT_VAL_MASK);
  774. }
  775. mxs_5v_boot();
  776. }
  777. } else {
  778. /* 5V not detected, booting from battery. */
  779. mxs_batt_boot();
  780. }
  781. /*
  782. * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
  783. * from USB VBUS
  784. */
  785. mxs_power_clock2pll();
  786. mxs_init_batt_bo();
  787. mxs_switch_vddd_to_dcdc_source();
  788. #ifdef CONFIG_MX23
  789. /* Fire up the VDDMEM LinReg now that we're all set. */
  790. debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
  791. writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
  792. &power_regs->hw_power_vddmemctrl);
  793. #endif
  794. }
  795. /**
  796. * mxs_enable_output_rail_protection() - Enable power rail protection
  797. *
  798. * This function enables overload protection on the power rails. This is
  799. * triggered if the power rails' voltage drops rapidly due to overload and
  800. * in such case, the supply to the powerrail is cut-off, protecting the
  801. * CPU from damage. Note that under such condition, the system will likely
  802. * crash or misbehave.
  803. */
  804. static void mxs_enable_output_rail_protection(void)
  805. {
  806. struct mxs_power_regs *power_regs =
  807. (struct mxs_power_regs *)MXS_POWER_BASE;
  808. debug("SPL: Enabling output rail protection\n");
  809. writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
  810. POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  811. setbits_le32(&power_regs->hw_power_vdddctrl,
  812. POWER_VDDDCTRL_PWDN_BRNOUT);
  813. setbits_le32(&power_regs->hw_power_vddactrl,
  814. POWER_VDDACTRL_PWDN_BRNOUT);
  815. setbits_le32(&power_regs->hw_power_vddioctrl,
  816. POWER_VDDIOCTRL_PWDN_BRNOUT);
  817. }
  818. /**
  819. * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
  820. *
  821. * This function tests if the VDDIO rail is supplied by linear regulator
  822. * or by the DC-DC converter. Returns 1 if powered by linear regulator,
  823. * returns 0 if powered by the DC-DC converter.
  824. */
  825. static int mxs_get_vddio_power_source_off(void)
  826. {
  827. struct mxs_power_regs *power_regs =
  828. (struct mxs_power_regs *)MXS_POWER_BASE;
  829. uint32_t tmp;
  830. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  831. tmp = readl(&power_regs->hw_power_vddioctrl);
  832. if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
  833. if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
  834. POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
  835. return 1;
  836. }
  837. }
  838. if (!(readl(&power_regs->hw_power_5vctrl) &
  839. POWER_5VCTRL_ENABLE_DCDC)) {
  840. if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
  841. POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
  842. return 1;
  843. }
  844. }
  845. }
  846. return 0;
  847. }
  848. /**
  849. * mxs_get_vddd_power_source_off() - Get VDDD rail power source
  850. *
  851. * This function tests if the VDDD rail is supplied by linear regulator
  852. * or by the DC-DC converter. Returns 1 if powered by linear regulator,
  853. * returns 0 if powered by the DC-DC converter.
  854. */
  855. static int mxs_get_vddd_power_source_off(void)
  856. {
  857. struct mxs_power_regs *power_regs =
  858. (struct mxs_power_regs *)MXS_POWER_BASE;
  859. uint32_t tmp;
  860. tmp = readl(&power_regs->hw_power_vdddctrl);
  861. if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
  862. if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
  863. POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
  864. return 1;
  865. }
  866. }
  867. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  868. if (!(readl(&power_regs->hw_power_5vctrl) &
  869. POWER_5VCTRL_ENABLE_DCDC)) {
  870. return 1;
  871. }
  872. }
  873. if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
  874. if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
  875. POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
  876. return 1;
  877. }
  878. }
  879. return 0;
  880. }
  881. struct mxs_vddx_cfg {
  882. uint32_t *reg;
  883. uint8_t step_mV;
  884. uint16_t lowest_mV;
  885. int (*powered_by_linreg)(void);
  886. uint32_t trg_mask;
  887. uint32_t bo_irq;
  888. uint32_t bo_enirq;
  889. uint32_t bo_offset_mask;
  890. uint32_t bo_offset_offset;
  891. };
  892. static const struct mxs_vddx_cfg mxs_vddio_cfg = {
  893. .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
  894. hw_power_vddioctrl),
  895. #if defined(CONFIG_MX23)
  896. .step_mV = 25,
  897. #else
  898. .step_mV = 50,
  899. #endif
  900. .lowest_mV = 2800,
  901. .powered_by_linreg = mxs_get_vddio_power_source_off,
  902. .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
  903. .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
  904. .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
  905. .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
  906. .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
  907. };
  908. static const struct mxs_vddx_cfg mxs_vddd_cfg = {
  909. .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
  910. hw_power_vdddctrl),
  911. .step_mV = 25,
  912. .lowest_mV = 800,
  913. .powered_by_linreg = mxs_get_vddd_power_source_off,
  914. .trg_mask = POWER_VDDDCTRL_TRG_MASK,
  915. .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
  916. .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
  917. .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
  918. .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
  919. };
  920. #ifdef CONFIG_MX23
  921. static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
  922. .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
  923. hw_power_vddmemctrl),
  924. .step_mV = 50,
  925. .lowest_mV = 1700,
  926. .powered_by_linreg = NULL,
  927. .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
  928. .bo_irq = 0,
  929. .bo_enirq = 0,
  930. .bo_offset_mask = 0,
  931. .bo_offset_offset = 0,
  932. };
  933. #endif
  934. /**
  935. * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
  936. * @cfg: Configuration data of the DC-DC converter rail
  937. * @new_target: New target voltage of the DC-DC converter rail
  938. * @new_brownout: New brownout trigger voltage
  939. *
  940. * This function configures the output voltage on the DC-DC converter rail.
  941. * The rail is selected by the @cfg argument. The new voltage target is
  942. * selected by the @new_target and the voltage is specified in mV. The
  943. * new brownout value is selected by the @new_brownout argument and the
  944. * value is also in mV.
  945. */
  946. static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
  947. uint32_t new_target, uint32_t new_brownout)
  948. {
  949. struct mxs_power_regs *power_regs =
  950. (struct mxs_power_regs *)MXS_POWER_BASE;
  951. uint32_t cur_target, diff, bo_int = 0;
  952. uint32_t powered_by_linreg = 0;
  953. int adjust_up, tmp;
  954. new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
  955. cfg->step_mV);
  956. cur_target = readl(cfg->reg);
  957. cur_target &= cfg->trg_mask;
  958. cur_target *= cfg->step_mV;
  959. cur_target += cfg->lowest_mV;
  960. adjust_up = new_target > cur_target;
  961. if (cfg->powered_by_linreg)
  962. powered_by_linreg = cfg->powered_by_linreg();
  963. if (adjust_up && cfg->bo_irq) {
  964. if (powered_by_linreg) {
  965. bo_int = readl(cfg->reg);
  966. clrbits_le32(cfg->reg, cfg->bo_enirq);
  967. }
  968. setbits_le32(cfg->reg, cfg->bo_offset_mask);
  969. }
  970. do {
  971. if (abs(new_target - cur_target) > 100) {
  972. if (adjust_up)
  973. diff = cur_target + 100;
  974. else
  975. diff = cur_target - 100;
  976. } else {
  977. diff = new_target;
  978. }
  979. diff -= cfg->lowest_mV;
  980. diff /= cfg->step_mV;
  981. clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
  982. if (powered_by_linreg ||
  983. (readl(&power_regs->hw_power_sts) &
  984. POWER_STS_VDD5V_GT_VDDIO))
  985. early_delay(500);
  986. else {
  987. for (;;) {
  988. tmp = readl(&power_regs->hw_power_sts);
  989. if (tmp & POWER_STS_DC_OK)
  990. break;
  991. }
  992. }
  993. cur_target = readl(cfg->reg);
  994. cur_target &= cfg->trg_mask;
  995. cur_target *= cfg->step_mV;
  996. cur_target += cfg->lowest_mV;
  997. } while (new_target > cur_target);
  998. if (cfg->bo_irq) {
  999. if (adjust_up && powered_by_linreg) {
  1000. writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
  1001. if (bo_int & cfg->bo_enirq)
  1002. setbits_le32(cfg->reg, cfg->bo_enirq);
  1003. }
  1004. clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
  1005. new_brownout << cfg->bo_offset_offset);
  1006. }
  1007. }
  1008. /**
  1009. * mxs_setup_batt_detect() - Start the battery voltage measurement logic
  1010. *
  1011. * This function starts and configures the LRADC block. This allows the
  1012. * power initialization code to measure battery voltage and based on this
  1013. * knowledge, decide whether to boot at all, boot from battery or boot
  1014. * from 5V input.
  1015. */
  1016. static void mxs_setup_batt_detect(void)
  1017. {
  1018. debug("SPL: Starting battery voltage measurement logic\n");
  1019. mxs_lradc_init();
  1020. mxs_lradc_enable_batt_measurement();
  1021. early_delay(10);
  1022. }
  1023. /**
  1024. * mxs_ungate_power() - Ungate the POWER block
  1025. *
  1026. * This function ungates clock to the power block. In case the power block
  1027. * was still gated at this point, it will not be possible to configure the
  1028. * block and therefore the power initialization would fail. This function
  1029. * is only needed on i.MX233, on i.MX28 the power block is always ungated.
  1030. */
  1031. static void mxs_ungate_power(void)
  1032. {
  1033. #ifdef CONFIG_MX23
  1034. struct mxs_power_regs *power_regs =
  1035. (struct mxs_power_regs *)MXS_POWER_BASE;
  1036. writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
  1037. #endif
  1038. }
  1039. /**
  1040. * mxs_power_init() - The power block init main function
  1041. *
  1042. * This function calls all the power block initialization functions in
  1043. * proper sequence to start the power block.
  1044. */
  1045. void mxs_power_init(void)
  1046. {
  1047. struct mxs_power_regs *power_regs =
  1048. (struct mxs_power_regs *)MXS_POWER_BASE;
  1049. debug("SPL: Initialising Power Block\n");
  1050. mxs_ungate_power();
  1051. mxs_power_clock2xtal();
  1052. mxs_power_set_auto_restart();
  1053. mxs_power_set_linreg();
  1054. mxs_power_setup_5v_detect();
  1055. mxs_setup_batt_detect();
  1056. mxs_power_configure_power_source();
  1057. mxs_enable_output_rail_protection();
  1058. debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
  1059. mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
  1060. debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n");
  1061. mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400);
  1062. #ifdef CONFIG_MX23
  1063. debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
  1064. mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
  1065. #endif
  1066. writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
  1067. POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
  1068. POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
  1069. POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  1070. writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
  1071. early_delay(1000);
  1072. }
  1073. #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
  1074. /**
  1075. * mxs_power_wait_pswitch() - Wait for power switch to be pressed
  1076. *
  1077. * This function waits until the power-switch was pressed to start booting
  1078. * the board.
  1079. */
  1080. void mxs_power_wait_pswitch(void)
  1081. {
  1082. struct mxs_power_regs *power_regs =
  1083. (struct mxs_power_regs *)MXS_POWER_BASE;
  1084. debug("SPL: Waiting for power switch input\n");
  1085. while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
  1086. ;
  1087. }
  1088. #endif