spl_mem_init.c 9.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 RAM init
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <config.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <linux/compiler.h>
  16. #include "mxs_init.h"
  17. __weak uint32_t mxs_dram_vals[] = {
  18. /*
  19. * i.MX28 DDR2 at 200MHz
  20. */
  21. #if defined(CONFIG_MX28)
  22. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  23. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  24. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  25. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  26. 0x00000000, 0x00000100, 0x00000000, 0x00000000,
  27. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  28. 0x00000000, 0x00000000, 0x00010101, 0x01010101,
  29. 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
  30. 0x00000100, 0x00000100, 0x00000000, 0x00000002,
  31. 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
  32. 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
  33. 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
  34. 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
  35. 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
  36. 0x00000003, 0x00000000, 0x00000000, 0x00000000,
  37. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  38. 0x00000000, 0x00000000, 0x00000612, 0x01000F02,
  39. 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
  40. 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
  41. 0x07000300, 0x07400300, 0x07400300, 0x00000005,
  42. 0x00000000, 0x00000000, 0x01000000, 0x01020408,
  43. 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
  44. 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
  45. 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
  46. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  47. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  48. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  49. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  50. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  51. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  52. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  53. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  54. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  55. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  56. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  57. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  58. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  59. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  60. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  61. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  62. 0x00000000, 0x00000000, 0x00010000, 0x00030404,
  63. 0x00000003, 0x00000000, 0x00000000, 0x00000000,
  64. 0x00000000, 0x00000000, 0x00000000, 0x01010000,
  65. 0x01000000, 0x03030000, 0x00010303, 0x01020202,
  66. 0x00000000, 0x02040303, 0x21002103, 0x00061200,
  67. 0x06120612, 0x04420442, 0x04420442, 0x00040004,
  68. 0x00040004, 0x00000000, 0x00000000, 0x00000000,
  69. 0x00000000, 0xffffffff
  70. /*
  71. * i.MX23 DDR at 133MHz
  72. */
  73. #elif defined(CONFIG_MX23)
  74. 0x01010001, 0x00010100, 0x01000101, 0x00000001,
  75. 0x00000101, 0x00000000, 0x00010000, 0x01000001,
  76. 0x00000000, 0x00000001, 0x07000200, 0x00070202,
  77. 0x02020000, 0x04040a01, 0x00000201, 0x02040000,
  78. 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
  79. 0x02061521, 0x0000000a, 0x00080008, 0x00200020,
  80. 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
  81. 0x00000000, 0x00000020, 0x00000020, 0x00c80000,
  82. 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
  83. 0x00000101, 0x00040001, 0x00000000, 0x00000000,
  84. 0x00010000
  85. #else
  86. #error Unsupported memory initialization
  87. #endif
  88. };
  89. __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
  90. {
  91. debug("SPL: Using default SDRAM parameters\n");
  92. }
  93. #ifdef CONFIG_MX28
  94. static void initialize_dram_values(void)
  95. {
  96. int i;
  97. debug("SPL: Setting mx28 board specific SDRAM parameters\n");
  98. mxs_adjust_memory_params(mxs_dram_vals);
  99. debug("SPL: Applying SDRAM parameters\n");
  100. for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
  101. writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
  102. }
  103. #else
  104. static void initialize_dram_values(void)
  105. {
  106. int i;
  107. debug("SPL: Setting mx23 board specific SDRAM parameters\n");
  108. mxs_adjust_memory_params(mxs_dram_vals);
  109. /*
  110. * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
  111. * per FSL bootlets code.
  112. *
  113. * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
  114. * "reserved".
  115. * HW_DRAM_CTL8 is setup as the last element.
  116. * So skip the initialization of these HW_DRAM_CTL registers.
  117. */
  118. debug("SPL: Applying SDRAM parameters\n");
  119. for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
  120. if (i == 8 || i == 27 || i == 28 || i == 35)
  121. continue;
  122. writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
  123. }
  124. /*
  125. * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
  126. * element to be set
  127. */
  128. writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
  129. }
  130. #endif
  131. static void mxs_mem_init_clock(void)
  132. {
  133. struct mxs_clkctrl_regs *clkctrl_regs =
  134. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  135. #if defined(CONFIG_MX23)
  136. /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
  137. const unsigned char divider = 33;
  138. #elif defined(CONFIG_MX28)
  139. /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
  140. const unsigned char divider = 21;
  141. #endif
  142. debug("SPL: Initialising FRAC0\n");
  143. /* Gate EMI clock */
  144. writeb(CLKCTRL_FRAC_CLKGATE,
  145. &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
  146. /* Set fractional divider for ref_emi */
  147. writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
  148. &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
  149. /* Ungate EMI clock */
  150. writeb(CLKCTRL_FRAC_CLKGATE,
  151. &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
  152. early_delay(11000);
  153. /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
  154. writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
  155. (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
  156. &clkctrl_regs->hw_clkctrl_emi);
  157. /* Unbypass EMI */
  158. writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
  159. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  160. early_delay(10000);
  161. debug("SPL: FRAC0 Initialised\n");
  162. }
  163. static void mxs_mem_setup_cpu_and_hbus(void)
  164. {
  165. struct mxs_clkctrl_regs *clkctrl_regs =
  166. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  167. debug("SPL: Setting CPU and HBUS clock frequencies\n");
  168. /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
  169. * and ungate CPU clock */
  170. writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
  171. (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
  172. /* Set CPU bypass */
  173. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  174. &clkctrl_regs->hw_clkctrl_clkseq_set);
  175. /* HBUS = 151MHz */
  176. writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
  177. writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
  178. &clkctrl_regs->hw_clkctrl_hbus_clr);
  179. early_delay(10000);
  180. /* CPU clock divider = 1 */
  181. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
  182. CLKCTRL_CPU_DIV_CPU_MASK, 1);
  183. /* Disable CPU bypass */
  184. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  185. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  186. early_delay(15000);
  187. }
  188. static void mxs_mem_setup_vdda(void)
  189. {
  190. struct mxs_power_regs *power_regs =
  191. (struct mxs_power_regs *)MXS_POWER_BASE;
  192. debug("SPL: Configuring VDDA\n");
  193. writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
  194. (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
  195. POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
  196. &power_regs->hw_power_vddactrl);
  197. }
  198. uint32_t mxs_mem_get_size(void)
  199. {
  200. uint32_t sz, da;
  201. uint32_t *vt = (uint32_t *)0x20;
  202. /* The following is "subs pc, r14, #4", used as return from DABT. */
  203. const uint32_t data_abort_memdetect_handler = 0xe25ef004;
  204. /* Replace the DABT handler. */
  205. da = vt[4];
  206. vt[4] = data_abort_memdetect_handler;
  207. sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  208. /* Restore the old DABT handler. */
  209. vt[4] = da;
  210. return sz;
  211. }
  212. #ifdef CONFIG_MX23
  213. static void mx23_mem_setup_vddmem(void)
  214. {
  215. struct mxs_power_regs *power_regs =
  216. (struct mxs_power_regs *)MXS_POWER_BASE;
  217. debug("SPL: Setting mx23 VDDMEM\n");
  218. /* We must wait before and after disabling the current limiter! */
  219. early_delay(10000);
  220. clrbits_le32(&power_regs->hw_power_vddmemctrl,
  221. POWER_VDDMEMCTRL_ENABLE_ILIMIT);
  222. early_delay(10000);
  223. }
  224. static void mx23_mem_init(void)
  225. {
  226. debug("SPL: Initialising mx23 SDRAM Controller\n");
  227. /*
  228. * Reset/ungate the EMI block. This is essential, otherwise the system
  229. * suffers from memory instability. This thing is mx23 specific and is
  230. * no longer present on mx28.
  231. */
  232. mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
  233. mx23_mem_setup_vddmem();
  234. /*
  235. * Configure the DRAM registers
  236. */
  237. /* Clear START and SREFRESH bit from DRAM_CTL8 */
  238. clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
  239. initialize_dram_values();
  240. /* Set START bit in DRAM_CTL8 */
  241. setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
  242. clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
  243. /* Wait for EMI_STAT bit DRAM_HALTED */
  244. for (;;) {
  245. if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
  246. break;
  247. early_delay(1000);
  248. }
  249. /* Adjust EMI port priority. */
  250. clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
  251. early_delay(20000);
  252. setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
  253. setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
  254. }
  255. #endif
  256. #ifdef CONFIG_MX28
  257. static void mx28_mem_init(void)
  258. {
  259. struct mxs_pinctrl_regs *pinctrl_regs =
  260. (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
  261. debug("SPL: Initialising mx28 SDRAM Controller\n");
  262. /* Set DDR2 mode */
  263. writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
  264. &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
  265. /*
  266. * Configure the DRAM registers
  267. */
  268. /* Clear START bit from DRAM_CTL16 */
  269. clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
  270. initialize_dram_values();
  271. /* Clear SREFRESH bit from DRAM_CTL17 */
  272. clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
  273. /* Set START bit in DRAM_CTL16 */
  274. setbits_le32(MXS_DRAM_BASE + 0x40, 1);
  275. /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
  276. while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
  277. ;
  278. }
  279. #endif
  280. void mxs_mem_init(void)
  281. {
  282. early_delay(11000);
  283. mxs_mem_init_clock();
  284. mxs_mem_setup_vdda();
  285. #if defined(CONFIG_MX23)
  286. mx23_mem_init();
  287. #elif defined(CONFIG_MX28)
  288. mx28_mem_init();
  289. #endif
  290. early_delay(10000);
  291. mxs_mem_setup_cpu_and_hbus();
  292. }