spl_lradc_init.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 Battery measurement init
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <config.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include "mxs_init.h"
  14. void mxs_lradc_init(void)
  15. {
  16. struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  17. debug("SPL: Initialisating LRADC\n");
  18. writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
  19. writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
  20. writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
  21. clrsetbits_le32(&regs->hw_lradc_ctrl3,
  22. LRADC_CTRL3_CYCLE_TIME_MASK,
  23. LRADC_CTRL3_CYCLE_TIME_6MHZ);
  24. clrsetbits_le32(&regs->hw_lradc_ctrl4,
  25. LRADC_CTRL4_LRADC7SELECT_MASK |
  26. LRADC_CTRL4_LRADC6SELECT_MASK,
  27. LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
  28. LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
  29. }
  30. void mxs_lradc_enable_batt_measurement(void)
  31. {
  32. struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  33. debug("SPL: Enabling LRADC battery measurement\n");
  34. /* Check if the channel is present at all. */
  35. if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
  36. debug("SPL: LRADC channel 7 is not present - aborting\n");
  37. return;
  38. }
  39. debug("SPL: LRADC channel 7 is present - configuring\n");
  40. writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
  41. writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
  42. clrsetbits_le32(&regs->hw_lradc_conversion,
  43. LRADC_CONVERSION_SCALE_FACTOR_MASK,
  44. LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
  45. writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
  46. /* Configure the channel. */
  47. writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  48. &regs->hw_lradc_ctrl2_clr);
  49. writel(0xffffffff, &regs->hw_lradc_ch7_clr);
  50. clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
  51. writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
  52. /* Schedule the channel. */
  53. writel(1 << 7, &regs->hw_lradc_ctrl0_set);
  54. /* Start the channel sampling. */
  55. writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
  56. ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
  57. 100, &regs->hw_lradc_delay3);
  58. writel(0xffffffff, &regs->hw_lradc_ch7_clr);
  59. writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
  60. debug("SPL: LRADC channel 7 configuration complete\n");
  61. }