clock.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 clock setup code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  10. */
  11. #include <common.h>
  12. #include <log.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/imx-regs.h>
  17. /*
  18. * The PLL frequency is 480MHz and XTAL frequency is 24MHz
  19. * iMX23: datasheet section 4.2
  20. * iMX28: datasheet section 10.2
  21. */
  22. #define PLL_FREQ_KHZ 480000
  23. #define PLL_FREQ_COEF 18
  24. #define XTAL_FREQ_KHZ 24000
  25. #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
  26. #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
  27. #if defined(CONFIG_MX23)
  28. #define MXC_SSPCLK_MAX MXC_SSPCLK0
  29. #elif defined(CONFIG_MX28)
  30. #define MXC_SSPCLK_MAX MXC_SSPCLK3
  31. #endif
  32. static uint32_t mxs_get_pclk(void)
  33. {
  34. struct mxs_clkctrl_regs *clkctrl_regs =
  35. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  36. uint32_t clkctrl, clkseq, div;
  37. uint8_t clkfrac, frac;
  38. clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
  39. /* No support of fractional divider calculation */
  40. if (clkctrl &
  41. (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
  42. return 0;
  43. }
  44. clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
  45. /* XTAL Path */
  46. if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
  47. div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
  48. CLKCTRL_CPU_DIV_XTAL_OFFSET;
  49. return XTAL_FREQ_MHZ / div;
  50. }
  51. /* REF Path */
  52. clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
  53. frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
  54. div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
  55. return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
  56. }
  57. static uint32_t mxs_get_hclk(void)
  58. {
  59. struct mxs_clkctrl_regs *clkctrl_regs =
  60. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  61. uint32_t div;
  62. uint32_t clkctrl;
  63. clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
  64. /* No support of fractional divider calculation */
  65. if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
  66. return 0;
  67. div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
  68. return mxs_get_pclk() / div;
  69. }
  70. static uint32_t mxs_get_emiclk(void)
  71. {
  72. struct mxs_clkctrl_regs *clkctrl_regs =
  73. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  74. uint32_t clkctrl, clkseq, div;
  75. uint8_t clkfrac, frac;
  76. clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
  77. clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
  78. /* XTAL Path */
  79. if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
  80. div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
  81. CLKCTRL_EMI_DIV_XTAL_OFFSET;
  82. return XTAL_FREQ_MHZ / div;
  83. }
  84. /* REF Path */
  85. clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
  86. frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
  87. div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
  88. return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
  89. }
  90. static uint32_t mxs_get_gpmiclk(void)
  91. {
  92. struct mxs_clkctrl_regs *clkctrl_regs =
  93. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  94. #if defined(CONFIG_MX23)
  95. uint8_t *reg =
  96. &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
  97. #elif defined(CONFIG_MX28)
  98. uint8_t *reg =
  99. &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
  100. #endif
  101. uint32_t clkctrl, clkseq, div;
  102. uint8_t clkfrac, frac;
  103. clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
  104. clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
  105. /* XTAL Path */
  106. if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
  107. div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
  108. return XTAL_FREQ_MHZ / div;
  109. }
  110. /* REF Path */
  111. clkfrac = readb(reg);
  112. frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
  113. div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
  114. return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
  115. }
  116. /*
  117. * Set IO clock frequency, in kHz
  118. */
  119. void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
  120. {
  121. struct mxs_clkctrl_regs *clkctrl_regs =
  122. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  123. uint32_t div;
  124. int io_reg;
  125. if (freq == 0)
  126. return;
  127. if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
  128. return;
  129. div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
  130. if (div < 18)
  131. div = 18;
  132. if (div > 35)
  133. div = 35;
  134. io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
  135. writeb(CLKCTRL_FRAC_CLKGATE,
  136. &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
  137. writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
  138. &clkctrl_regs->hw_clkctrl_frac0[io_reg]);
  139. writeb(CLKCTRL_FRAC_CLKGATE,
  140. &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
  141. }
  142. /*
  143. * Get IO clock, returns IO clock in kHz
  144. */
  145. static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
  146. {
  147. struct mxs_clkctrl_regs *clkctrl_regs =
  148. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  149. uint8_t ret;
  150. int io_reg;
  151. if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
  152. return 0;
  153. io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
  154. ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
  155. CLKCTRL_FRAC_FRAC_MASK;
  156. return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
  157. }
  158. /*
  159. * Configure SSP clock frequency, in kHz
  160. */
  161. void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
  162. {
  163. struct mxs_clkctrl_regs *clkctrl_regs =
  164. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  165. uint32_t clk, clkreg;
  166. if (ssp > MXC_SSPCLK_MAX)
  167. return;
  168. clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
  169. (ssp * sizeof(struct mxs_register_32));
  170. clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
  171. while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
  172. ;
  173. if (xtal)
  174. clk = XTAL_FREQ_KHZ;
  175. else
  176. clk = mxs_get_ioclk(ssp >> 1);
  177. if (freq > clk)
  178. return;
  179. /* Calculate the divider and cap it if necessary */
  180. clk /= freq;
  181. if (clk > CLKCTRL_SSP_DIV_MASK)
  182. clk = CLKCTRL_SSP_DIV_MASK;
  183. clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
  184. while (readl(clkreg) & CLKCTRL_SSP_BUSY)
  185. ;
  186. if (xtal)
  187. writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
  188. &clkctrl_regs->hw_clkctrl_clkseq_set);
  189. else
  190. writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
  191. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  192. }
  193. /*
  194. * Return SSP frequency, in kHz
  195. */
  196. static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
  197. {
  198. struct mxs_clkctrl_regs *clkctrl_regs =
  199. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  200. uint32_t clkreg;
  201. uint32_t clk, tmp;
  202. if (ssp > MXC_SSPCLK_MAX)
  203. return 0;
  204. tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
  205. if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
  206. return XTAL_FREQ_KHZ;
  207. clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
  208. (ssp * sizeof(struct mxs_register_32));
  209. tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
  210. if (tmp == 0)
  211. return 0;
  212. clk = mxs_get_ioclk(ssp >> 1);
  213. return clk / tmp;
  214. }
  215. /*
  216. * Set SSP/MMC bus frequency, in kHz)
  217. */
  218. void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
  219. {
  220. struct mxs_ssp_regs *ssp_regs;
  221. const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
  222. const uint32_t sspclk = mxs_get_sspclk(clk);
  223. uint32_t reg;
  224. uint32_t divide, rate, tgtclk;
  225. ssp_regs = mxs_ssp_regs_by_bus(bus);
  226. /*
  227. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  228. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  229. * CLOCK_RATE could be any integer from 0 to 255.
  230. */
  231. for (divide = 2; divide < 254; divide += 2) {
  232. rate = sspclk / freq / divide;
  233. if (rate <= 256)
  234. break;
  235. }
  236. tgtclk = sspclk / divide / rate;
  237. while (tgtclk > freq) {
  238. rate++;
  239. tgtclk = sspclk / divide / rate;
  240. }
  241. if (rate > 256)
  242. rate = 256;
  243. /* Always set timeout the maximum */
  244. reg = SSP_TIMING_TIMEOUT_MASK |
  245. (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
  246. ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
  247. writel(reg, &ssp_regs->hw_ssp_timing);
  248. debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
  249. bus, tgtclk, freq);
  250. }
  251. void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
  252. {
  253. struct mxs_clkctrl_regs *clkctrl_regs =
  254. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  255. uint32_t fp, x, k_rest, k_best, x_best, tk;
  256. int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
  257. if (freq == 0)
  258. return;
  259. #if defined(CONFIG_MX23)
  260. writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
  261. #elif defined(CONFIG_MX28)
  262. writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
  263. #endif
  264. /*
  265. * / 18 \ 1 1
  266. * freq kHz = | 480000000 Hz * -- | * --- * ------
  267. * \ x / k 1000
  268. *
  269. * 480000000 Hz 18
  270. * ------------ * --
  271. * freq kHz x
  272. * k = -------------------
  273. * 1000
  274. */
  275. fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
  276. for (x = 18; x <= 35; x++) {
  277. tk = fp / x;
  278. if ((tk / 1000 == 0) || (tk / 1000 > 255))
  279. continue;
  280. k_rest = tk % 1000;
  281. if (k_rest < (k_best_l % 1000)) {
  282. k_best_l = tk;
  283. x_best_l = x;
  284. }
  285. if (k_rest > (k_best_t % 1000)) {
  286. k_best_t = tk;
  287. x_best_t = x;
  288. }
  289. }
  290. if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
  291. k_best = k_best_l;
  292. x_best = x_best_l;
  293. } else {
  294. k_best = k_best_t;
  295. x_best = x_best_t;
  296. }
  297. k_best /= 1000;
  298. #if defined(CONFIG_MX23)
  299. writeb(CLKCTRL_FRAC_CLKGATE,
  300. &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
  301. writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
  302. &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
  303. writeb(CLKCTRL_FRAC_CLKGATE,
  304. &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
  305. writel(CLKCTRL_PIX_CLKGATE,
  306. &clkctrl_regs->hw_clkctrl_pix_set);
  307. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
  308. CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
  309. k_best << CLKCTRL_PIX_DIV_OFFSET);
  310. while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
  311. ;
  312. #elif defined(CONFIG_MX28)
  313. writeb(CLKCTRL_FRAC_CLKGATE,
  314. &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
  315. writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
  316. &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
  317. writeb(CLKCTRL_FRAC_CLKGATE,
  318. &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
  319. writel(CLKCTRL_DIS_LCDIF_CLKGATE,
  320. &clkctrl_regs->hw_clkctrl_lcdif_set);
  321. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
  322. CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
  323. k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
  324. while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
  325. ;
  326. #endif
  327. }
  328. uint32_t mxc_get_clock(enum mxc_clock clk)
  329. {
  330. switch (clk) {
  331. case MXC_ARM_CLK:
  332. return mxs_get_pclk() * 1000000;
  333. case MXC_GPMI_CLK:
  334. return mxs_get_gpmiclk() * 1000000;
  335. case MXC_AHB_CLK:
  336. case MXC_IPG_CLK:
  337. return mxs_get_hclk() * 1000000;
  338. case MXC_EMI_CLK:
  339. return mxs_get_emiclk();
  340. case MXC_IO0_CLK:
  341. return mxs_get_ioclk(MXC_IOCLK0);
  342. case MXC_IO1_CLK:
  343. return mxs_get_ioclk(MXC_IOCLK1);
  344. case MXC_XTAL_CLK:
  345. return XTAL_FREQ_KHZ * 1000;
  346. case MXC_SSP0_CLK:
  347. return mxs_get_sspclk(MXC_SSPCLK0);
  348. #ifdef CONFIG_MX28
  349. case MXC_SSP1_CLK:
  350. return mxs_get_sspclk(MXC_SSPCLK1);
  351. case MXC_SSP2_CLK:
  352. return mxs_get_sspclk(MXC_SSPCLK2);
  353. case MXC_SSP3_CLK:
  354. return mxs_get_sspclk(MXC_SSPCLK3);
  355. #endif
  356. }
  357. return 0;
  358. }