board.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Bosch Guardian
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  9. */
  10. #include <common.h>
  11. #include <cpsw.h>
  12. #include <dm.h>
  13. #include <env_internal.h>
  14. #include <errno.h>
  15. #include <i2c.h>
  16. #include <led.h>
  17. #include <miiphy.h>
  18. #include <panel.h>
  19. #include <power/tps65217.h>
  20. #include <power/tps65910.h>
  21. #include <spl.h>
  22. #include <watchdog.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/cpu.h>
  25. #include <asm/arch/ddr_defs.h>
  26. #include <asm/arch/gpio.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/mem.h>
  29. #include <asm/arch/mmc_host_def.h>
  30. #include <asm/arch/omap.h>
  31. #include <asm/arch/sys_proto.h>
  32. #include <asm/emif.h>
  33. #include <asm/gpio.h>
  34. #include <asm/io.h>
  35. #include "board.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  38. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39. static const struct ddr_data ddr3_data = {
  40. .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  41. .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  42. .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  43. .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  44. };
  45. static const struct cmd_control ddr3_cmd_ctrl_data = {
  46. .cmd0csratio = MT41K128M16JT125K_RATIO,
  47. .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  48. .cmd1csratio = MT41K128M16JT125K_RATIO,
  49. .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  50. .cmd2csratio = MT41K128M16JT125K_RATIO,
  51. .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  52. };
  53. static struct emif_regs ddr3_emif_reg_data = {
  54. .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  55. .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  56. .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  57. .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  58. .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  59. .zq_config = MT41K128M16JT125K_ZQ_CFG,
  60. .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  61. };
  62. #define OSC (V_OSCK / 1000000)
  63. const struct dpll_params dpll_ddr = {
  64. 400, OSC - 1, 1, -1, -1, -1, -1};
  65. void am33xx_spl_board_init(void)
  66. {
  67. int mpu_vdd;
  68. int usb_cur_lim;
  69. /* Get the frequency */
  70. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  71. if (i2c_probe(TPS65217_CHIP_PM))
  72. return;
  73. /*
  74. * Increase USB current limit to 1300mA or 1800mA and set
  75. * the MPU voltage controller as needed.
  76. */
  77. if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  78. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  79. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  80. } else {
  81. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  82. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  83. }
  84. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  85. TPS65217_POWER_PATH,
  86. usb_cur_lim,
  87. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  88. puts("tps65217_reg_write failure\n");
  89. /* Set DCDC3 (CORE) voltage to 1.125V */
  90. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  91. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  92. puts("tps65217_voltage_update failure\n");
  93. return;
  94. }
  95. /* Set CORE Frequencies to OPP100 */
  96. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  97. /* Set DCDC2 (MPU) voltage */
  98. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  99. puts("tps65217_voltage_update failure\n");
  100. return;
  101. }
  102. /*
  103. * Set LDO3 to 1.8V and LDO4 to 3.3V
  104. */
  105. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  106. TPS65217_DEFLS1,
  107. TPS65217_LDO_VOLTAGE_OUT_1_8,
  108. TPS65217_LDO_MASK))
  109. puts("tps65217_reg_write failure\n");
  110. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  111. TPS65217_DEFLS2,
  112. TPS65217_LDO_VOLTAGE_OUT_3_3,
  113. TPS65217_LDO_MASK))
  114. puts("tps65217_reg_write failure\n");
  115. /* Set MPU Frequency to what we detected now that voltages are set */
  116. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  117. }
  118. const struct dpll_params *get_dpll_ddr_params(void)
  119. {
  120. enable_i2c0_pin_mux();
  121. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  122. return &dpll_ddr;
  123. }
  124. void set_uart_mux_conf(void)
  125. {
  126. enable_uart0_pin_mux();
  127. }
  128. void set_mux_conf_regs(void)
  129. {
  130. enable_board_pin_mux();
  131. }
  132. const struct ctrl_ioregs ioregs = {
  133. .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  134. .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  135. .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  136. .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  137. .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  138. };
  139. void sdram_init(void)
  140. {
  141. config_ddr(400, &ioregs,
  142. &ddr3_data,
  143. &ddr3_cmd_ctrl_data,
  144. &ddr3_emif_reg_data, 0);
  145. }
  146. #endif
  147. int board_init(void)
  148. {
  149. save_omap_boot_params();
  150. #if defined(CONFIG_HW_WATCHDOG)
  151. hw_watchdog_init();
  152. #endif
  153. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  154. #ifdef CONFIG_MTD_RAW_NAND
  155. gpmc_init();
  156. #endif
  157. return 0;
  158. }
  159. #ifdef CONFIG_BOARD_LATE_INIT
  160. static void set_bootmode_env(void)
  161. {
  162. char *boot_device_name = NULL;
  163. char *boot_mode_gpio = "gpio@44e07000_14";
  164. int ret;
  165. int value;
  166. struct gpio_desc boot_mode_desc;
  167. switch (gd->arch.omap_boot_device) {
  168. case BOOT_DEVICE_NAND:
  169. boot_device_name = "nand";
  170. break;
  171. case BOOT_DEVICE_USBETH:
  172. boot_device_name = "usbeth";
  173. break;
  174. default:
  175. break;
  176. }
  177. if (boot_device_name)
  178. env_set("boot_device", boot_device_name);
  179. ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
  180. if (ret) {
  181. printf("%s is not found\n", boot_mode_gpio);
  182. goto err;
  183. }
  184. ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
  185. if (ret && ret != -EBUSY) {
  186. printf("requesting gpio: %s failed\n", boot_mode_gpio);
  187. goto err;
  188. }
  189. value = dm_gpio_get_value(&boot_mode_desc);
  190. value ? env_set("swi_status", "0") : env_set("swi_status", "1");
  191. return;
  192. err:
  193. env_set("swi_status", "err");
  194. }
  195. int board_late_init(void)
  196. {
  197. #ifdef CONFIG_LED_GPIO
  198. led_default_state();
  199. #endif
  200. set_bootmode_env();
  201. return 0;
  202. }
  203. #endif /* CONFIG_BOARD_LATE_INIT */