imxrt_sdram.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019
  4. * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <ram.h>
  10. #include <asm/io.h>
  11. #include <linux/err.h>
  12. /* SDRAM Command Code */
  13. #define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
  14. #define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
  15. #define SD_CC_IRD 0x8 /* IP command - Read */
  16. #define SD_CC_IWR 0x9 /* IP command - Write */
  17. #define SD_CC_IMS 0xA /* IP command - Set Mode Register */
  18. #define SD_CC_IACT 0xB /* IP command - ACTIVE */
  19. #define SD_CC_IAF 0xC /* IP command - Auto Refresh */
  20. #define SD_CC_ISF 0xD /* IP Command - Self Refresh */
  21. #define SD_CC_IPRE 0xE /* IP command - Precharge */
  22. #define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
  23. #define SEMC_MCR_MDIS BIT(1)
  24. #define SEMC_MCR_DQSMD BIT(2)
  25. #define SEMC_INTR_IPCMDERR BIT(1)
  26. #define SEMC_INTR_IPCMDDONE BIT(0)
  27. #define SEMC_IPCMD_KEY 0xA55A0000
  28. struct imxrt_semc_regs {
  29. /* 0x0 */
  30. u32 mcr;
  31. u32 iocr;
  32. u32 bmcr0;
  33. u32 bmcr1;
  34. u32 br[9];
  35. /* 0x34 */
  36. u32 res1;
  37. u32 inten;
  38. u32 intr;
  39. /* 0x40 */
  40. u32 sdramcr0;
  41. u32 sdramcr1;
  42. u32 sdramcr2;
  43. u32 sdramcr3;
  44. /* 0x50 */
  45. u32 nandcr0;
  46. u32 nandcr1;
  47. u32 nandcr2;
  48. u32 nandcr3;
  49. /* 0x60 */
  50. u32 norcr0;
  51. u32 norcr1;
  52. u32 norcr2;
  53. u32 norcr3;
  54. /* 0x70 */
  55. u32 sramcr0;
  56. u32 sramcr1;
  57. u32 sramcr2;
  58. u32 sramcr3;
  59. /* 0x80 */
  60. u32 dbicr0;
  61. u32 dbicr1;
  62. u32 res2[2];
  63. /* 0x90 */
  64. u32 ipcr0;
  65. u32 ipcr1;
  66. u32 ipcr2;
  67. u32 ipcmd;
  68. /* 0xA0 */
  69. u32 iptxdat;
  70. u32 res3[3];
  71. /* 0xB0 */
  72. u32 iprxdat;
  73. u32 res4[3];
  74. /* 0xC0 */
  75. u32 sts[16];
  76. };
  77. #define SEMC_IOCR_MUX_A8_SHIFT 0
  78. #define SEMC_IOCR_MUX_CSX0_SHIFT 3
  79. #define SEMC_IOCR_MUX_CSX1_SHIFT 6
  80. #define SEMC_IOCR_MUX_CSX2_SHIFT 9
  81. #define SEMC_IOCR_MUX_CSX3_SHIFT 12
  82. #define SEMC_IOCR_MUX_RDY_SHIFT 15
  83. struct imxrt_sdram_mux {
  84. u8 a8;
  85. u8 csx0;
  86. u8 csx1;
  87. u8 csx2;
  88. u8 csx3;
  89. u8 rdy;
  90. };
  91. #define SEMC_SDRAMCR0_PS_SHIFT 0
  92. #define SEMC_SDRAMCR0_BL_SHIFT 4
  93. #define SEMC_SDRAMCR0_COL_SHIFT 8
  94. #define SEMC_SDRAMCR0_CL_SHIFT 10
  95. struct imxrt_sdram_control {
  96. u8 memory_width;
  97. u8 burst_len;
  98. u8 no_columns;
  99. u8 cas_latency;
  100. };
  101. #define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
  102. #define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
  103. #define SEMC_SDRAMCR1_RFRC_SHIFT 8
  104. #define SEMC_SDRAMCR1_WRC_SHIFT 13
  105. #define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
  106. #define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
  107. #define SEMC_SDRAMCR2_SRRC_SHIFT 0
  108. #define SEMC_SDRAMCR2_REF2REF_SHIFT 8
  109. #define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
  110. #define SEMC_SDRAMCR2_ITO_SHIFT 24
  111. #define SEMC_SDRAMCR3_REN BIT(0)
  112. #define SEMC_SDRAMCR3_REBL_SHIFT 1
  113. #define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
  114. #define SEMC_SDRAMCR3_RT_SHIFT 16
  115. #define SEMC_SDRAMCR3_UT_SHIFT 24
  116. struct imxrt_sdram_timing {
  117. u8 pre2act;
  118. u8 act2rw;
  119. u8 rfrc;
  120. u8 wrc;
  121. u8 ckeoff;
  122. u8 act2pre;
  123. u8 srrc;
  124. u8 ref2ref;
  125. u8 act2act;
  126. u8 ito;
  127. u8 rebl;
  128. u8 prescale;
  129. u8 rt;
  130. u8 ut;
  131. };
  132. enum imxrt_semc_bank {
  133. SDRAM_BANK1,
  134. SDRAM_BANK2,
  135. SDRAM_BANK3,
  136. SDRAM_BANK4,
  137. MAX_SDRAM_BANK,
  138. };
  139. #define SEMC_BR_VLD_MASK 1
  140. #define SEMC_BR_MS_SHIFT 1
  141. struct bank_params {
  142. enum imxrt_semc_bank target_bank;
  143. u32 base_address;
  144. u32 memory_size;
  145. };
  146. struct imxrt_sdram_params {
  147. struct imxrt_semc_regs *base;
  148. struct imxrt_sdram_mux *sdram_mux;
  149. struct imxrt_sdram_control *sdram_control;
  150. struct imxrt_sdram_timing *sdram_timing;
  151. struct bank_params bank_params[MAX_SDRAM_BANK];
  152. u8 no_sdram_banks;
  153. };
  154. static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
  155. {
  156. do {
  157. readl(&regs->intr);
  158. if (regs->intr & SEMC_INTR_IPCMDDONE)
  159. return 0;
  160. if (regs->intr & SEMC_INTR_IPCMDERR)
  161. return -EIO;
  162. mdelay(50);
  163. } while (1);
  164. }
  165. static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
  166. u32 ipcmd, u32 wd, u32 *rd)
  167. {
  168. int ret;
  169. if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
  170. writel(wd, &regs->iptxdat);
  171. /* set slave address for every command as specified on RM */
  172. writel(mem_addr, &regs->ipcr0);
  173. /* execute command */
  174. writel(SEMC_IPCMD_KEY | ipcmd, &regs->ipcmd);
  175. ret = imxrt_sdram_wait_ipcmd_done(regs);
  176. if (ret < 0)
  177. return ret;
  178. if (ipcmd == SD_CC_IRD) {
  179. if (!rd)
  180. return -EINVAL;
  181. *rd = readl(&regs->iprxdat);
  182. }
  183. return 0;
  184. }
  185. int imxrt_sdram_init(struct udevice *dev)
  186. {
  187. struct imxrt_sdram_params *params = dev_get_platdata(dev);
  188. struct imxrt_sdram_mux *mux = params->sdram_mux;
  189. struct imxrt_sdram_control *ctrl = params->sdram_control;
  190. struct imxrt_sdram_timing *time = params->sdram_timing;
  191. struct imxrt_semc_regs *regs = params->base;
  192. struct bank_params *bank_params;
  193. u32 rd;
  194. int i;
  195. /* enable the SEMC controller */
  196. clrbits_le32(&regs->mcr, SEMC_MCR_MDIS);
  197. /* set DQS mode from DQS pad */
  198. setbits_le32(&regs->mcr, SEMC_MCR_DQSMD);
  199. for (i = 0, bank_params = params->bank_params;
  200. i < params->no_sdram_banks; bank_params++,
  201. i++)
  202. writel((bank_params->base_address & 0xfffff000)
  203. | bank_params->memory_size << SEMC_BR_MS_SHIFT
  204. | SEMC_BR_VLD_MASK,
  205. &regs->br[bank_params->target_bank]);
  206. writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
  207. | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
  208. | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
  209. | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
  210. | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
  211. | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
  212. &regs->iocr);
  213. writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
  214. | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
  215. | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
  216. | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
  217. &regs->sdramcr0);
  218. writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
  219. | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
  220. | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
  221. | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
  222. | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
  223. | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
  224. &regs->sdramcr1);
  225. writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
  226. | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
  227. | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
  228. | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
  229. &regs->sdramcr2);
  230. writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
  231. | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
  232. | time->rt << SEMC_SDRAMCR3_RT_SHIFT
  233. | time->ut << SEMC_SDRAMCR3_UT_SHIFT
  234. | SEMC_SDRAMCR3_REN,
  235. &regs->sdramcr3);
  236. writel(2, &regs->ipcr1);
  237. for (i = 0, bank_params = params->bank_params;
  238. i < params->no_sdram_banks; bank_params++,
  239. i++) {
  240. mdelay(250);
  241. imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
  242. 0, &rd);
  243. imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
  244. 0, &rd);
  245. imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
  246. 0, &rd);
  247. imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
  248. ctrl->burst_len | (ctrl->cas_latency << 4),
  249. &rd);
  250. mdelay(250);
  251. }
  252. return 0;
  253. }
  254. static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
  255. {
  256. struct imxrt_sdram_params *params = dev_get_platdata(dev);
  257. ofnode bank_node;
  258. u8 bank = 0;
  259. params->sdram_mux =
  260. (struct imxrt_sdram_mux *)
  261. dev_read_u8_array_ptr(dev,
  262. "fsl,sdram-mux",
  263. sizeof(struct imxrt_sdram_mux));
  264. if (!params->sdram_mux) {
  265. pr_err("fsl,sdram-mux not found");
  266. return -EINVAL;
  267. }
  268. params->sdram_control =
  269. (struct imxrt_sdram_control *)
  270. dev_read_u8_array_ptr(dev,
  271. "fsl,sdram-control",
  272. sizeof(struct imxrt_sdram_control));
  273. if (!params->sdram_control) {
  274. pr_err("fsl,sdram-control not found");
  275. return -EINVAL;
  276. }
  277. params->sdram_timing =
  278. (struct imxrt_sdram_timing *)
  279. dev_read_u8_array_ptr(dev,
  280. "fsl,sdram-timing",
  281. sizeof(struct imxrt_sdram_timing));
  282. if (!params->sdram_timing) {
  283. pr_err("fsl,sdram-timing not found");
  284. return -EINVAL;
  285. }
  286. dev_for_each_subnode(bank_node, dev) {
  287. struct bank_params *bank_params;
  288. char *bank_name;
  289. int ret;
  290. /* extract the bank index from DT */
  291. bank_name = (char *)ofnode_get_name(bank_node);
  292. strsep(&bank_name, "@");
  293. if (!bank_name) {
  294. pr_err("missing sdram bank index");
  295. return -EINVAL;
  296. }
  297. bank_params = &params->bank_params[bank];
  298. strict_strtoul(bank_name, 10,
  299. (unsigned long *)&bank_params->target_bank);
  300. if (bank_params->target_bank >= MAX_SDRAM_BANK) {
  301. pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
  302. bank_params->target_bank);
  303. return -EINVAL;
  304. }
  305. ret = ofnode_read_u32(bank_node,
  306. "fsl,memory-size",
  307. &bank_params->memory_size);
  308. if (ret < 0) {
  309. pr_err("fsl,memory-size not found");
  310. return -EINVAL;
  311. }
  312. ret = ofnode_read_u32(bank_node,
  313. "fsl,base-address",
  314. &bank_params->base_address);
  315. if (ret < 0) {
  316. pr_err("fsl,base-address not found");
  317. return -EINVAL;
  318. }
  319. debug("Found bank %s %u\n", bank_name,
  320. bank_params->target_bank);
  321. bank++;
  322. }
  323. params->no_sdram_banks = bank;
  324. debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
  325. return 0;
  326. }
  327. static int imxrt_semc_probe(struct udevice *dev)
  328. {
  329. struct imxrt_sdram_params *params = dev_get_platdata(dev);
  330. int ret;
  331. fdt_addr_t addr;
  332. addr = dev_read_addr(dev);
  333. if (addr == FDT_ADDR_T_NONE)
  334. return -EINVAL;
  335. params->base = (struct imxrt_semc_regs *)addr;
  336. #ifdef CONFIG_CLK
  337. struct clk clk;
  338. ret = clk_get_by_index(dev, 0, &clk);
  339. if (ret < 0)
  340. return ret;
  341. ret = clk_enable(&clk);
  342. if (ret) {
  343. dev_err(dev, "failed to enable clock\n");
  344. return ret;
  345. }
  346. #endif
  347. ret = imxrt_sdram_init(dev);
  348. if (ret)
  349. return ret;
  350. return 0;
  351. }
  352. static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
  353. {
  354. return 0;
  355. }
  356. static struct ram_ops imxrt_semc_ops = {
  357. .get_info = imxrt_semc_get_info,
  358. };
  359. static const struct udevice_id imxrt_semc_ids[] = {
  360. { .compatible = "fsl,imxrt-semc", .data = 0 },
  361. { }
  362. };
  363. U_BOOT_DRIVER(imxrt_semc) = {
  364. .name = "imxrt_semc",
  365. .id = UCLASS_RAM,
  366. .of_match = imxrt_semc_ids,
  367. .ops = &imxrt_semc_ops,
  368. .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
  369. .probe = imxrt_semc_probe,
  370. .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
  371. };