poplar.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017 Linaro
  4. * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <dm/platform_data/serial_pl01x.h>
  12. #include <asm/arch/hi3798cv200.h>
  13. #include <asm/armv8/mmu.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. static struct mm_region poplar_mem_map[] = {
  16. {
  17. .virt = 0x0UL,
  18. .phys = 0x0UL,
  19. .size = 0x80000000UL,
  20. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  21. PTE_BLOCK_INNER_SHARE
  22. }, {
  23. .virt = 0x80000000UL,
  24. .phys = 0x80000000UL,
  25. .size = 0x80000000UL,
  26. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27. PTE_BLOCK_NON_SHARE |
  28. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  29. }, {
  30. 0,
  31. }
  32. };
  33. struct mm_region *mem_map = poplar_mem_map;
  34. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  35. static const struct pl01x_serial_platdata serial_platdata = {
  36. .base = REG_BASE_UART0,
  37. .type = TYPE_PL010,
  38. .clock = 75000000,
  39. };
  40. U_BOOT_DEVICE(poplar_serial) = {
  41. .name = "serial_pl01x",
  42. .platdata = &serial_platdata,
  43. };
  44. #endif
  45. int checkboard(void)
  46. {
  47. puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
  48. return 0;
  49. }
  50. void reset_cpu(ulong addr)
  51. {
  52. psci_system_reset();
  53. }
  54. int dram_init(void)
  55. {
  56. gd->ram_size = get_ram_size(NULL, 0x80000000);
  57. return 0;
  58. }
  59. /*
  60. * Some linux kernel versions don't use memory before its load address, so to
  61. * be generic we just pretend it isn't there. In previous uboot versions we
  62. * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
  63. * could persist in memory and be left alone by the kernel.
  64. *
  65. * That led to a problem when mapping memory in older kernels. That PSCI code
  66. * now lies in memory below the kernel load offset; it therefore won't be
  67. * touched by the kernel, and by not specially reserving it we avoid the mapping
  68. * problem as well.
  69. *
  70. */
  71. #define KERNEL_TEXT_OFFSET 0x00080000
  72. int dram_init_banksize(void)
  73. {
  74. gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
  75. gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
  76. return 0;
  77. }
  78. static void usb2_phy_config(void)
  79. {
  80. const u32 config[] = {
  81. /* close EOP pre-emphasis. open data pre-emphasis */
  82. 0xa1001c,
  83. /* Rcomp = 150mW, increase DC level */
  84. 0xa00607,
  85. /* keep Rcomp working */
  86. 0xa10700,
  87. /* Icomp = 212mW, increase current drive */
  88. 0xa00aab,
  89. /* EMI fix: rx_active not stay 1 when error packets received */
  90. 0xa11140,
  91. /* Comp mode select */
  92. 0xa11041,
  93. /* adjust eye diagram */
  94. 0xa0098c,
  95. /* adjust eye diagram */
  96. 0xa10a0a,
  97. };
  98. int i;
  99. for (i = 0; i < ARRAY_SIZE(config); i++) {
  100. writel(config[i], PERI_CTRL_USB0);
  101. clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
  102. udelay(20);
  103. }
  104. }
  105. static void usb2_phy_init(void)
  106. {
  107. /* reset usb2 controller bus/utmi/roothub */
  108. setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
  109. USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
  110. udelay(200);
  111. /* reset usb2 phy por/utmi */
  112. setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
  113. udelay(200);
  114. /* open usb2 ref clk */
  115. setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
  116. udelay(300);
  117. /* cancel usb2 power on reset */
  118. clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
  119. udelay(500);
  120. usb2_phy_config();
  121. /* cancel usb2 port reset, wait comp circuit stable */
  122. clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
  123. mdelay(10);
  124. /* open usb2 controller clk */
  125. setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
  126. USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
  127. USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
  128. udelay(200);
  129. /* cancel usb2 control reset */
  130. clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
  131. USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
  132. udelay(200);
  133. }
  134. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  135. #include <env.h>
  136. #include <usb.h>
  137. #include <usb/dwc2_udc.h>
  138. #include <g_dnl.h>
  139. static struct dwc2_plat_otg_data poplar_otg_data = {
  140. .regs_otg = HIOTG_BASE_ADDR
  141. };
  142. static void set_usb_to_device(void)
  143. {
  144. setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
  145. }
  146. int board_usb_init(int index, enum usb_init_type init)
  147. {
  148. set_usb_to_device();
  149. return dwc2_udc_probe(&poplar_otg_data);
  150. }
  151. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  152. {
  153. if (!env_get("serial#"))
  154. g_dnl_set_serialnumber("0123456789POPLAR");
  155. return 0;
  156. }
  157. #endif
  158. int board_init(void)
  159. {
  160. usb2_phy_init();
  161. return 0;
  162. }