elgin_rv1108.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C)Copyright 2016 Rockchip Electronics Co., Ltd
  4. * Authors: Andy Yan <andy.yan@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <syscon.h>
  9. #include <asm/io.h>
  10. #include <asm/arch-rockchip/clock.h>
  11. #include <asm/arch-rockchip/grf_rv1108.h>
  12. #include <asm/arch-rockchip/hardware.h>
  13. #include <asm/gpio.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. int board_early_init_f(void)
  16. {
  17. struct rv1108_grf *grf;
  18. enum {
  19. GPIO3C3_SHIFT = 6,
  20. GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
  21. GPIO3C2_SHIFT = 4,
  22. GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
  23. GPIO2D2_SHIFT = 4,
  24. GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
  25. GPIO2D2_GPIO = 0,
  26. GPIO2D2_UART2_SOUT_M0,
  27. GPIO2D1_SHIFT = 2,
  28. GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
  29. GPIO2D1_GPIO = 0,
  30. GPIO2D1_UART2_SIN_M0,
  31. };
  32. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  33. /* Elgin board use UART2 m0 for debug*/
  34. rk_clrsetreg(&grf->gpio2d_iomux,
  35. GPIO2D2_MASK | GPIO2D1_MASK,
  36. GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
  37. GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
  38. rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
  39. return 0;
  40. }
  41. #define MODEM_ENABLE_GPIO 111
  42. int rk_board_late_init(void)
  43. {
  44. gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
  45. gpio_direction_output(MODEM_ENABLE_GPIO, 0);
  46. return 0;
  47. }
  48. int dram_init(void)
  49. {
  50. gd->ram_size = 0x8000000;
  51. return 0;
  52. }
  53. int dram_init_banksize(void)
  54. {
  55. gd->bd->bi_dram[0].start = 0x60000000;
  56. gd->bd->bi_dram[0].size = 0x8000000;
  57. return 0;
  58. }