mtrr.h 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. *
  5. * From Coreboot file of the same name
  6. */
  7. #ifndef _ASM_MTRR_H
  8. #define _ASM_MTRR_H
  9. /* MTRR region types */
  10. #define MTRR_TYPE_UNCACHEABLE 0
  11. #define MTRR_TYPE_WRCOMB 1
  12. #define MTRR_TYPE_WRTHROUGH 4
  13. #define MTRR_TYPE_WRPROT 5
  14. #define MTRR_TYPE_WRBACK 6
  15. #define MTRR_TYPE_COUNT 7
  16. #define MTRR_CAP_MSR 0x0fe
  17. #define MTRR_DEF_TYPE_MSR 0x2ff
  18. #define MTRR_CAP_SMRR (1 << 11)
  19. #define MTRR_CAP_WC (1 << 10)
  20. #define MTRR_CAP_FIX (1 << 8)
  21. #define MTRR_CAP_VCNT_MASK 0xff
  22. #define MTRR_DEF_TYPE_MASK 0xff
  23. #define MTRR_DEF_TYPE_EN (1 << 11)
  24. #define MTRR_DEF_TYPE_FIX_EN (1 << 10)
  25. #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
  26. #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
  27. #define MTRR_PHYS_MASK_VALID (1 << 11)
  28. #define MTRR_BASE_TYPE_MASK 0x7
  29. /* Number of MTRRs supported */
  30. #define MTRR_COUNT 8
  31. #define NUM_FIXED_MTRRS 11
  32. #define RANGES_PER_FIXED_MTRR 8
  33. #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
  34. #define MTRR_FIX_64K_00000_MSR 0x250
  35. #define MTRR_FIX_16K_80000_MSR 0x258
  36. #define MTRR_FIX_16K_A0000_MSR 0x259
  37. #define MTRR_FIX_4K_C0000_MSR 0x268
  38. #define MTRR_FIX_4K_C8000_MSR 0x269
  39. #define MTRR_FIX_4K_D0000_MSR 0x26a
  40. #define MTRR_FIX_4K_D8000_MSR 0x26b
  41. #define MTRR_FIX_4K_E0000_MSR 0x26c
  42. #define MTRR_FIX_4K_E8000_MSR 0x26d
  43. #define MTRR_FIX_4K_F0000_MSR 0x26e
  44. #define MTRR_FIX_4K_F8000_MSR 0x26f
  45. #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t)
  46. #if !defined(__ASSEMBLY__)
  47. /**
  48. * Information about the previous MTRR state, set up by mtrr_open()
  49. *
  50. * @deftype: Previous value of MTRR_DEF_TYPE_MSR
  51. * @enable_cache: true if cache was enabled
  52. */
  53. struct mtrr_state {
  54. uint64_t deftype;
  55. bool enable_cache;
  56. };
  57. /**
  58. * mtrr_open() - Prepare to adjust MTRRs
  59. *
  60. * Use mtrr_open() passing in a structure - this function will init it. Then
  61. * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
  62. * possibly the cache.
  63. *
  64. * @state: Empty structure to pass in to hold settings
  65. * @do_caches: true to disable caches before opening
  66. */
  67. void mtrr_open(struct mtrr_state *state, bool do_caches);
  68. /**
  69. * mtrr_open() - Clean up after adjusting MTRRs, and enable them
  70. *
  71. * This uses the structure containing information returned from mtrr_open().
  72. *
  73. * @state: Structure from mtrr_open()
  74. * @state: true to restore cache state to that before mtrr_open()
  75. */
  76. void mtrr_close(struct mtrr_state *state, bool do_caches);
  77. /**
  78. * mtrr_add_request() - Add a new MTRR request
  79. *
  80. * This adds a request for a memory region to be set up in a particular way.
  81. *
  82. * @type: Requested type (MTRR_TYPE_)
  83. * @start: Start address
  84. * @size: Size
  85. *
  86. * @return: 0 on success, non-zero on failure
  87. */
  88. int mtrr_add_request(int type, uint64_t start, uint64_t size);
  89. /**
  90. * mtrr_commit() - set up the MTRR registers based on current requests
  91. *
  92. * This sets up MTRRs for the available DRAM and the requests received so far.
  93. * It must be called with caches disabled.
  94. *
  95. * @do_caches: true if caches are currently on
  96. *
  97. * @return: 0 on success, non-zero on failure
  98. */
  99. int mtrr_commit(bool do_caches);
  100. /**
  101. * mtrr_set_next_var() - set up a variable MTRR
  102. *
  103. * This finds the first free variable MTRR and sets to the given area
  104. *
  105. * @type: Requested type (MTRR_TYPE_)
  106. * @start: Start address
  107. * @size: Size
  108. * @return 0 on success, -ENOSPC if there are no more MTRRs
  109. */
  110. int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
  111. #endif
  112. #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
  113. # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
  114. #endif
  115. #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
  116. # error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
  117. #endif
  118. #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
  119. #endif