sdram_arria10.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
  4. */
  5. #ifndef _SOCFPGA_SDRAM_ARRIA10_H_
  6. #define _SOCFPGA_SDRAM_ARRIA10_H_
  7. #ifndef __ASSEMBLY__
  8. int ddr_calibration_sequence(void);
  9. struct socfpga_ecc_hmc {
  10. u32 ip_rev_id;
  11. u32 _pad_0x4_0x7;
  12. u32 ddrioctrl;
  13. u32 ddrcalstat;
  14. u32 mpr_0beat1;
  15. u32 mpr_1beat1;
  16. u32 mpr_2beat1;
  17. u32 mpr_3beat1;
  18. u32 mpr_4beat1;
  19. u32 mpr_5beat1;
  20. u32 mpr_6beat1;
  21. u32 mpr_7beat1;
  22. u32 mpr_8beat1;
  23. u32 mpr_0beat2;
  24. u32 mpr_1beat2;
  25. u32 mpr_2beat2;
  26. u32 mpr_3beat2;
  27. u32 mpr_4beat2;
  28. u32 mpr_5beat2;
  29. u32 mpr_6beat2;
  30. u32 mpr_7beat2;
  31. u32 mpr_8beat2;
  32. u32 _pad_0x58_0x5f[2];
  33. u32 auto_precharge;
  34. u32 _pad_0x64_0xff[39];
  35. u32 eccctrl;
  36. u32 eccctrl2;
  37. u32 _pad_0x108_0x10f[2];
  38. u32 errinten;
  39. u32 errintens;
  40. u32 errintenr;
  41. u32 intmode;
  42. u32 intstat;
  43. u32 diaginttest;
  44. u32 modstat;
  45. u32 derraddra;
  46. u32 serraddra;
  47. u32 _pad_0x134_0x137;
  48. u32 autowb_corraddr;
  49. u32 serrcntreg;
  50. u32 autowb_drop_cntreg;
  51. u32 _pad_0x144_0x147;
  52. u32 ecc_reg2wreccdatabus;
  53. u32 ecc_rdeccdata2regbus;
  54. u32 ecc_reg2rdeccdatabus;
  55. u32 _pad_0x154_0x15f[3];
  56. u32 ecc_diagon;
  57. u32 ecc_decstat;
  58. u32 _pad_0x168_0x16f[2];
  59. u32 ecc_errgenaddr_0;
  60. u32 ecc_errgenaddr_1;
  61. u32 ecc_errgenaddr_2;
  62. u32 ecc_errgenaddr_3;
  63. };
  64. struct socfpga_noc_ddr_scheduler {
  65. u32 ddr_t_main_scheduler_id_coreid;
  66. u32 ddr_t_main_scheduler_id_revisionid;
  67. u32 ddr_t_main_scheduler_ddrconf;
  68. u32 ddr_t_main_scheduler_ddrtiming;
  69. u32 ddr_t_main_scheduler_ddrmode;
  70. u32 ddr_t_main_scheduler_readlatency;
  71. u32 _pad_0x20_0x34[8];
  72. u32 ddr_t_main_scheduler_activate;
  73. u32 ddr_t_main_scheduler_devtodev;
  74. };
  75. /*
  76. * OCRAM firewall
  77. */
  78. struct socfpga_noc_fw_ocram {
  79. u32 enable;
  80. u32 enable_set;
  81. u32 enable_clear;
  82. u32 region0;
  83. u32 region1;
  84. u32 region2;
  85. u32 region3;
  86. u32 region4;
  87. u32 region5;
  88. };
  89. /* for master such as MPU and FPGA */
  90. struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
  91. u32 enable;
  92. u32 enable_set;
  93. u32 enable_clear;
  94. u32 _pad_0xc_0xf;
  95. u32 mpuregion0addr;
  96. u32 mpuregion1addr;
  97. u32 mpuregion2addr;
  98. u32 mpuregion3addr;
  99. u32 fpga2sdram0region0addr;
  100. u32 fpga2sdram0region1addr;
  101. u32 fpga2sdram0region2addr;
  102. u32 fpga2sdram0region3addr;
  103. u32 fpga2sdram1region0addr;
  104. u32 fpga2sdram1region1addr;
  105. u32 fpga2sdram1region2addr;
  106. u32 fpga2sdram1region3addr;
  107. u32 fpga2sdram2region0addr;
  108. u32 fpga2sdram2region1addr;
  109. u32 fpga2sdram2region2addr;
  110. u32 fpga2sdram2region3addr;
  111. };
  112. /* for L3 master */
  113. struct socfpga_noc_fw_ddr_l3 {
  114. u32 enable;
  115. u32 enable_set;
  116. u32 enable_clear;
  117. u32 hpsregion0addr;
  118. u32 hpsregion1addr;
  119. u32 hpsregion2addr;
  120. u32 hpsregion3addr;
  121. u32 hpsregion4addr;
  122. u32 hpsregion5addr;
  123. u32 hpsregion6addr;
  124. u32 hpsregion7addr;
  125. };
  126. struct socfpga_io48_mmr {
  127. u32 dbgcfg0;
  128. u32 dbgcfg1;
  129. u32 dbgcfg2;
  130. u32 dbgcfg3;
  131. u32 dbgcfg4;
  132. u32 dbgcfg5;
  133. u32 dbgcfg6;
  134. u32 reserve0;
  135. u32 reserve1;
  136. u32 reserve2;
  137. u32 ctrlcfg0;
  138. u32 ctrlcfg1;
  139. u32 ctrlcfg2;
  140. u32 ctrlcfg3;
  141. u32 ctrlcfg4;
  142. u32 ctrlcfg5;
  143. u32 ctrlcfg6;
  144. u32 ctrlcfg7;
  145. u32 ctrlcfg8;
  146. u32 ctrlcfg9;
  147. u32 dramtiming0;
  148. u32 dramodt0;
  149. u32 dramodt1;
  150. u32 sbcfg0;
  151. u32 sbcfg1;
  152. u32 sbcfg2;
  153. u32 sbcfg3;
  154. u32 sbcfg4;
  155. u32 sbcfg5;
  156. u32 sbcfg6;
  157. u32 sbcfg7;
  158. u32 caltiming0;
  159. u32 caltiming1;
  160. u32 caltiming2;
  161. u32 caltiming3;
  162. u32 caltiming4;
  163. u32 caltiming5;
  164. u32 caltiming6;
  165. u32 caltiming7;
  166. u32 caltiming8;
  167. u32 caltiming9;
  168. u32 caltiming10;
  169. u32 dramaddrw;
  170. u32 sideband0;
  171. u32 sideband1;
  172. u32 sideband2;
  173. u32 sideband3;
  174. u32 sideband4;
  175. u32 sideband5;
  176. u32 sideband6;
  177. u32 sideband7;
  178. u32 sideband8;
  179. u32 sideband9;
  180. u32 sideband10;
  181. u32 sideband11;
  182. u32 sideband12;
  183. u32 sideband13;
  184. u32 sideband14;
  185. u32 sideband15;
  186. u32 dramsts;
  187. u32 dbgdone;
  188. u32 dbgsignals;
  189. u32 dbgreset;
  190. u32 dbgmatch;
  191. u32 counter0mask;
  192. u32 counter1mask;
  193. u32 counter0match;
  194. u32 counter1match;
  195. u32 niosreserve0;
  196. u32 niosreserve1;
  197. u32 niosreserve2;
  198. };
  199. #endif /*__ASSEMBLY__ */
  200. #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
  201. #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24
  202. #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
  203. #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT 19
  204. #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
  205. #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT 14
  206. #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
  207. #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT 9
  208. #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
  209. #define IO48_MMR_CTRLCFG0_AC_POS_SHIFT 7
  210. #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
  211. #define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT 4
  212. #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
  213. #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
  214. #define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM BIT(30)
  215. #define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM BIT(29)
  216. #define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM BIT(28)
  217. #define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM BIT(27)
  218. #define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM BIT(26)
  219. #define IO48_MMR_CTRLCFG1_DQSTRK_EN BIT(25)
  220. #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
  221. #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT 19
  222. #define IO48_MMR_CTRLCFG1_REORDER_READ BIT(18)
  223. #define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA BIT(17)
  224. #define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA BIT(16)
  225. #define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA BIT(15)
  226. #define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA BIT(14)
  227. #define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA BIT(13)
  228. #define IO48_MMR_CTRLCFG1_REORDER_DATA BIT(12)
  229. #define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC BIT(11)
  230. #define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC BIT(10)
  231. #define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC BIT(9)
  232. #define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC BIT(8)
  233. #define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC BIT(7)
  234. #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
  235. #define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT 5
  236. #define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F
  237. #define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0
  238. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000
  239. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT 24
  240. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000
  241. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT 18
  242. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000
  243. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT 12
  244. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0
  245. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT 6
  246. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F
  247. #define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0
  248. #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000
  249. #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT 24
  250. #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000
  251. #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT 18
  252. #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000
  253. #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT 12
  254. #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0
  255. #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT 6
  256. #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F
  257. #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0
  258. #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000
  259. #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT 24
  260. #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000
  261. #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT 18
  262. #define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000
  263. #define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT 12
  264. #define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0
  265. #define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT 6
  266. #define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F
  267. #define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0
  268. #define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000
  269. #define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT 24
  270. #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000
  271. #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT 18
  272. #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000
  273. #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT 12
  274. #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0
  275. #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT 6
  276. #define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F
  277. #define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0
  278. #define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000
  279. #define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT 26
  280. #define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000
  281. #define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT 18
  282. #define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000
  283. #define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT 12
  284. #define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0
  285. #define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT 6
  286. #define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F
  287. #define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0
  288. #define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF
  289. #define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0
  290. #define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000
  291. #define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT 16
  292. #define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000
  293. #define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT 14
  294. #define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00
  295. #define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT 10
  296. #define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0
  297. #define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT 5
  298. #define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F
  299. #define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0
  300. #define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
  301. #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK BIT(0)
  302. #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK BIT(1)
  303. #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK BIT(0)
  304. #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK BIT(1)
  305. #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK BIT(16)
  306. #define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
  307. #define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK BIT(8)
  308. #define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK BIT(0)
  309. #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK BIT(8)
  310. #define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK BIT(0)
  311. #define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE 8
  312. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
  313. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
  314. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
  315. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
  316. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
  317. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
  318. #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
  319. #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
  320. #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
  321. #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
  322. #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
  323. #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
  324. #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
  325. #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
  326. #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
  327. #define ALT_NOC_FW_DDR_END_ADDR_LSB 16
  328. #define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF
  329. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK BIT(0)
  330. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK BIT(1)
  331. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK BIT(2)
  332. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK BIT(3)
  333. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK BIT(4)
  334. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK BIT(5)
  335. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK BIT(6)
  336. #define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK BIT(7)
  337. #define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK BIT(0)
  338. #define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK BIT(1)
  339. #define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK BIT(2)
  340. #define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK BIT(3)
  341. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK BIT(4)
  342. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK BIT(5)
  343. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK BIT(6)
  344. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK BIT(7)
  345. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK BIT(8)
  346. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK BIT(9)
  347. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK BIT(10)
  348. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK BIT(11)
  349. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK BIT(12)
  350. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK BIT(13)
  351. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK BIT(14)
  352. #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK BIT(15)
  353. #define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F
  354. #endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */