clock_manager_gen5.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef _CLOCK_MANAGER_GEN5_H_
  6. #define _CLOCK_MANAGER_GEN5_H_
  7. #ifndef __ASSEMBLY__
  8. struct cm_config {
  9. /* main group */
  10. u32 main_vco_base;
  11. u32 mpuclk;
  12. u32 mainclk;
  13. u32 dbgatclk;
  14. u32 mainqspiclk;
  15. u32 mainnandsdmmcclk;
  16. u32 cfg2fuser0clk;
  17. u32 maindiv;
  18. u32 dbgdiv;
  19. u32 tracediv;
  20. u32 l4src;
  21. /* peripheral group */
  22. u32 peri_vco_base;
  23. u32 emac0clk;
  24. u32 emac1clk;
  25. u32 perqspiclk;
  26. u32 pernandsdmmcclk;
  27. u32 perbaseclk;
  28. u32 s2fuser1clk;
  29. u32 perdiv;
  30. u32 gpiodiv;
  31. u32 persrc;
  32. /* sdram pll group */
  33. u32 sdram_vco_base;
  34. u32 ddrdqsclk;
  35. u32 ddr2xdqsclk;
  36. u32 ddrdqclk;
  37. u32 s2fuser2clk;
  38. /* altera group */
  39. u32 altera_grp_mpuclk;
  40. };
  41. /* Clock manager group */
  42. #define CLKMGR_GEN5_CTRL 0x00
  43. #define CLKMGR_GEN5_BYPASS 0x04
  44. #define CLKMGR_GEN5_INTER 0x08
  45. #define CLKMGR_GEN5_STAT 0x14
  46. /* MainPLL group */
  47. #define CLKMGR_GEN5_MAINPLL_VCO 0x40
  48. #define CLKMGR_GEN5_MAINPLL_MISC 0x44
  49. #define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48
  50. #define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c
  51. #define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50
  52. #define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54
  53. #define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58
  54. #define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c
  55. #define CLKMGR_GEN5_MAINPLL_EN 0x60
  56. #define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64
  57. #define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68
  58. #define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c
  59. #define CLKMGR_GEN5_MAINPLL_L4SRC 0x70
  60. /* Peripheral PLL group */
  61. #define CLKMGR_GEN5_PERPLL_VCO 0x80
  62. #define CLKMGR_GEN5_PERPLL_MISC 0x84
  63. #define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88
  64. #define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c
  65. #define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90
  66. #define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94
  67. #define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98
  68. #define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c
  69. #define CLKMGR_GEN5_PERPLL_EN 0xa0
  70. #define CLKMGR_GEN5_PERPLL_DIV 0xa4
  71. #define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8
  72. #define CLKMGR_GEN5_PERPLL_SRC 0xac
  73. /* SDRAM PLL group */
  74. #define CLKMGR_GEN5_SDRPLL_VCO 0xc0
  75. #define CLKMGR_GEN5_SDRPLL_CTRL 0xc4
  76. #define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8
  77. #define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc
  78. #define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0
  79. #define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4
  80. #define CLKMGR_GEN5_SDRPLL_EN 0xd8
  81. /* Altera group */
  82. #define CLKMGR_GEN5_ALTR_MPUCLK 0xe0
  83. #define CLKMGR_GEN5_ALTR_MAINCLK 0xe4
  84. #define CLKMGR_STAT CLKMGR_GEN5_STAT
  85. #define CLKMGR_INTER CLKMGR_GEN5_INTER
  86. #define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
  87. /* Clock speed accessors */
  88. unsigned long cm_get_mpu_clk_hz(void);
  89. unsigned long cm_get_sdram_clk_hz(void);
  90. unsigned int cm_get_l4_sp_clk_hz(void);
  91. unsigned int cm_get_mmc_controller_clk_hz(void);
  92. unsigned int cm_get_qspi_controller_clk_hz(void);
  93. unsigned int cm_get_spi_controller_clk_hz(void);
  94. const unsigned int cm_get_osc_clk_hz(const int osc);
  95. const unsigned int cm_get_f2s_per_ref_clk_hz(void);
  96. const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
  97. /* Clock configuration accessors */
  98. int cm_basic_init(const struct cm_config * const cfg);
  99. const struct cm_config * const cm_get_default_config(void);
  100. #endif /* __ASSEMBLY__ */
  101. #define LOCKED_MASK \
  102. (CLKMGR_INTER_SDRPLLLOCKED_MASK | \
  103. CLKMGR_INTER_PERPLLLOCKED_MASK | \
  104. CLKMGR_INTER_MAINPLLLOCKED_MASK)
  105. #define CLKMGR_CTRL_SAFEMODE BIT(0)
  106. #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
  107. #define CLKMGR_BYPASS_PERPLLSRC BIT(4)
  108. #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
  109. #define CLKMGR_BYPASS_PERPLL BIT(3)
  110. #define CLKMGR_BYPASS_PERPLL_OFFSET 3
  111. #define CLKMGR_BYPASS_SDRPLLSRC BIT(2)
  112. #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
  113. #define CLKMGR_BYPASS_SDRPLL BIT(1)
  114. #define CLKMGR_BYPASS_SDRPLL_OFFSET 1
  115. #define CLKMGR_BYPASS_MAINPLL BIT(0)
  116. #define CLKMGR_BYPASS_MAINPLL_OFFSET 0
  117. #define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3)
  118. #define CLKMGR_INTER_PERPLLLOST_MASK BIT(4)
  119. #define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5)
  120. #define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6)
  121. #define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7)
  122. #define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8)
  123. #define CLKMGR_STAT_BUSY BIT(0)
  124. /* Main PLL */
  125. #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0)
  126. #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
  127. #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
  128. #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
  129. #define CLKMGR_MAINPLLGRP_VCO_EN BIT(1)
  130. #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
  131. #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
  132. #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
  133. #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
  134. #define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2)
  135. #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
  136. #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
  137. #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
  138. #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
  139. #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
  140. #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
  141. #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
  142. #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
  143. #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
  144. #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
  145. #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
  146. #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
  147. #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
  148. #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
  149. #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
  150. #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
  151. #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4)
  152. #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5)
  153. #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6)
  154. #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7)
  155. #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9)
  156. #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
  157. #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
  158. #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
  159. #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
  160. #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
  161. #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
  162. #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
  163. #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
  164. #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
  165. #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
  166. #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
  167. #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
  168. #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
  169. #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
  170. #define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0)
  171. #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
  172. #define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1)
  173. #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
  174. #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
  175. #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
  176. #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
  177. /* Per PLL */
  178. #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
  179. #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
  180. #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
  181. #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
  182. #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
  183. #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
  184. #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
  185. #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
  186. #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
  187. #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
  188. #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
  189. #define CLKMGR_VCO_SSRC_EOSC1 0x0
  190. #define CLKMGR_VCO_SSRC_EOSC2 0x1
  191. #define CLKMGR_VCO_SSRC_F2S 0x2
  192. #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
  193. #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
  194. #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
  195. #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
  196. #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
  197. #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
  198. #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
  199. #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
  200. #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
  201. #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
  202. #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
  203. #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
  204. #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
  205. #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
  206. #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
  207. #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
  208. #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
  209. #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
  210. #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
  211. #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
  212. #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
  213. #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
  214. #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
  215. #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
  216. #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
  217. #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
  218. #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
  219. #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
  220. #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
  221. #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
  222. #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
  223. #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
  224. #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
  225. #define CLKMGR_SDMMC_CLK_SRC_PER 0x2
  226. #define CLKMGR_QSPI_CLK_SRC_F2S 0x0
  227. #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
  228. #define CLKMGR_QSPI_CLK_SRC_PER 0x2
  229. /* SDR PLL */
  230. #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
  231. #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
  232. #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
  233. #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
  234. #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24)
  235. #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
  236. #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
  237. #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
  238. #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31)
  239. #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
  240. #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
  241. #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
  242. #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
  243. #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
  244. #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
  245. #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
  246. #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
  247. #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
  248. #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
  249. #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
  250. #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
  251. #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
  252. #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
  253. #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
  254. #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
  255. #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
  256. #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
  257. #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
  258. #endif /* _CLOCK_MANAGER_GEN5_H_ */